LMP7715, LMP7716, LMP7716Q
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SNOSAV0E – MARCH 2006 – REVISED MARCH 2013
Single and Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifiers
Check for Samples: LMP7715, LMP7716, LMP7716Q
FEATURES
DESCRIPTION
•
The LMP7715/LMP7716/LMP7716Q are single and
dual low noise, low offset, CMOS input, rail-to-rail
output precision amplifiers with high gain bandwidth
products. The LMP7715/LMP7716/LMP7716Q are
part of the LMP™ precision amplifier family and are
ideal for a variety of instrumentation applications.
1
23
Unless Otherwise Noted,
Typical Values at VS = 5V.
– Input Offset Voltage ±150 μV (Max)
– Input Bias Current 100 fA
– Input Voltage Noise 5.8 nV/√Hz
– Gain Bandwidth Product 17 MHz
– Supply Current (LMP7715) 1.15 mA
– Supply Current (LMP7716/LMP7716Q) 1.30
mA
– Supply Voltage Range 1.8V to 5.5V
– THD+N @ f = 1 kHz 0.001%
– Operating Temperature Range −40°C to
125°C
– Rail-to-rail Output Swing
– Space Saving SOT-23 Package (LMP7715)
– 8-Pin VSSOP Package
(LMP7716/LMP7716Q)
– LMP7716Q is AEC-Q100 Grade 1 Qualified
and is Manufactured on an Automotive
Grade Flow
APPLICATIONS
•
•
•
•
Active Filters and Buffers
Sensor Interface Applications
Transimpedance Amplifiers
Automotive
Utilizing
a
CMOS
input
stage,
the
LMP7715/LMP7716/LMP7716Q achieve an input bias
current of 100 fA, an input referred voltage noise of
5.8 nV/√Hz, and an input offset voltage of less than
±150
μV.
These
features
make
the
LMP7715/LMP7716/LMP7716Q superior choices for
precision applications.
Consuming only 1.15 mA of supply current, the
LMP7715 offers a high gain bandwidth product of 17
MHz, enabling accurate amplification at high closed
loop gains.
The LMP7715/LMP7716/LMP7716Q have a supply
voltage range of 1.8V to 5.5V, which makes these
ideal choices for portable low power applications with
low supply voltage requirements.
The LMP7715/LMP7716/LMP7716Q are built with
TI’s advanced VIP50 process technology. The
LMP7715 is offered in a 5-pin SOT-23 package and
the LMP7716/LMP7716Q is offered in an 8-pin
VSSOP.
The
LMP7716Q
incorporates
enhanced
manufacturing and support processes for the
automotive market, including defect detection
methodologies. Reliability qualification is compliant
with the requirements and temperature grades
defined in the AEC-Q100 standard.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMP7715, LMP7716, LMP7716Q
SNOSAV0E – MARCH 2006 – REVISED MARCH 2013
www.ti.com
Typical Performance
PERCENTAGE (%)
20
100
VS = 5V
VS = 5.5V
VCM = VS/2
UNITS TESTED: 10,000
VOLTAGE NOISE (nV/ Hz)
25
15
10
5
0
-200
VS = 2.5V
10
1
-100
0
100
1
200
10
100
1k
10k
100k
FREQUENCY (Hz)
OFFSET VOLTAGE (PV)
Figure 1. Offset Voltage Distribution
Figure 2. Input Referred Voltage Noise
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
Human Body Model
ESD Tolerance (3)
2000V
Machine Model
200V
Charge-Device Model
1000V
VIN Differential
±0.3V
Supply Voltage (VS = V+ – V−)
6.0V
+
−
Voltage on Input/Output Pins
V +0.3V, V −0.3V
Storage Temperature Range
−65°C to 150°C
Junction Temperature (4)
Soldering Information
(1)
(2)
(3)
(4)
+150°C
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
Temperature Range (2)
Supply Voltage (VS = V+ – V−)
Package Thermal Resistance (θJA (2))
(1)
(2)
2
−40°C to 125°C
0°C ≤ TA ≤ 125°C
1.8V to 5.5V
−40°C ≤ TA ≤ 125°C
2.0V to 5.5V
5-Pin SOT-23
180°C/W
8-Pin VSSOP
236°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
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SNOSAV0E – MARCH 2006 – REVISED MARCH 2013
2.5V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2. Boldface limits apply at
the temperature extremes.
Symbol
Parameter
Conditions
VOS
Min (1)
−20°C ≤ TA ≤ 85°C
Input Offset Voltage
−40°C ≤ TA ≤ 125°C
TC VOS
Input Offset Voltage Temperature
Drift (3) (4)
LMP7715
LMP7716/LMP7716Q
IB
VCM = 1.0V
IOS
Input Offset Current
VCM = 1V (4)
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 1.4V
CMVR
AVOL
Open Loop Voltage Gain
VOUT
Output Voltage Swing
High
Output Voltage Swing
Low
IOUT
Output Current
IS
(2)
(3)
(4)
(5)
(6)
-1
±4
-1.75
0.05
1
100
0.006
0.5
50
83
80
100
2.0V ≤ V ≤ 5.5V
V− = 0V, VCM = 0
85
80
100
1.8V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
98
−0.3
–0.3
Units
μV
μV/°C
pA
pA
dB
dB
1.5
1.5
LMP7715, VO = 0.15 to 2.2V
RL = 2 kΩ to V+/2
88
82
98
LMP7716/LMP7716Q, VO = 0.15 to 2.2V
RL = 2 kΩ to V+/2
84
80
92
LMP7715, VO = 0.15 to 2.2V
RL = 10 kΩ to V+/2
92
88
110
LMP7716/ LMP7716Q, VO = 0.15 to 2.2V
RL = 10 kΩ to V+/2
90
86
95
25
70
77
RL = 10 kΩ to V+/2
20
60
66
RL = 2 kΩ to V+/2
30
70
73
RL = 10 kΩ to V+/2
15
60
62
Sourcing to V−
VIN = 200 mV (6)
36
30
52
Sinking to V+
VIN = −200 mV (6)
7.5
5.0
15
1.30
1.65
1.10
1.50
1.85
8.3
AV = +1, Falling (90% to 10%)
10.3
mV from
either rail
mA
0.95
AV = +1, Rising (10% to 90%)
V
dB
RL = 2 kΩ to V+/2
LMP7716/LMP7716Q (per channel)
(1)
±180
±430
−40°C ≤ TA ≤ 125°C
LMP7715
Slew Rate
±20
1
25
Supply Current
SR
±180
±330
0.05
CMRR ≥ 80 dB
CMRR ≥ 78 dB
Common Mode Voltage Range
±20
−40°C ≤ TA ≤ 85°C
+
Power Supply Rejection Ratio
Max (1)
(4) (5)
Input Bias Current
PSRR
Typ (2)
mA
V/μs
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
The short circuit test is a momentary open loop test.
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2.5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2. Boldface limits apply at
the temperature extremes.
Symbol
GBW
Parameter
Min (1)
Conditions
Gain Bandwidth
en
Max (1)
14
Input Referred Voltage Noise Density
in
Typ (2)
Input Referred Current Noise Density
THD+N
Total Harmonic Distortion + Noise
f = 400 Hz
6.8
f = 1 kHz
5.8
f = 1 kHz
0.01
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 0.9 VPP
0.003
f = 1 kHz, AV = 1, RL = 600Ω
VO = 0.9 VPP
0.004
Units
MHz
nV/
pA/√Hz
%
5V Electrical Characteristics
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2. Boldface limits apply at the
temperature extremes.
Symbol
VOS
Typ (2)
Max (1)
−20°C ≤ TA ≤ 85°C
±10
±150
±300
−40°C ≤ TA ≤ 125°C
±10
±150
±400
-1
±4
Parameter
Min (1)
Conditions
Input Offset Voltage
TC VOS Input Offset Voltage Temperature
Drift (3) (4)
LMP7715
LMP7716/LMP7716Q
IB
-1.75
−40°C ≤ TA ≤ 85°C
Input Bias Current
VCM = 2.0V
−40°C ≤ TA ≤ 125°C
IOS
CMRR
4
0.01
0.5
50
0V ≤ VCM ≤ 3.7V
85
82
100
2.0V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
80
100
1.8V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
98
Common Mode Voltage Range
Open Loop Voltage Gain
(3)
(4)
(5)
1
100
Common Mode Rejection Ratio
AVOL
(2)
0.1
VCM = 2.0V (4)
Power Supply Rejection Ratio
(1)
1
25
Input Offset Current
PSRR
CMVR
0.1
(4) (5)
CMRR ≥ 80 dB
CMRR ≥ 78 dB
−0.3
–0.3
88
82
107
LMP7716/LMP7716Q, VO = 0.3 to 4.7V
RL = 2 kΩ to V+/2
84
80
90
LMP7715, VO = 0.3 to 4.7V
RL = 10 kΩ to V+/2
92
88
110
LMP7716/LMP7716Q, VO = 0.3 to 4.7V
RL = 10 kΩ to V+/2
90
86
95
μV
μV/°C
pA
pA
dB
dB
4
4
LMP7715, VO = 0.3 to 4.7V
RL = 2 kΩ to V+/2
Units
V
dB
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
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SNOSAV0E – MARCH 2006 – REVISED MARCH 2013
5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2. Boldface limits apply at the
temperature extremes.
Symbol
Typ (2)
Max (1)
RL = 2 kΩ to V+/2
32
70
77
RL = 10 kΩ to V+/2
22
60
66
RL = 2 kΩ to V+/2
(LMP7715)
42
70
73
RL = 2 kΩ to V+/2
(LMP7716/LMP7716Q)
45
75
78
RL = 10 kΩ to V+/2
20
60
62
Parameter
Min (1)
Conditions
VOUT
Output Voltage Swing
High
Output Voltage Swing
Low
IOUT
Output Current
IS
Sourcing to V−
VIN = 200 mV (6)
46
38
66
Sinking to V+
VIN = −200 mV (6)
10.5
6.5
23
LMP7715
Supply Current
LMP7716/LMP7716Q (per channel)
SR
Slew Rate
GBW
en
1.70
2.05
AV = +1, Falling (90% to 10%)
7.5
11.5
Input Referred Current Noise Density
Total Harmonic Distortion + Noise
f = 400 Hz
7.0
f = 1 kHz
5.8
f = 1 kHz
0.01
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 4 VPP
0.001
f = 1 kHz, AV = 1, RL = 600Ω
VO = 4 VPP
0.004
mA
V/μs
17
THD+N
(6)
1.30
9.5
Gain Bandwidth
Input Referred Voltage Noise Density
in
1.40
1.75
6.0
mV from
either rail
mA
1.15
AV = +1, Rising (10% to 90%)
Units
MHz
nV/√Hz
pA/√Hz
%
The short circuit test is a momentary open loop test.
Connection Diagram
5-Pin SOT-23
5
1
+
V
OUT A
-IN A
V
-
2
7
+
+
V
OUT B
2
+
+IN
8
1
-
OUTPUT
8-Pin VSSOP
+IN A
4
3
Figure 3. Top View
-IN
V
-
3
4
+-
6
5
-IN B
+IN B
Figure 4. Top View
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Typical Performance Characteristics
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Offset Voltage Distribution
PERCENTAGE (%)
20
TCVOS Distribution (LMP7715)
25
VS = 2.5V
-40°C d TA d 125qC
VCM = VS/2
UNITS TESTED:10,000
VS = 2.5V, 5V
20
PERCENTAGE (%)
25
15
10
5
VCM = VS/2
UNITS TESTED:
10,000
15
10
5
0
-200
0
-100
0
100
200
-3
-4
-2
-1
0
TCVOS (PV/°C)
OFFSET VOLTAGE (PV)
Figure 5.
TCVOS Distribution (LMP7716/LMP7716Q)
25
-40°C d TA d 125°C
VS = 2.5V, 5V
VS = 5V
VCM = VS/2
UNITS TESTED: 10,000
PERCENTAGE (%)
PERCENTAGE (%)
20
15
10
20 VCM = VS/2
UNITS TESTED:
10,000
15
10
5
5
0
-200
0
-100
0
100
-4
200
-3
-2
-1
Figure 7.
Figure 8.
Offset Voltage vs. VCM
Offset Voltage vs. VCM
200
200
VS = 1.8V
VS = 2.5V
150
-40°C
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
150
100
50
25°C
0
-50
125°C
-100
-40°C
100
25°C
50
0
125°C
-50
-100
-150
-150
-200
-0.3
0
TCVOS (PV/°C)
OFFSET VOLTAGE (PV)
0
0.3
0.9
0.6
1.2
1.5
-200
-0.3
0
VCM (V)
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0.3
0.6
0.9
1.2
1.5
1.8
2.1
VCM (V)
Figure 9.
6
2
Figure 6.
Offset Voltage Distribution
25
1
Figure 10.
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SNOSAV0E – MARCH 2006 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Offset Voltage vs. VCM
Offset Voltage vs. Supply Voltage
200
200
VS = 5V
150
100
-40°C
50
25°C
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
150
0
125°C
-50
-100
-150
100
-40°C
50
25°C
0
125°C
-50
-100
-150
-200
-0.3
-200
0.7
1.7
2.7
3.7
4.7
1.5
2.5
3.5
4.5
VS (V)
VCM (V)
Figure 11.
6
Figure 12.
Offset Voltage vs. Temperature
CMRR vs. Frequency
150
120
100
100
VS = 2.5V
50
VS = 2.5V
0
80
CMRR (dB)
OFFSET VOLTAGE (PV)
5.5
LMP7711
-50
VS = 5V
60
40
-100
VS = 5V
20
-150
LMP7712
-200
-40 -20
0
20
40
60
0
10
80 100 120 125
100k
1M
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 13.
Figure 14.
Input Bias Current vs. VCM
Input Bias Current vs. VCM
50
1000
VS = 5V
0
-500
-40°C
-1000
VS = 5V
40
INPUT BIAS CURRENT (pA)
25°C
500
INPUT BIAS CURRENT (fA)
10k
1k
100
-1500
-2000
-2500
30
20
125°C
10
0
-10
85°C
-20
-30
-40
-50
-3000
0
1
2
3
4
0
1
2
3
4
VCM (V)
VCM (V)
Figure 15.
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Figure 16.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Supply Current vs. Supply Voltage (LMP7715)
Supply Current vs. Supply Voltage (LMP7716/LMP7716Q)
2
2
1.6
1.6
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
125°C
125°C
25°C
1.2
0.8
-40°C
0.4
25°C
1.2
-40°C
0.8
0.4
0
0
1.5
2.5
3.5
4.5
5.5
1.5
Figure 18.
140
70
120
60
100
80
60
30
20
10
1M
10M
0
1.5
100M
-40°C
25°C
40
20
0
125°C
50
40
100k
5.5
Sourcing Current vs. Supply Voltage
80
ISOURCE (mA)
CROSSTALK REJECTION RATIO (dB)
4.5
Figure 17.
160
10k
3.5
VS (V)
Crosstalk Rejection Ratio (LMP7716/LMP7716Q)
1k
2.5
VS (V)
2.5
3.5
FREQUENCY (Hz)
4.5
5.5
VS (V)
Figure 19.
Figure 20.
Sinking Current vs. Supply Voltage
Sourcing Current vs. Output Voltage
35
70
30
60
125°C
125°C
20
50
ISOURCE (mA)
ISINK (mA)
25
25°C
15
10
8
25°C
30
20
-40°C
5
0
1.5
-40°C
40
10
0
2.5
3.5
4.5
5.5
0
1
2
3
VS (V)
VOUT (V)
Figure 21.
Figure 22.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Sinking Current vs. Output Voltage
Output Swing High vs. Supply Voltage
30
50
RL = 10 k:
VOUT FROM RAIL (mV)
125°C
25
ISINK (mA)
20
25°C
15
10
-40°C
40
30
25°C
125°C
20
-40°C
10
5
0
0
0
1
2
3
4
5
1.5
2.5
3.5
4.5
Figure 23.
Figure 24.
Output Swing Low vs. Supply Voltage
Output Swing High vs. Supply Voltage
50
50
40
30
-40°C
20
125°C
10
RL = 2 k:
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
RL =10 k:
40
125°C
25°C
30
20
-40°C
10
25°C
0
0
1.5
2.5
3.5
4.5
5.5
1.5
2.5
3.5
VS (V)
4.5
5.5
VS (V)
Figure 25.
Figure 26.
Output Swing Low vs. Supply Voltage
Output Swing High vs. Supply Voltage
50
150
RL = 600:
-40°C
40
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
5.5
VS (V)
VOUT (V)
125°C
30
25°C
20
10
120
90
125°C
25°C
60
30
-40°C
RL = 2 k:
0
1.5
0
2.5
3.5
4.5
5.5
1.5
2.5
3.5
4.5
5.5
VS (V)
VS (V)
Figure 27.
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Figure 28.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Output Swing Low vs. Supply Voltage
Open Loop Frequency Response
120
120
100
CL = 20 pF
80
25°C
-40°C
60
CL = 50 pF
60
125°C
90
GAIN
40
20
-20
CL = 50 pF
-40
CL = 100 pF
-60
100M
-60
1.5
2.5
3.5
4.5
1k
5.5
10k
VS (V)
100k
Open Loop Frequency Response
Phase Margin vs. Capacitive Load
50
120
PHASE
100
60
60
40
40
GAIN
20
20
0
0
-20
-20
-40
-40
10M
40
PHASE MARGIN (°)
80
PHASE (°)
80
RL = 600: 10 k: 10 M:
-60
10k
100k
1M
10M
Figure 30.
120
100
1M
FREQUENCY (Hz)
Figure 29.
GAIN (dB)
0
CL = 20 pF
-40
RL = 600:
30
RL = 10 k:
RL = 10 M:
20
10
VS = 2.5V
0
-60
100M
10
100
1000
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 31.
Figure 32.
Phase Margin vs. Capacitive Load
Overshoot and Undershoot vs. Capacitive Load
50
OVERSHOOT AND UNDERSHOOT (%)
70
RL = 600:
40
PHASE MARGIN (°)
40
20
0
0
80
60
CL = 100 pF
-20
30
RL = 10 k:
30
20
RL = 10 M:
10
VS = 5V
0
100
1000
CAPACITIVE LOAD (pF)
UNDERSHOOT%
60
50
OVERSHOOT %
40
30
20
10
0
10
0
20
40
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60
80
100
120
CAPACITIVE LOAD (pF)
Figure 33.
10
120
PHASE
100
GAIN (dB)
VOUT FROM RAIL (mV)
RL = 600:
PHASE (°)
150
Figure 34.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Slew Rate vs. Supply Voltage
Small Signal Step Response
12
FALLING EDGE
10 mV/DIV
SLEW RATE (V/Ps)
11
10
9
RISING EDGE
VIN = 20 mVPP
8
f = 1 MHz, AV = +1
VS = 2.5V, CL = 10 pF
7
1.5
2.5
3.5
4.5
5.5
200 ns/DIV
6
VS (V)
Figure 36.
Large Signal Step Response
Small Signal Step Response
10 mV/DIV
200 mV/DIV
Figure 35.
VIN = 1 VPP
VIN = 20 mVPP
f = 200 kHz, AV = +1
f = 1 MHz, AV = +1
VS = 2.5V, CL = 10 pF
VS = 5V, CL = 10 pF
800 ns/DIV
200 ns/DIV
Figure 37.
Figure 38.
Large Signal Step Response
THD+N vs. Output Voltage
0
THD+N (dB)
200 mV/DIV
-20
VS = 1.8V
f = 1 kHz
AV = +2
-40
-60
RL = 600:
-80
VIN = 1 VPP
f = 200 kHz, AV = +1
VS = 5V, CL = 10 pF
-100
RL = 100 k:
-120
0.01
800 ns/DIV
0.1
1
10
OUTPUT AMPLITUDE (VPP)
Figure 39.
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Figure 40.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
THD+N vs. Output Voltage
THD+N vs. Frequency
0.006
0
VS = 5.5V
f = 1 kHz
-20
VS = 1.8V
VO = 0.9 VPP
0.005
AV = +2
AV = +2
0.004
THD+N (%)
THD+N (dB)
-40
RL = 600:
-60
RL = 600:
-80
RL = 100 k:
0.003
0.002
-100
0.001
-120
RL = 100 k:
-140
0.01
0.1
1
0
10
10
100
1k
10k
100k
FREQUENCY (Hz)
OUTPUT AMPLITUDE (VPP)
Figure 41.
Figure 42.
THD+N vs. Frequency
PSRR vs. Frequency
120
0.006
VS = 5V
VS = 5.5V, -PSRR
VO = 4 VPP
0.005
VS = 1.8V, -PSRR
100
AV = +2
80
PSRR (dB)
THD+N (%)
0.004
RL = 600:
0.003
VS = 5.5V, +PSRR
60
0.002
40
0.001
20
VS = 1.8V, +PSRR
RL = 100 k:
0
0
10
100
1k
10k
100k
10
100
FREQUENCY (Hz)
1k
10k
100k
Figure 43.
Figure 44.
Input Referred Voltage Noise vs. Frequency
Time Domain Voltage Noise
100
VCM = 0.0V
400 nV/DIV
VS = 2.5V
10
1
1
10
100
10M
VS = ±2.5V
VS = 5.5V
VOLTAGE NOISE (nV/ Hz)
1M
FREQUENCY (Hz)
1k
10k
1 s/DIV
100k
FREQUENCY (Hz)
Figure 45.
12
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Figure 46.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Closed Loop Frequency Response
RL = 2 k:
180
3
CL = 20 pF
135
2
VO = 2 VPP
90
AV = +1
45
0
0
-1
-45
PHASE
-2
-90
-135
-3
GAIN
-4
-5
100
1k
100
10k
100 k
1M
OUTPUT IMPEDANCE (:)
VS = 5V
4
1
Closed Loop Output Impedance vs. Frequency
225
PHASE (°)
GAIN (dB)
5
10
1
0.1
-180
-225
10M
0.01
10
100
1k
10k 100k
1M
10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47.
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Figure 48.
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APPLICATION INFORMATION
LMP7715/LMP7716/LMP7716Q
The LMP7715/LMP7716/LMP7716Q are single and dual, low noise, low offset, rail-to-rail output precision
amplifiers with a wide gain bandwidth product of 17 MHz and low supply current. The wide bandwidth makes the
LMP7715/LMP7716/LMP7716Q ideal choices for wide-band amplification in portable applications.
The LMP7715/LMP7716/LMP7716Q are superior for sensor applications. The very low input referred voltage
noise of only 5.8 nV/√Hz at 1 kHz and very low input referred current noise of only 10 fA/√Hz mean more signal
fidelity and higher signal-to-noise ratio.
The LMP7715/LMP7716/LMP7716Q have a supply voltage range of 1.8V to 5.5V over a wide temperature range
of 0°C to 125°C. This is optimal for low voltage commercial applications. For applications where the ambient
temperature might be less than 0°C, the LMP7715/LMP7716/LMP7716Q are fully operational at supply voltages
of 2.0V to 5.5V over the temperature range of −40°C to 125°C.
The outputs of the LMP7715/LMP7716/LMP7716Q swing within 25 mV of either rail providing maximum dynamic
range in applications requiring low supply voltage. The input common mode range of the
LMP7715/LMP7716/LMP7716Q extends to 300 mV below ground. This feature enables users to utilize this
device in single supply applications.
The use of a very innovative feedback topology has enhanced the current drive capability of the
LMP7715/LMP7716/LMP7716Q, resulting in sourcing currents of as much as 47 mA with a supply voltage of only
1.8V.
The LMP7715 is offered in the space saving SOT-23 package and the LMP7716/LMP7716Q is offered in an 8pin VSSOP. These small packages are ideal solutions for applications requiring minimum PC board footprint.
CAPACITIVE LOAD
The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive
load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a
phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the
response will be either underdamped or the amplifier will oscillate.
The LMP7715/LMP7716/LMP7716Q can directly drive capacitive loads of up to 120 pF without oscillating. To
drive heavier capacitive loads, an isolation resistor, RISO as shown in Figure 49, should be used. This resistor
and CL form a pole and hence delay the phase lag or increase the phase margin of the overall system. The
larger the value of RISO, the more stable the output voltage will be. However, larger values of RISO result in
reduced output swing and reduced output current drive.
Figure 49. Isolating Capacitive Load
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The
LMP7715/LMP7716/LMP7716Q enhance this performance by having the low input bias current of only 50 fA, as
well as, a very low input referred voltage noise of 5.8 nV/√Hz. In order to achieve this a larger input stage has
been used. This larger input stage increases the input capacitance of the LMP7715/LMP7716/LMP7716Q.
Figure 50 shows typical input common mode capacitance of the LMP7715/LMP7716/LMP7716Q.
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25
VS = 5V
CCM (pF)
20
15
10
5
0
0
1
2
3
4
VCM (V)
Figure 50. Input Common Mode Capacitance
This input capacitance will interact with other impedances, such as gain and feedback resistors which are seen
on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at
low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher
frequencies, the presence of this pole will decrease phase margin and also cause gain peaking. In order to
compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being
selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase
stability.
The DC gain of the circuit shown in Figure 51 is simply −R2/R1.
CF
R2
R1
-
+
CIN
VIN
+
+
-
-
AV = -
VOUT
VIN
=-
VOUT
R2
R1
Figure 51. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in Figure 51 can be calculated as follows:
-R2/R1
(s) =
1+
s2
s
+
§ A0 R 1
§ A0
¨
¨C R
© R1 + R2
© IN 2
§
¨
©
VIN
§
¨
©
VOUT
(1)
This equation is rearranged to find the location of the two poles:
1
1
+
r
R1
R2
§1
1
+
¨
R
R
© 1
2
§
¨
©
-1
P1,2 =
2CIN
2
-
4 A0CIN
R2
(2)
As shown in Equation 2, as the values of R1 and R2 are increased, the magnitude of the poles are reduced,
which in turn decreases the bandwidth of the amplifier. Figure 52 shows the frequency response with different
value resistors for R1 and R2. Whenever possible, it is best to chose smaller feedback resistors.
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15
AV = -1
10
GAIN (dB)
5
0
-5
R1, R2 = 30 k:
-10
R1, R2 = 10 k:
-15
R1, R2 = 1 k:
-20
-25
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 52. Closed Loop Frequency Response
As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CF will
form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the
presence of pairs of poles that cause the peaking of gain. Figure 53 shows the frequency response of the
schematic presented in Figure 51 with different values of CF. As can be seen, using a small value capacitor
significantly reduces or eliminates the peaking.
20
R1, R2 = 30 k:
10
CF = 0 pF
AV = -1
GAIN (dB)
0
CF = 5 pF
-10
CF = 2 pF
-20
-30
-40
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 53. Closed Loop Frequency Response
TRANSIMPEDANCE AMPLIFIER
In many applications the signal of interest is a very small amount of current that needs to be detected. Current
that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers,
and industrial sensors are some typical applications utilizing photodiodes for current detection. This current
needs to be amplified before it can be further processed. This amplification is performed using a current-tovoltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of
an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to
the negative of the input current times the value of the feedback resistor. Figure 54 shows a transimpedance
amplifier configuration. CD represents the photodiode parasitic capacitance and CCM denotes the common-mode
capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less
stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to
prevent the circuit from oscillating.
With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the
LMP7715/LMP7716/LMP7716Q are ideal for wideband transimpedance applications.
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CF
RF
IIN
CCM
+
+
VOUT
CD
-
VB
CIN = CD + CCM
VOUT
= - RF
IIN
Figure 54. Transimpedance Amplifier
A feedback capacitance CF is usually added in parallel with RF to maintain circuit stability and to control the
frequency response. To achieve a maximally flat, 2nd order response, RF and CF should be chosen by using
Equation 3
CF =
CIN
GBWP
2 S RF
(3)
Calculating CF from Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is
especially the case for high speed applications. In these instances, it is often more practical to use the circuit
shown in Figure 55 in order to allow more sensible choices for CF. The new feedback capacitor, CF′, is (1+
RB/RA) CF. This relationship holds as long as RA
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