DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
DS92LV3241/DS92LV3242
Demonstration Kit
User Manual
P/N LV32EVK01
Rev 1.0
National Semiconductor Corporation
Date: 9/28/2009
Page 1 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................... 2
INTRODUCTION: ..................................................................................................................................................... 3
CONTENTS OF THE EVALUATION KIT:........................................................................................................... 4
HOW TO SET UP THE EVALUATION KIT:........................................................................................................ 5
POWER CONNECTION: ......................................................................................................................................... 5
SERIALIZER (TX) BOARD DESCRIPTION: ....................................................................................................... 6
CONFIGURATION SETTINGS FOR THE SERIALIZER BOARD ......................................................................................... 7
SERIALIZER LVCMOS AND LVDS PINOUT BY IDC CONNECTOR ............................................................................ 9
DESERIALIZER (RX) BOARD: ............................................................................................................................ 10
CONFIGURATION SETTINGS FOR THE DESERIALIZER BOARD .................................................................................. 11
DESERIALIZER LVDS AND LVCMOS PINOUT BY CONNECTOR ............................................................................. 12
TYPICAL APPLICATIONS:.................................................................................................................................. 14
TROUBLESHOOTING ........................................................................................................................................... 16
APPENDIX................................................................................................................................................................ 17
BOM (BILL OF MATERIALS) SERIALIZER PCB: ...................................................................................................... 17
BOM (BILL OF MATERIALS) DESERIALIZER PCB:.................................................................................................. 18
SERIALIZER (TX) PCB SCHEMATIC:............................................................................................................... 19
DESERIALIZER (RX) PCB SCHEMATIC: ......................................................................................................... 23
SERIALIZER (TX) PCB LAYOUT: ...................................................................................................................... 27
SERIALIZER (TX) PCB STACKUP: .................................................................................................................... 30
DESERIALIZER (RX) PCB LAYOUT:................................................................................................................. 31
DESERIALIZER (RX) PCB STACKUP:............................................................................................................... 34
National Semiconductor Corporation
Date: 9/28/2009
Page 2 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Introduction:
National Semiconductor’s SERDES evaluation kit contains one (1) DS92LV3241
Serializer (Tx) board, one (1) DS92LV3242 Deserializer (Rx) board, and one (1)
standard (~2) meter CAT 6 style cable assembly.
Note: The demo boards are not intended for EMI testing. These demo boards were
designed for easy accessibility to device pins with tap points for monitoring or applying
signals, and additional pads for termination.
The DS92LV3241/3242 chipset supports a variety of display and imaging applications.
Typical applications include: navigation displays, automated teller machines (ATMs),
POS, video cameras, global positioning systems (GPS), portable
equipment/instruments, factory automation, printers, etc.
The DS92LV3241 and DS92LV3242 can also be used as a 32-bit general purpose
LVDS Serializer and Deserializer chipset designed to transmit data at clocks speeds
ranging from 20 to 50 MHz in dual mode or 40MHz to 85 MHz in quad mode.
The DS92LV3241 serializer board accepts LVCMOS input signals at either 3.3V or
1.8V.
Note: IOVDD must be set to 3.3V for 3.3V input levels or 1.8V for 1.8V input levels.
The LVDS Serializer converts the LVCMOS parallel lines into either two (2) serialized
LVDS data pairs with an embedded LVDS clock on each channel or four (4) serialized
LVDS data pairs with an embedded LVDS clock on each channel.
The DS92LV3242 deserializer board accepts the LVDS serialized data streams with an
embedded clock on each LVDS stream and converts the data back into parallel
LVCMOS signals and clock. Note that NO reference clock is needed to prevent
harmonic lock as with other devices currently on the market.
Suggested equipment to evaluate the chipset include: an LVCMOS signal source, such
as a video generator, word generator, or pulse generator and oscilloscope.
The user needs to provide the proper LVCMOS clock and data inputs to the serializer
and also provide a proper interface from the deserializer output to an LCD panel or test
equipment. The serializer and deserializer boards can also be used to evaluate device
parameters.
National Semiconductor Corporation
Date: 9/28/2009
Page 3 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board
for more detailed information.
Contents of the Evaluation Kit:
1) One serializer board with the DS92LV3241
2) One deserializer board with the DS92LV3242
3) One 2-meter standard CAT 6 cable assembly
4) Evaluation Kit Documentation (this manual)
5) DS92LV3241/3242 Datasheet
National Semiconductor Corporation
Date: 9/28/2009
Page 4 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
How to set up the Evaluation Kit:
The PCB routing for the serializer input pins (TxIN) have been laid out to accept
incoming LVCMOS signals from a 50-pin IDC connector. The serial interface between
the DS92LV3241 and the DS92LV3242 uses a standard RJ-45 connector and CAT-5/6
cable assembly (small CAT-6 cable provided). The PCB routing for the Rx output pins
(RxOUT) are accessed through a 50-pin IDC connector. Please follow these steps to
set up the evaluation kit for bench testing and performance measurements:
1) A two (2) meter CAT 6 connector/cable assembly has been included in the kit.
Connect one side of cable to the serializer board and the other side to the
deserializer board. This completes the LVDS interface connection.
2) Jumpers and switches have been configured at the factory; they should not require
any changes for immediate operation of the chipset. See text on Configuration
Settings for more details. From the transmitting test equipment, connect a flat cable
or fly wires (not supplied) to the Serializer board and connect another flat cable or fly
wires (not supplied) from the Deserializer board to the receiving test equipment.
Caution: The LVCMOS input levels should be within the specified range for optimal
performance, not to exceed the absolute maximum rating of -0.3V to (VDD +0.3V).
Note: For 50 ohm signal sources, add 50 ohm parallel termination resistors R1-R32
on the DS92LV3241 Serializer board and provide appropriate 3.3V LVCMOS input
signal levels into TxIN[32:0] and TxCLKIN.
Note: The Rx board may require the use of LVCMOS buffers to drive 50 ohm inputs
found in some test equipment.
3) Power for the Tx and Rx boards must be supplied externally through Power Jack
(VDD). Grounds for both boards are connected through Power Jack (VSS) (see
section below).
Power Connection:
The serializer and deserializer boards must be powered by supplying power externally
through J7 (VDD) and J8 (VSS) on the serializer Board and J6 (VDD) and J7 (VSS) on the
deserializer board. Note +4V is the absolute MAXIMUM voltage (not operating voltage)
that should ever be applied to the serializer (DS92LV3241) or deserializer
(DS92LV3242) VDD terminal. Damage to the device(s) can result if the voltage
maximum is exceeded.
National Semiconductor Corporation
Date: 9/28/2009
Page 5 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) Board Description:
The 50-pin IDC connector J1 accepts 32 bits of LVCMOS RGB/generic data (TxIN0TxIN32) along with the clock input (TCLK).
The SERDES serializer board is powered externally from the J7 (VDD) and J8 (VSS)
connectors shown below. For the serializer to be operational, the Power Down
(PWDNB) switch on S1 must be set HIGH. The board is factory configured (with series
0.1μF capacitors on the LVDS outputs. Rising or falling edge input clock is also
selected on S1-TRFB: HIGH (rising) or LOW (falling). JP2 is configured from the factory
to be tied to VDD (3.3V), which sets the LVCMOS I/O pins to operate at 3.3V logic levels.
The RJ-45 connector P1 (on the bottom side of the board) provides the interface
connection to the LVDS signals to the deserializer board.
c LVDS OUTPUTS
d LVCMOS INPUTS
e FUNCTION CONTROLS
f POWER SUPPLY
g 50Ω INPUT
f J7, J8
Note:
VDD and VSS MUST
be applied externally
here.
TERMINATION
(For 50Ω signal sources,
populated with 50ohm
resistors to provide proper
termination.)
(IOVDD default setting IOVDD is connected to VDD)
g
J1
c
g
P1 (BOTTOM SIDE)
(RJ-45)
d
g
g
e VR1, JP4
S1
e
ASSY DS92LV3241 TX DEMO
REV
National Semiconductor Corporation
Date: 9/28/2009
Page 6 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Serializer Board
S1: Serializer Input Features Selection
Reference
Description
Input = L
PWDNB
PoWerDowN Bar Powers
Down
BISTEN
BIST ENable
TRFB
Latch input data
on Rising or
Falling edge of
TCLK
Dual or Quad
mode
REServed
MODE
DB/Q
RES_0
V SEL
LVDS output VOD
SELect
BIST mode
disabled
(Default)
Falling
Edge
(Default)
Dual mode
(Default)
MUST be
tied low for
normal
operation
(Default)
≈440 mVP-P
(Default)
JP2: Serializer Input Features Selection
Reference
Description
Default
IOVDD
1.8V input
Connected
option.
to VDD (J7)
For 1.8V input
swing IOVDD is
connected to
VDDI. VDDI
must be applied
on JP1 pin 1.
Input = H
Normal
operation
(Default)
BIST mode
enabled
S1
Rising
Edge
Quad mode
Not allowed
≈850 mVP-P
External
National Semiconductor Corporation
JP2
Date: 9/28/2009
Page 7 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
JP4,VR1: Pre-Emphasis Feature Selection
Reference
Description
JP4
JP4 &
VR1
Pre-Emphasis – helps to
increase the eye pattern
opening in the LVDS
streams by providing current
boost
Pre-Emphasis adjustment
(via screw)
JP1 MUST have a jumper to
use VR1 potentiometer.
VR1 = 0Ω to 20 kΩ,
JP1 + VR1 + 12 kΩ (R34) =
~12 kΩ (maximum preemphasis) to
~32 kΩ (minimum preemphasis*).
IPRE = [1.2/(RPRE)] x 40,
RPRE (minimum) > 12 kΩ
OPEN
(floating)
Disabled –
no jumper
(Default)
CLOSED
(Path to GND)
Enabled –
With jumper
Clockwise
CounterClockwise
increases
RPRE value
which
decreases
preemphasis
decreases
RPRE value
which
increases
preemphasis
*Note: maximum is based on resistor
value. In this case ~32KΩ value is based
on the ~12kΩ fixed resistor plus ~20KΩ
maximum potentiometer value. User can
use hundreds of k Ohms to reduce the preemphasis value.
Pre-emphasis user note:
Pre-emphasis must be adjusted correctly based on application frequency, cable quality,
cable length, and connector quality. Maximum pre-emphasis should only be used under
worse case conditions; for example at the upper frequency specification of the part
and/or low grade cables at maximum cable lengths. Typically all that is needed is
minimum pre-emphasis. Users should start with no pre-emphasis first and gradually
apply pre-emphasis until there is clock lock and no data errors. The best way to monitor
the pre-emphasis effect is to hook up a differential probe across the AC-coupling
capacitors for the (+) and (-) inputs of the LVDS channels on the DS92LV3242 Rx demo
board (NOT across the AC-coupling capacitors for the LVDS channels on the
DS92LV3241 Tx demo board).
National Semiconductor Corporation
Date: 9/28/2009
Page 8 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer LVCMOS and LVDS Pinout by IDC Connector
The following two (2) tables illustrate how the serializer inputs are mapped to the IDC
connector J1, the LVDS outputs on the RJ-45 connector P1 pinout.
Note: Labels are also printed on the demo boards for both the LVCMOS input and
LVDS outputs.
TTL INPUT
J1 Pin No. Symbol
2
TxIN0
4
TxIN1
6
TxIN2
8
TxIN3
10
TxIN4
12
TxIN5
14
TxIN6
16
TxIN7
18
TxIN8
20
TxIN9
22
TxIN10
24
TxIN11
26
TxIN12
28
TxIN13
30
TxIN14
32
TxIN15
34
TxIN16
36
TxIN17
38
TxIN18
40
TxIN19
42
TxIN20
44
TxIN21
46
TxIN22
48
TxIN23
50
TxIN24
52
TxIN25
54
TxIN26
56
TxIN27
58
TxIN28
60
TxIN29
62
TxIN30
64
TxIN31
66
TxCLKIN
LVDS OUTPUT
P1 Pin No. Symbol
1
OUT 0 +
2
OUT 0 3
OUT 1 +
4
OUT 2 +
5
OUT 2 6
OUT 1 7
OUT 3 +
8
OUT 3 -
All Odd Pins GND
National Semiconductor Corporation
Date: 9/28/2009
Page 9 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) Board:
The RJ-45 connector P1 provides the interface connection for LVDS signals to the
deserializer board.
The deserializer board is powered externally from the J6 (VDD) and J7 (VSS)
connectors shown below. For the deserializer to be operational, the Power Down
(PWDNB) and Receiver Enable (REN) switches on S1 must be set HIGH. Rising or
falling edge output clock is also selected by S1(R FB): HIGH (rising) or LOW (falling).
The 50 pin IDC Connector J1 provides access to the 32 LVCMOS data and clock
outputs.
f J6, J7
Note:
VDD and Gnd MUST be
applied externally here
e S1
g
g
d J1
c P1 (TOP SIDE)
g
d JP3
ASSY DS92LV3242 RX DEMO
c LVDS INPUTS
d LVCMOS OUTPUTS
e FUNCTION CONTROLS
f POWER SUPPLY
g OPTIONAL PARALLEL
LVCMOS LOADING PADS
REV
National Semiconductor Corporation
Date: 9/28/2009
Page 10 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Configuration Settings for the Deserializer Board
S1: Deserializer Input Features Selection
Reference
Description
Input = L
RSVD
ReSerVeD
MUST be
tied low for
normal
operation
(Default)
RRFB
Latch input data on Rising Falling Edge
or Falling edge of
(Default)
RxCLKOUT
PWDNB
PoWerDowN Bar
Power Down
(Disabled)
REN
Receiver Output Data
ENabled
Disabled
Input = H
Not allowed
S1
Rising Edge
Normal
Operational
(Default)
Enabled
(Default)
Output Monitor Pins for the Deserializer Board
JP3: Output Lock Monitor
Reference
Description
LOCK
Receiver PLL LOCK Status
Note:
DO NOT PUT A SHORTING
JUMPER IN JP3.
Output = L
Unlocked
National Semiconductor Corporation
Output = H
PLL LOCKED
(LED1 will
illuminate)
JP3
Date: 9/28/2009
Page 11 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer LVDS and LVCMOS Pinout by Connector
The following two tables illustrate how the LVDS inputs are mapped to the RJ-45
connector J1 and the Rx outputs are mapped to the IDC connector J1.
Note: Labels are also printed on the demo boards for both the LVDS inputs and
LVCMOS outputs.
LVCMOS OUTPUT
J1 Pin No. Symbol
1
RxOUT0
3
RxOUT1
5
RxOUT2
7
RxOUT3
9
RxOUT4
11
RxOUT5
13
RxOUT6
15
RxOUT7
17
RxOUT8
19
RxOUT9
21
RxOUT10
23
RxOUT11
25
RxOUT12
27
RxOUT13
29
RxOUT14
31
RxOUT15
33
RxOUT16
35
RxOUT17
37
RxOUT18
39
RxOUT19
41
RxOUT20
43
RxOUT21
45
RxOUT22
47
RxOUT23
49
RxOUT24
51
RxOUT25
53
RxOUT26
55
RxOUT27
57
RxOUT28
59
RxOUT29
61
RxOUT30
63
RxOUT31
65
RxCLKOUT
LVDS INPUT
P1 Pin No. Symbol
1
IN 0 +
2
IN 0 3
IN 1 +
4
IN 2 +
5
IN 2 6
IN 1 7
IN 3 +
8
IN 3 -
All Even Pins GND
LVCMOS OUTPUT
JP3 pin no. Symbol
1
LOCK (PLL)
2
GND
National Semiconductor Corporation
Date: 9/28/2009
Page 12 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Typical Connection and Test Equipment
The following is a list of typical test equipment that may be used to generate signals for
the TX inputs:
1) Digital Video Source – for generation of specific display timing such as Digital Video
Processor or Graphics Controller with digital RGB (LVCMOS) output.
2) Astro Systems VG-835 - This video generator may be used for video signal sources
for 6-bit Digital TTL/RGB.
3) Any other signal / video generator that generates the correct input levels as specified
in the datasheet.
4) Logic Analyzer or Oscilloscope
The following is a list of typically test equipment that may be used to monitor the output
signals from the RX:
1)
2)
3)
4)
LCD Display Panel which supports digital RGB (LVCMOS) inputs.
National Semiconductor DS92LV3241 Serializer (Tx)
Optional – Logic Analyzer or Oscilloscope
Any SCOPE with a bandwidth of at least 170 MHz for TTL and/or 1 GHz for looking
at the LVDS signals.
LVDS signals may be easily measured with high impedance, low capacitance, high
bandwidth differential probes such as the TEK P6330 differential probes.
National Semiconductor Corporation
Date: 9/28/2009
Page 13 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Typical Applications:
Figure 1. Typical SERDES Application
The chipset supports up to 30-bit color depth TFT LCD Panels. The picture below
shows a typical test set up using a Graphics Controller and LCD Panel.
Transmitter
Board
Receiver
Board
LCD Panel
Digital RGB (TTL)
from Graphic
Contoller
LVDS Interface
Cable
Digital RGB
(TTL) to Panel
Contents of Demo Kit
Graphics Controller /
Video Processor Board
Figure 2. Typical SERDES Setup of LCD Panel Application
National Semiconductor Corporation
Date: 9/28/2009
Page 14 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
The picture below shows a typical test set up using a generator and scope.
Figure 3. Typical SERDES Test Setup for Evaluation
National Semiconductor Corporation
Date: 9/28/2009
Page 15 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Troubleshooting
If the demo boards are not performing properly, use the following as a guide for quick
solutions to potential problems. If the problem persists, please contact the local Sales
Representative for assistance.
QUICK CHECKS:
1. Check that Power and Ground are connected to both Tx AND Rx boards.
2. Check the supply voltage (typical 3.3V) and also current draw with both Tx and Rx
boards. The Serializer board should draw about 150-200 mA with clock and all data
bits switching at 85 MHz in Quad Mode, (RPRE=12 kΩ). The Deserializer board
should draw about 240-265mA with clock and all data bits switching at 85 MHz in
Quad Mode (8pF RxOUT loading).
3. Verify input clock and input data signals meet requirements for VILmin, VILmax,
VIHmin, VIHmax, tSTC, tHTC), also verify that data is strobed on the selected
rising/falling (RFB pin) edge of the clock.
4. Check that the Jumpers and Switches are set correctly.
5. Check that the cable is properly connected.
TROUBLESHOOTING CHART
Problem…
There is only the output clock.
There is no output data.
Solution…
Make sure the data is applied to the correct input pin.
Make sure data is valid at the input.
No output data and clock.
Make sure Power is on. Input data and clock are
active and connected correctly.
Power, ground, input data and
input clock are connected
correctly, but no outputs.
The devices are pulling more
than 1A of current.
After powering up the demo
boards, the power supply
reads less than 3V when it is
set to 3.3V.
Make sure that the cable is secured to both demo
boards.
Check the Power Down pins of both Serializer and
Deserializer boards to make sure that the devices are
enabled (/PWDB=VDD) for operation. Also check
DEN on the Serializer board and REN on the
Deserializer board is set HIGH.
Check for shorts in the cables connecting the TX and
RX boards.
Use a larger power supply that will provide enough
current for the demo boards, a 500mA minimum
power supply is recommended.
National Semiconductor Corporation
Date: 9/28/2009
Page 16 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Appendix
BOM (Bill of Materials) Serializer PCB:
DS92LV3241 Tx Demo Board - Board Stackup Revised: Monday, September 21, 2009
DS92LV3241 Tx Demo Board
Revision: 1
Bill Of Materials September 21, 2009
Item
Qty Reference
Part
______________________________________________
1
2
3
4
2
2
2
8
5
8
6
8
7
8
8
9
10
11
12
13
14
15
16
17
2
1
2
1
4
1
2
1
1
32
18
19
20
21
1
1
2
10
22
24
25
26
27
6
1
1
1
1
C4,C1
C5,C2
C3,C6
C7,C8,C9,C10,C11,C12,C13,
C14
C15,C16,C17,C26,C31,C34,
C35,C38
C18,C21,C22,C25,C28,C29,
C36,C37
C19,C20,C23,C24,C27,C30,
C32,C33
JP1,JP4
JP2
JP3,JP5
J1
J2,J3,J4,J5
J6
J7,J8
J9
P1
R1,R2,R3,R4,R5,R6,R7,R8,
R9,R10,R11,R12,R13,R14,
R15,R16,R17,R18,R19,R20,
R21,R22,R23,R24,R25,R26,
R27,R28,R29,R30,R31,R32
R33
R34
R36,R35
R37,R38,R39,R40,R41,R42,
R43,R44,R45, R52
R46,R47,R48,R49,R50,R51
S1
U1
U2
VR1
PCB Footprint
22uF
2.2uF
0.1uF
0.1uF
CAP/N
3528-21_EIA
CAP/HDC-1206
CAP/HDC-0603
22uF
CAP/EIA-B 3528-21
0.1uF
CAP/HDC-0603
0.01uF
CAP/HDC-0603
2-Pin Header
3-Pin Header
2-Pin Header_open
IDC2X33_Unshrouded
IDC2X2_Unshrouded
2x4 pin Jumper_OPEN
BANANA
CONN JACK PWR_open
RJ-45 8pin_open
49.9ohm_open
Header/2P
Header/3P
Header/2P
IDC-66
IDC-2x2
IDC_2x4
CON/BANANA-S
3-terminal thru hole power jack
RJ-45_thru_hole
RES/HDC-0201
49.9ohm_open
12.0K, 0402
332 ohm_open
0 Ohm,0402
RES/HDC-0805
RES/HDC-0402
RES/HDC-0805
RES/HDC-0402
10K
SW DIP-6
DS92LV3241
LM3940/SOT223_open
SVR20K
RES/HDC-0805
DIP-12
64ld TQFP
SOT223
Surface Mount 4mm Square
National Semiconductor Corporation
Date: 9/28/2009
Page 17 of 34
DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
BOM (Bill of Materials) Deserializer PCB:
DS92LV3242 Rx Demo Board - Board Stackup Revised: Monday, September 21, 2009
DS92LV3242 Rx Demo Board
Revision: 1
Bill Of Materials
September 21, 2009
Item
Qty Reference
Part
______________________________________________
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
8 C1,C2,C3,C4,C5,C6,C7,C8
33 C9,C10,C11,C12,C13,C14,
C15,C16,C17,C18,C19,C20,
C21,C22,C23,C24,C25,C26,
C27,C28,C29,C30,C31,C32,
C33,C34,C35,C36,C37,C38,
C39,C40,C41
1 C42
1 C43
1 C44
9 C45,C46,C47,C54,C55,C66,
C69,C70,C71
9 C48,C51,C53,C57,C59,C61,
C62,C64,C67
9 C49,C50,C52,C56,C58,C60,
C63,C65,C68
2 JP1,JP2
1 JP3
1 J1
4 J2,J3,J4,J5
2 J6,J7
1 J8
1 J9
1 LED1
1 P1
2 R2,R1
4 R3,R4,R5,R6
10 R7,R8,R9,R10,R11,R12,R13,
R14,R15,R16
1 S1
1 U1
1 U2
PCB Footprint
0.1uF
open0402
CAP/HDC-0603
CAP/HDC-0402
22uF
2.2uF
0.1uF
22uF
CAP/N
3528-21_EIA
CAP/HDC-1206
CAP/EIA-B 3528-21
0.01uF
CAP/HDC-0603
0.1uF
CAP/HDC-0603
2-Pin Header_open
2-Pin Header
IDC2X33_Unshrouded
IDC2X2_Unshrouded
BANANA
2x4 pin Jumper_OPEN
CONN JACK PWR_open
0603_green_LED
RJ-45 8pin
332 ohm_open
10K
0 Ohm,0402
Header/2P
Header/2P
IDC-66
IDC-2x2
CON/BANANA-S
IDC_2x4
3-terminal thru hole power jack
0603 (Super Thin)
RJ-45_thru_hole
RES/HDC-0805
RES/HDC-0805
RES/HDC-0402
SW DIP-4
DS92LV3242
LM3940/SOT223_open
DIP-8
64ld TQFP
SOT223
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Schematic:
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Schematic:
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
National Semiconductor Corporation
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
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Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Layout:
ASSY DS92LV3241 TX DEMO
REV
PWB DS92LV3241 TX DEMO REV 1
TOP VIEW
BOTTOMSIDE VIEW
National Semiconductor Corporation
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
PRIMARY COMPONENT SIDE – LAYER 1
SECONDARY COMP SIDE – LAYER 4
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1)
GROUND PLANE (VSS) – LAYER 2
PRIMARY COMP SIDE – SOLDER MASK (LAYER 1)
POWER PLANE (VDD) – LAYER 3
SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
ASSY DS92LV3241 TX DEMO
REV
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1)
SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
National Semiconductor Corporation
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Serializer (Tx) PCB Stackup:
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Layout:
ASSY DS92LV3242 RX DEMO
REV
PWB DS92LV3242 RX DEMO REV 1
TOP VIEW
BOTTOMSIDE VIEW
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
PRIMARY COMPONENT SIDE – LAYER 1
SECONDARY COMP SIDE – LAYER 4
GROUND PLANE (VSS) – LAYER 2
POWER PLANE (VDD) – LAYER 3
PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) SECONDARY COMP SIDE – SOLDER MASK (LAYER 4)
PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4)
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
ASSY DS92LV3242 RX DEMO
REV
PRIMARY COMP SIDE – SILKSCREEN (LAYER 1)
SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4)
National Semiconductor Corporation
Date: 9/28/2009
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DS92LV3241/3242 Evaluation Kit Users Manual Version 1.0
Deserializer (Rx) PCB Stackup:
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