SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
FEATURES
•
•
•
•
•
•
•
•
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enable Mode
Operates From 1.65 V to 3.6 V
Max tpd of 3.2 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
GND
OEAB
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
OEBA
CLKENBA
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus transceiver is designed for
1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA) and clock-enable
(CLKENBA) inputs. For the A-to-B data flow, the data
flows through a single buffer. The B-to-A data can
flow through a four-stage pipeline register path, or
through a single register path, depending on the state
of the select (SEL) input.
Data is stored in the internal registers on the
low-to-high transition of the clock (CLK) input,
provided that the appropriate CLKENBA input is low.
The B-to-A data transfer is synchronized with CLK.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
GND
SEL
B1
GND
B2
B3
VCC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
VCC
B16
B17
GND
B18
CLK
GND
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
PACKAGE (1)
TA
-40 to 85°C
SSOP - DL
TSSOP - DGG
(1)
ORDERABLE PART NUMBER
Tube
SN74ALVCH16524DL
Tape and reel
SN74ALVCH16524DLR
Tape and reel
SN74ALVCH16524DGGR
TOP-SIDE MARKING
ALVCH16524
ALVCH16524
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2004, Texas Instruments Incorporated
SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
FUNCTION TABLE
B-TO-A STORAGE (OEBA = L)
INPUTS
(1)
(2)
CLKENBA
CLK
SEL
B
OUTPUT
A
H
X
X
X
A0 (1)
L
↑
H
L
L
L
↑
H
H
H
L
↑
L
L
L (2)
L
↑
L
H
H (2)
Output level before the indicated steady-state input conditions were
established
Four positive CLK edges are needed to propagate data from B to A
when SEL is low.
LOGIC DIAGRAM (POSITIVE LOGIC)
30
CLK
CLKENBA
28
2
OEAB
27
OEBA
SEL
55
1 of 18 Channels
CE
3
A1
2
C1
1D
G1
1
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
54
B1
SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
Except I/O ports (2)
MIN
MAX
-0.5
4.6
-0.5
4.6
-0.5
VCC + 0.5
-0.5
VCC + 0.5
UNIT
V
VI
Input voltage range
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
-50
mA
IOK
Output clamp current
VO < 0
-50
mA
IO
Continuous output current
±50
mA
±100
mA
I/O ports
(2) (3)
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
DGG package
64
DL package
56
-65
150
V
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 1.65 V to 1.95 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V to 3.6 V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.8
VCC = 1.65 V
-4
VCC = 2.3 V
-12
VCC = 2.7 V
-12
VCC = 3 V
-24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
-40
mA
mA
10
ns/V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = -100 µA
1.65 V to 3.6 V
1.65 V
IOH = -6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = -24 mA
3V
2
IOL = 100 µA
IOH = -12 mA
II(hold)
V
1.65 V to 3.6 V
0.2
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
IOL = 24 mA
II
1.2
IOL = 4 mA
IOL = 12 mA
2.7 V
0.4
3V
0.55
±5
VI = VCC or GND
3.6 V
VI = 0.58 V
1.65 V
25
VI = 1.07 V
1.65 V
-25
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
-45
VI = 0.8 V
3V
75
3V
-75
VI = 2 V
UNIT
VCC - 0.2
IOH = -4 mA
VOH
VOL
MIN TYP (1) MAX
VCC
V
µA
µA
3.6 V
±500
IOZ (3)
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND, IO = 0
3.6 V
40
µA
∆ICC
One input at VCC - 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
750
µA
VI = 0 to 3.6
V (2)
Ci
Control inputs
VI = VCC or GND
3.3 V
3
pF
Cio
A or B ports
VO = VCC or GND
3.3 V
7
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
(1)
4
MAX
VCC = 2.7 V
MIN
120
MAX
VCC = 3.3 V
± 0.3 V
MIN
125
3.2
3.2
3
B data before CLK↑
(1)
1.5
1.2
1.1
SEL before CLK↑
(1)
2.7
2.4
2.1
CLKENBA before CLK↑
(1)
2.7
2.6
2
B data after CLK↑
(1)
1
0.6
1.2
SEL after CLK↑
(1)
0.5
0.2
0.8
CLKENBA after CLK↑
(1)
0.1
0.1
0.3
This information was not available at the time of publication.
UNIT
MAX
150
(1)
Pulse duration, CLK high or low
Hold time
MIN
(1)
Clock frequency
Setup time
MAX
VCC = 2.5 V
± 0.2 V
MHz
ns
ns
ns
SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
MIN
(1)
fmax
MIN
MAX
120
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
125
150
UNIT
MHz
A
B
(1)
1
3.9
3.8
1
3.2
CLK
A
(1)
1
6.1
6.2
1
5.2
ten
OEAB or OEBA
A or B
(1)
1
6.1
6.1
1
5.1
ns
tdis
OEAB or OEBA
A or B
(1)
1
6.3
5.4
1
4.9
ns
tpd
(1)
TYP
VCC = 2.5 V
± 0.2 V
ns
This information was not available at the time of publication.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
(1)
Power dissipation Outputs enabled
capacitance
Outputs disabled
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
160
160
(1)
160
160
UNIT
pF
This information was not available at the time of publication.
5
SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES080E – JULY 1996 – REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SN74ALVCH16524DL
ACTIVE
SSOP
DL
56
20
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVCH16524
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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