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SN74LVC1G80
SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
SN74LVC1G80 Single Positive-Edge-Triggered D-Type Flip-Flop
1 Features
3 Description
•
This single positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoFree™ Package
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to VCC
Maximum tpd of 4.2 ns at 3.3 V
Low Power Consumption, 10-µA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Test and Measurement
Enterprise Switching
Telecom Infrastructure
Motor Drives
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the level at the output.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC1G80DBV
SOT-23 (5)
2.90 mm × 1.60 mm
SN74LVC1G80DCK
SC70 (5)
2.00 mm × 1.25 mm
SN74LVC1G80YZP
DSBGA (5)
1.41 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
CLK
C
C
C
4
TG
C
C
Q
C
C
D
1
(1)
TG
TG
TG
C
C
C
TG - Transmission Gate
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G80
SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Absolute Maximum Ratings ..................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Timing Requirements: TA = –40°C to +85°C ............ 6
Timing Requirements: TA = –40°C to +125°C .......... 6
Switching Characteristics: TA = –40°C to +85°C, CL =
15 pF .......................................................................... 7
6.9 Switching Characteristics: TA = –40°C to +85°C, CL =
30 pF or 50 pF ........................................................... 7
6.10 Switching Characteristics: TA = –40°C to +125°C,
CL = 30 pF or 50 pF ................................................... 7
6.11 Operating Characteristics........................................ 7
6.12 Typical Characteristics ............................................ 8
7
Parameter Measurement Information .................. 9
8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision R (December 2013) to Revision S
Page
•
Added Applications section, Device Information table, ESD Ratings table, Thermal Information table, Typical
Characteristics section, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Added max junction temperature to the Recommended Operating Conditions table ........................................................... 5
•
Added operating free-air temperature for YZP package to the Recommended Operating Conditions table ........................ 5
•
Changed RθJA value for DBV package from: 206°C/W to: 243.4°C/W ................................................................................... 5
•
Changed RθJA value for DCK package from: 252°C/W to: 278.9°C/W ................................................................................... 5
•
Changed RθJA value for YZP package from: 132°C/W to: 136.9°C/W.................................................................................... 5
Changes from Revision Q (January 2007) to Revision R
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Ioff in Features. ......................................................................................................................................................... 1
•
Updated operating temperature range. .................................................................................................................................. 4
•
Added ESD warning ............................................................................................................................................................ 15
2
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SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
YZP Package
5-Pin DSBGA
Bottom View
GND
3 4
CLK
2
D
DCK Package
5-Pin SC70
Top View
Q
VCC
1 5
D
1
CLK
2
GND
3
5
VCC
4
Q
DBV Package
5-Pin SOT-23
Top View
D
1
CLK
2
GND
3
5
VCC
4
Q
Pin Functions (1)
PIN
NO.
1
NAME
D
I/O
DESCRIPTION
I
Data input
Clocking input
2
CLK
I
3
GND
—
Ground pin
4
Q
O
Flip-flop output
5
VCC
—
Power pin
(1)
See Mechanical, Packaging, and Orderable Information for dimensions
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
ºC
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The value of VCC is provided in Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic
discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
MIN
MAX
1.65
5.5
1.5
Low-level input voltage
V
0.65 × VCC
1.7
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
VCC = 3 V
VCC = 4.5 V
(1)
4
–4
–8
–16
mA
–24
–32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TJ
Junction temperature
8
16
VCC = 3 V
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
UNIT
ns/V
5
150
Operating free-air temperature
DBV and DCK packages
–40
125
YZP package
–40
85
°C
°C
6.4 Thermal Information
SN74LVC1G80
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
YZP (DSBGA)
5 PINS
5 PINS
5 PINS
UNIT
243.4
278.9
136.9
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
179
121.3
1.3
°C/W
RθJB
Junction-to-board thermal resistance
77.6
65.6
32.6
°C/W
ψJT
Junction-to-top characterization parameter
58.4
7.5
6.3
°C/W
ψJB
Junction-to-board characterization parameter
77
64.9
32.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.2
IOH = –8 mA
2.3 V
1.9
3V
2.3
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
3.8
0.4
3V
IOL = 32 mA
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
IO = 0
TA = –40°C to
85°C
UNIT
V
2.4
4.5 V
IOL = 24 mA
(1)
MAX
IOH = –32 mA
IOL = 16 mA
CLK or D inputs
TYP (1)
VCC – 0.1
1.65 V
IOH = –24 mA
II
MIN
IOH = –4 mA
IOH = –16 mA
VOL
VCC
V
0.55
4.5 V
0.55
0 to 5.5 V
±10
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Timing Requirements: TA = –40°C to +85°C
over recommended operating free-air temperature range, TA = –40°C to +85°C (unless otherwise noted) (see Figure 2)
VCC
MIN
MAX
UNIT
160
MHz
VCC = 1.8 V ± 0.15 V
fclock
VCC = 2.5 V ± 0.2 V
Clock frequency
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
VCC = 1.8 V ± 0.15 V
tw
VCC = 2.5 V ± 0.2 V
Pulse duration, CLK high or low
VCC = 3.3 V ± 0.3 V
2.5
ns
VCC = 5.5 V ± 0.5 V
Data high
tsu
Setup time before CLK↑
Data low
th
Hold time, data after CLK↑
VCC = 1.8 V ± 0.15 V
2.3
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
2.5
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
0
VCC = 2.5 V ± 0.2 V
0.2
VCC = 3.3 V ± 0.3 V
0.9
VCC = 5.5 V ± 0.5 V
0.4
ns
ns
6.7 Timing Requirements: TA = –40°C to +125°C
over recommended operating free-air temperature range, TA = –40°C to +125°C (unless otherwise noted) (see Figure 2)
VCC
MIN
MAX
UNIT
160
MHz
VCC = 1.8 V ± 0.15 V
fclock
VCC = 2.5 V ± 0.2 V
Clock frequency
VCC = 3.3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
VCC = 1.8 V ± 0.15 V
tw
VCC = 2.5 V ± 0.2 V
Pulse duration, CLK high or low
VCC = 3.3 V ± 0.3 V
2.5
ns
VCC = 5.5 V ± 0.5 V
Data high
tsu
Setup time before CLK↑
Data low
th
6
Hold time, data after CLK↑
VCC = 1.8 V ± 0.15 V
2.3
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
2.5
VCC = 2.5 V ± 0.2 V
1.5
VCC = 3.3 V ± 0.3 V
1.3
VCC = 5.5 V ± 0.5 V
1.1
VCC = 1.8 V ± 0.15 V
0
VCC = 2.5 V ± 0.2 V
0.2
VCC = 3.3 V ± 0.3 V
0.9
VCC = 5.5 V ± 0.5 V
0.4
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ns
ns
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SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
6.8 Switching Characteristics: TA = –40°C to +85°C, CL = 15 pF
over recommended operating free-air temperature range, TA = –40°C to +85°C, CL = 15 pF (unless otherwise noted) (see
Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
160
VCC = 3.3 V ± 0.3 V
MHz
VCC = 5 V ± 0.5 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
3
VCC = 2.5 V ± 0.2 V
1.5
9.1
6
VCC = 3.3 V ± 0.3 V
1.3
4.2
VCC = 5 V ± 0.5 V
1.1
3.8
ns
6.9 Switching Characteristics: TA = –40°C to +85°C, CL = 30 pF or 50 pF
over recommended operating free-air temperature range, TA = –40°C to +85°C, CL = 30 pF or 50 pF (unless otherwise noted)
(see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
VCC = 3.3 V ± 0.3 V
160
MHz
VCC = 5 V ± 0.5 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
4.4
VCC = 2.5 V ± 0.2 V
2.3
7
VCC = 3.3 V ± 0.3 V
2
5.2
1.3
4.5
VCC = 5 V ± 0.5 V
9.9
ns
6.10 Switching Characteristics: TA = –40°C to +125°C, CL = 30 pF or 50 pF
over recommended operating free-air temperature range, TA = –40°C to +125°C, CL = 30 pF or 50 pF (unless otherwise
noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
MAX
UNIT
VCC = 1.8 V ± 0.15 V
VCC = 2.5 V ± 0.2 V
fmax
VCC = 3.3 V ± 0.3 V
160
MHz
VCC = 5 V ± 0.5 V
tpd
CLK
Q
VCC = 1.8 V ± 0.15 V
4.4
12.5
VCC = 2.5 V ± 0.2 V
2.3
8.5
VCC = 3.3 V ± 0.3 V
2
6
1.3
5.5
VCC = 5 V ± 0.5 V
ns
6.11 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
VCC = 1.8 V
24
VCC = 2.5 V
24
VCC = 3.3 V
25
VCC = 5 V
27
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UNIT
pF
7
SN74LVC1G80
SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
www.ti.com
6.12 Typical Characteristics
This plot shows the different ICC values for various voltages on the data input (D). Voltage sweep on the input is from 0 V to 7
V. VCC = 5 V.
12
11
10
9
ICC (mA)
8
7
6
5
4
3
2
1
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
VIN (V)
D001
Figure 1. ICC vs VIN
8
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SCES221S – APRIL 1999 – REVISED NOVEMBER 2016
7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SN74LVC1G80 is a single positive-edge-trigger D-type flip-flop. Data at the input (D) is transferred to the
output (Q) on the positive-going edge of the clock pulse when the setup time requirement is met. Because the
clock triggering occurs at a voltage level, it is not directly related to the rise time of the clock pulse. This allows
for data at the input to be changed without affecting the level at the output, following the hold-time interval.
8.2 Functional Block Diagram
CLK
2
C
C
C
4
TG
C
C
Q
C
C
D
1
TG
TG
TG
C
C
C
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
This device has a wide operating VCC range of 1.65 V to 5.5 V. The wide operating range allows for a broad
range of systems the device can be used in. The output can handle This device is full specified for partial-powerdown applications. When VCC = 0, the Ioff circuitry disables the outputs, preventing damaging current backflow
through the device.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74LVC1G80.
Table 1. Function Table
INPUTS
OUTPUT
Q
CLK
D
↑
H
L
↑
L
H
L
X
Q0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A useful application for the SN74LVC1G80 is using it as a frequency divider. By feeding back the output (Q) to
the input (D), the output will toggle on every rising edge of the clock waveform. In other words, the output goes
HIGH once every two clock cycles so essentially the frequency of the clock signal is divided by a factor of two.
The SN74LVC1G80 does not have preset or clear functions so the initial state of the output is unknown. This
application implements the use of a microcontroller GPIO pin to initially set the input HIGH, so the output LOW.
Initialization is not needed, but should be kept in mind. Post initialization, the GPIO pin is set to a high
impedance mode. Depending on the microcontroller, the GPIO pin could be set to an input and used to monitor
the clock division.
9.2 Typical Application
10 k
VCC
GPIO Output
1
MCU
5
D
SN74LVC1G80
CLK
2
CLK
Q
4
CLK/2
3
Figure 5. Clock Frequency Division
9.2.1 Design Requirements
For this application a resistor needs to be placed on the feedback line in order for the initialization voltage from
the microcontroller to overpower the signal coming from the output (Q). Without it the state at the input would be
challenged by the GPIO from the microcontroller and from the output of the SN74LVC1G80.
The SN74LVC1G80 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits.
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For rise time and fall time specifications, see Δt/Δv in Recommended Operating Conditions.
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions.
– Input voltages are recommended to not go below 0 V and not exceed 5.5 V for any VCC. See
Recommended Operating Conditions.
2. Recommended output conditions:
– Load currents should not exceed ±50 mA. See Absolute Maximum Ratings .
– Output voltages are recommended to not go below 0 V and not exceed the VCC voltage. See
Recommended Operating Conditions.
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Typical Application (continued)
3. Feedback resistor:
– A 10-kΩ resistor is chosen here to bias the input so the microcontroller GPIO output can initialize the
input and output. The resistor value is important because a resistance too high, say at 1 MΩ, would
cause too much of a voltage drop, causing the output to no longer be able to drive the input. On the other
hand, a resistor too low, such as a 1 Ω, would not bias enough and might cause current to flow into the
microcontroller, possibly damaging the device.
9.2.3 Application Curve
Figure 6. Frequency Division
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in
Absolute Maximum Ratings . Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, a 0.1-µF bypass capacitor is recommended. If multiple pins are
labeled VCC, then a 0.01-µF or 0.022-µF capacitor is recommended for each VCC because the VCC pins are
tied together internally. For devices with dual-supply pins operating at different voltages, for example VCC and
VDD, a 0.1-µF bypass capacitor is recommended for each supply pin. To reject different frequencies of noise,
use multiple bypass capacitors in parallel. Capacitors with values of 0.1 µF and 1 µF are commonly used in
parallel. The bypass capacitor must be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 7 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 7. Trace Example
14
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004).
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LVC1G80DBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C805, C80F, C80J,
C80R)
Samples
SN74LVC1G80DBVRE4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C80F
Samples
SN74LVC1G80DBVRG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C80F
Samples
SN74LVC1G80DBVT
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(C805, C80F, C80J,
C80R)
Samples
SN74LVC1G80DBVTG4
ACTIVE
SOT-23
DBV
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C80F
Samples
SN74LVC1G80DCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CX5, CXF, CXJ, CX
K, CXR)
Samples
SN74LVC1G80DCKRG4
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CX5
Samples
SN74LVC1G80DCKT
ACTIVE
SC70
DCK
5
250
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(CX5, CXF, CXJ, CX
K, CXR)
Samples
SN74LVC1G80YZPR
ACTIVE
DSBGA
YZP
5
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(CX7, CXN)
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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