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TPA3244
SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
TPA3244 60-W Stereo, 110-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Differential Analog Inputs
Total Output Power at 10%THD+N
– 60-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 110-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
Total Output Power at 1%THD+N
– 50-W Stereo Continuous into 8 Ω in BTL
Configuration at 30 V
– 90-W Stereo Peak into 4 Ω in BTL
Configuration at 30 V
Advanced Integrated Feedback Design with Highspeed Gate Driver Error Correction
(PurePath™ Ultra-HD)
– Signal Bandwidth up to 100 kHz for High
Frequency Content From HD Sources
– Ultra Low 0.005% THD+N at 1 W into 4 Ω and
240VAC
Copyright © 2016, Texas Instruments Incorporated
THD+N - Total Harmonic Distortion + Noise - %
Total Harmonic Distortion
TPA3244
Audio Source
And Control
BODY SIZE (NOM)
6.10mm x 14.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
RIGHT
PACKAGE
HTSSOP (44)
10
8:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
1
Po - Output Power - W
10
100
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3244
SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Audio Characteristics (BTL) ...................................... 8
Audio Characteristics (SE) ....................................... 9
Audio Characteristics (PBTL) ................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 14
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
14
15
17
17
10 Application and Implementation........................ 22
10.1 Application Information.......................................... 22
10.2 Typical Applications .............................................. 22
10.3 Typical Application, Differential (2N), PBTL (Outputs
Paralleled after LC filter) .......................................... 30
11 Power Supply Recommendations ..................... 32
11.1
11.2
11.3
11.4
Power Supplies .....................................................
Powering Up..........................................................
Powering Down .....................................................
Thermal Design.....................................................
32
32
33
34
12 Layout................................................................... 37
12.1 Layout Guidelines ................................................. 37
12.2 Layout Examples................................................... 38
13 Device and Documentation Support ................. 42
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
42
14 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2016) to Revision A
Page
•
Changed From: Preview To Production data ........................................................................................................................ 1
•
Changed pin 18 From: INPUT_B To: INPUT_A in the Pin Functions table ........................................................................... 4
•
Changed pin 17 From: INPUT_A To: INPUT_B in the Pin Functions table ........................................................................... 4
•
Changed Figure 23............................................................................................................................................................... 22
•
Changed Figure 24............................................................................................................................................................... 26
•
Changed Figure 25............................................................................................................................................................... 28
2
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
TPA3245
100-W Stereo, 200-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3250
70-W Stereo, 130-W peak PurePath™ Ultra-HD Pad Down Class-D Amplifier
TPA3251
175-W Stereo, 350-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
TPA3255
315-W Stereo, 600-W Mono PurePath™ Ultra-HD Analog-Input Class-D Amplifier
6 Pin Configuration and Functions
The TPA3244 device is available in a thermally enhanced TSSOP package.
The package type contains a PowerPad™ that is located on the bottom side of the device for thermal connection
to the PCB.
DDW Package
HTSSOP 44-Pin
(Top View)
GVDD_CD
1
44
BST_D
CLIP_OTW
2
43
BST_C
VBG
3
42
GND
FAULT
RESET
INPUT_D
4
41
GND
5
6
40
39
OUT_D
OUT_D
INPUT_C
7
38
PVDD_CD
C_START
8
37
PVDD_CD
AVDD
9
36
PVDD_CD
GND
10
35
OUT_C
GND
11
34
GND
DVDD
12
33
GND
OSC_IOP
OSC_IOM
13
14
32
31
OUT_B
PVDD_AB
FREQ_ADJ
15
30
PVDD_AB
OC_ADJ
16
29
PVDD_AB
INPUT_B
17
28
OUT_A
INPUT_A
18
27
OUT_A
M2
19
26
GND
M1
VDD
20
21
25
24
GND
BST_B
GVDD_AB
22
23
BST_A
Thermal
Pad
Not to scale
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
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Pin Functions
PIN
I/O
NAME
DESCRIPTION
NO.
AVDD
9
P
Internal voltage regulator, analog section
BST_A
23
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_A required.
BST_B
24
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_B required.
BST_C
43
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_C required.
BST_D
44
P
HS bootstrap supply (BST), external 0.033 μF capacitor to OUT_D required.
CLIP_OTW
2
O
Clipping warning and Over-temperature warning; open drain; active low. Do not connect if not used.
C_START
8
O
Startup ramp, requires a charging capacitor to GND
DVDD
12
P
Internal voltage regulator, digital section
FAULT
4
O
Shutdown signal, open drain; active low. Do not connect if not used.
FREQ_ADJ
15
O
Oscillator frequency programming pin
10, 11, 25, 26,
33, 34, 41, 42
P
GVDD_AB
22
P
Gate-drive voltage supply; AB-side, requires 0.1 µF capacitor to GND
GVDD_CD
1
P
Gate-drive voltage supply; CD-side, requires 0.1 µF capacitor to GND
INPUT_A
18
I
Input signal for half bridge A
INPUT_B
17
I
Input signal for half bridge B
INPUT_C
7
I
Input signal for half bridge C
INPUT_D
6
I
Input signal for half bridge D
M1
20
I
Mode selection 1 (LSB)
M2
19
I
Mode selection 2 (MSB)
OC_ADJ
16
I/O
Over-Current threshold programming pin
OSC_IOM
14
I/O
Oscillator synchronization interface. Do not connect if not used.
OSC_IOP
13
O
Oscillator synchronization interface. Do not connect if not used.
OUT_A
27, 28
O
Output, half bridge A
OUT_B
32
O
Output, half bridge B
OUT_C
35
O
Output, half bridge C
OUT_D
39, 40
O
Output, half bridge D
PVDD_AB
29, 30, 31
P
PVDD supply for half-bridge A and B
PVDD_CD
36, 37, 38
P
PVDD supply for half-bridge C and D
RESET
5
I
Device reset Input; active low
VDD
21
P
Power supply for internal voltage regulator requires a 10-µF capacitor with a 0.1-µF capacitor to GND for decoupling.
VBG
3
P
Internal voltage reference requires a 0.1-µF capacitor to GND for decoupling.
P
Ground, connect to PCB copper pour. Placed on bottom side of device.
GND
PowerPAD™
Ground
Table 1. Mode Selection Pins
MODE PINS
INPUT MODE
OUTPUT
CONFIGURATION
M2
M1
0
0
2N + 1
2 × BTL
0
1
2N/1N + 1
1 x BTL + 2 x SE
1
0
2N + 1
1 x PBTL
1
1
1N +1
4 x SE
(1)
4
(1)
DESCRIPTION
Stereo BTL output configuration
2.1 BTL + SE mode. Channel AB: BTL, channel C + D: SE
Parallelled BTL configuration. Connect INPUT_C and INPUT_D to GND.
Single ended output configuration
1 refers to logic high (DVDD level), 0 refers to logic low (GND).
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
MIN
MAX
UNIT
BST_X to GVDD_X (2)
–0.3
43
V
VDD to GND
–0.3
13.2
V
GVDD_X to GND (2)
–0.3
13.2
V
PVDD_X to GND (2)
–0.3
43
V
DVDD to GND
–0.3
4.2
V
AVDD to GND
–0.3
8.5
V
VBG to GND
-0.3
4.2
V
(2)
–0.3
43
V
BST_X to GND (2)
–0.3
55.5
V
OC_ADJ, M1, M2, OSC_IOP, OSC_IOM, FREQ_ADJ, C_START, to GND
–0.3
4.2
V
RESET, FAULT, CLIP_OTW, CLIP to GND
–0.3
4.2
V
INPUT_X to GND
–0.3
7
V
9
mA
0
150
°C
–40
150
°C
OUT_X to GND
Interface pins
(1)
Continuous sink current, RESET, FAULT, CLIP_OTW, CLIP, RESET to
GND
TJ
Operating junction temperature range
Tstg
Storage temperature range
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
7.2 ESD Ratings
VESD
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
±1000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
PVDD_x
Half-bridge supply
DC supply voltage
12
30
31.5
V
GVDD_x
Supply for logic regulators and gate-drive
circuitry
DC supply voltage
10.8
12
13.2
V
VDD
Digital regulator supply voltage
DC supply voltage
10.8
12
13.2
V
2.7
4
Load impedance
Output filter inductance within
recommended value range
1.5
3
1.6
2
RL(BTL)
RL(SE)
RL(PBTL)
LOUT(BTL)
LOUT(SE)
5
Output filter inductance
Minimum output inductance at IOC
5
LOUT(PBTL)
R(FREQ_ADJ)
μH
5
PWM frame rate selectable for AM
interference avoidance; 1% Resistor
tolerance
FPWM
Ω
PWM frame rate programming resistor
Nominal
430
450
470
AM1
475
500
525
AM2
575
600
625
Nominal; Master mode
29.7
30
30.3
AM1; Master mode
19.8
20
20.2
AM2; Master mode
9.9
10
10.1
1.0
kHz
kΩ
CPVDD
PVDD close decoupling capacitors
ROC
Over-current programming resistor
Resistor tolerance = 5%
22
30
kΩ
ROC(LATCHED)
Over-current programming resistor
Resistor tolerance = 5%
47
64
kΩ
V(FREQ_ADJ)
Voltage on FREQ_ADJ pin for slave
mode operation
Slave mode
TJ
Junction temperature
μF
3.3
0
V
125
°C
7.4 Thermal Information
TPA3244
THERMAL METRIC (1)
DDV 44-PINS HTSSOP
UNIT
JEDEC STANDARD 4 LAYER PCB
RθJA
Junction-to-ambient thermal resistance
23.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
9.1
°C/W
RθJB
Junction-to-board thermal resistance
3.9
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
3.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
7.5 Electrical Characteristics
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
3.3
3.6
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
DVDD
Voltage regulator, only used as reference
node
VDD = 12 V
AVDD
Voltage regulator, only used as reference
node
VDD = 12 V
7.8
IVDD
VDD supply current
Operating, 50% duty cycle
40
Idle, reset mode
13
IGVDD_X
Gate-supply current per full-bridge
50% duty cycle
15
Reset mode
2
IPVDD_X
PVDD idle current per full bridge
50% duty cycle with 10µH Output Filter Inductors
Reset mode, No switching
V
V
mA
mA
12.5
mA
1
mA
ANALOG INPUTS
RIN
Input resistance
VIN
Maximum input voltage swing
24
7
V
IIN
Maximum input current
1
mA
G
Inverting voltage Gain
VOUT/VIN
kΩ
20
dB
OSCILLATOR
Nominal, Master Mode
2.58
2.7
2.82
2.85
3
3.15
AM2, Master Mode
3.45
3.6
3.75
VIH
High level input voltage
1.86
VIL
Low level input voltage
fOSC(IO+)
AM1, Master Mode
FPWM × 6
MHz
V
1.45
V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side (LS)
RDS(on)
Drain-to-source resistance, high side (HS)
TJ = 25°C, Includes metallization resistance,
GVDD = 12 V
65
mΩ
65
mΩ
9.5
V
0.6
V
10
V
I/O PROTECTION
Undervoltage protection limit, GVDD_x and
VDD
Vuvp,VDD,GVDD
Vuvp,VDD,
GVDD,hyst
(1)
Vuvp,PVDD
Undervoltage protection limit, PVDD_x
Vuvp,PVDD,hyst
(1)
Overtemperature warning, CLIP_OTW (1)
OTW
OTWhyst
0.6
(1)
OTE (1)
115
Temperature drop needed below OTW
temperature for CLIP_OTW to be inactive
after OTW event.
125
V
135
25
Overtemperature error
145
155
°C
°C
165
°C
A reset needs to occur for FAULT to be
released following an OTE event
25
°C
OTE-OTW(differential)
(1)
OTE-OTW differential
30
°C
OLPC
Overload protection counter
fPWM = 450 kHz
2.3
ms
IOC
Overcurrent limit protection
Resistor – programmable, nominal peak current in
1Ω load, ROCP = 22 kΩ
14
A
IOC(LATCHED)
Overcurrent limit protection
Resistor – programmable, peak current in 1Ω load,
ROCP = 47kΩ
14
A
IDCspkr
DC Speaker Protection Current Threshold
BTL current imbalance threshold
1.5
A
IOCT
Overcurrent response time
Time from switching transition to flip-state induced
by overcurrent.
150
ns
IPD
Output pulldown current of each half
Connected when RESET is active to provide
bootstrap charge. Not used in SE mode.
3
mA
OTEhyst
(1)
(1)
Specified by design.
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Electrical Characteristics (continued)
PVDD_X = 30 V, GVDD_X = 12 V, VDD = 12 V, TA (Ambient temperature) = 25°C, fS = 450 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC DIGITAL SPECIFICATIONS
VIH
High level input voltage
VIL
Low level input voltage
Ilkg
Input leakage current
1.9
M1, M2, OSC_IOP, OSC_IOM, RESET
V
0.8
V
100
μA
32
kΩ
OTW/SHUTDOWN (FAULT)
RINT_PU
Internal pullup resistance, CLIP_OTW to
DVDD, FAULT to DVDD
VOH
High level output voltage
Internal pullup resistor
3.3
3.6
V
VOL
Low level output voltage
IO = 4 mA
200
500
mV
Device fanout
CLIP_OTW, FAULT
No external pullup
30
20
3
26
devices
7.6 Audio Characteristics (BTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00,
AES17 + AUX-0025 measurement filters,unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
RL = 8 Ω, 10% THD+N
Power output per channel
THD+N
50
RL = 4 Ω, 1% THD+N, 3 seconds Peak
Power (1)
90
RL = 4 Ω, 1% THD+N, Single Channel, 40
seconds Peak Power (1)
90
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
|VOS|
Output offset voltage
Inputs AC coupled to GND
SNR
Signal-to-noise ratio (2)
DNR
Dynamic range
Pidle
Power dissipation due to Idle losses (IPVDD_X)
(1)
(2)
(3)
8
110
RL = 8 Ω, 1% THD+N
PO = 0, 4 channels switching (3)
UNIT
60
RL = 4 Ω, 10% THD+N, Single Channel, 20
seconds duration (1)
PO
TYP MAX
W
0.005%
60
20
μV
60
mV
111
dB
111
dB
0.38
W
Peak Power rating using TPA3244 EVM
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses also are affected by core losses of output inductors.
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7.7 Audio Characteristics (SE)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 1 µF, MODE = 11,
AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
RL = 4 Ω, 10% THD+N
30
RL = 3 Ω, 10% THD+N
39
RL = 4 Ω, 1% THD+N
25
UNIT
PO
Power output per channel
THD+N
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
100
μV
A-weighted
100
dB
A-weighted
101
dB
0.38
W
RL = 3 Ω, 1% THD+N
SNR
Signal to noise ratio
DNR
Dynamic range
Pidle
(1)
(2)
(1)
Power dissipation due to idle losses (IPVDD_X)
W
32
0.01%
PO = 0, 4 channels switching
(2)
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
7.8 Audio Characteristics (PBTL)
PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 30 V,
GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz, ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10,
outputs paralleled before LC filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
PARAMETER
PO
TEST CONDITIONS
Power output per channel
THD+N
MIN
RL = 4 Ω, 10% THD+N
125
RL = 3 Ω, 10% THD+N
160
RL = 4 Ω, 1% THD+N
100
RL = 3 Ω, 1% THD+N
130
Total harmonic distortion + noise
1W
Vn
Output integrated noise
A-weighted, AES17 filter, Input Capacitor
Grounded
SNR
Signal to noise ratio (1)
DNR
Dynamic range
Pidle
Power dissipation due to idle losses (IPVDD_X)
(1)
(2)
TYP MAX
UNIT
W
0.005%
55
μV
A-weighted
112
dB
A-weighted
112
dB
PO = 0, 4 channels switching (2)
0.38
W
SNR is calculated relative to 1% THD+N output level.
Actual system idle losses are affected by core losses of output inductors.
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7.9 Typical Characteristics
7.9.1 BTL Configuration
10
TA = 25qC
1W
20W
60W
1
0.1
0.01
0.001
0.0003
20
100
RL = 4 Ω
1k
f - Frequency - Hz
10k
20k
10
P = 1W, 20W, 60W
TA = 25°C
TA = 25qC
1W
20W
60W
1
0.1
0.01
0.001
20
100
D001
Figure 1. Total Harmonic Distortion+Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 8 Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, mode = 00, AES17 + AUX-0025
measurement filters,unless otherwise noted.
1k
f - Frequency - Hz
10k
40k
D002
RL = 4 Ω P = 1W, 20W, 60W
AUX-0025 filter, 80 kHz analyzer BW
TA = 25°C
Figure 2. Total Harmonic Distortion+Noise vs Frequency
120
10
4:
8:
4:
8:
PO - Output Power - W
100
1
0.1
0.01
80
60
40
20
TA = 25qC
0.001
10m
100m
RL =4 Ω, 8 Ω
1
10
Po - Output Power - W
THD+N = 10%
TA = 25qC
0
10
100 200
15
20
25
PVDD - Supply Voltage - V
30
33
D004
D003
RL = 4 Ω, 8 Ω
TA = 25°C
THD+N = 10%
TA = 25°C
Figure 4. Output Power vs Supply Voltage
Figure 3. Total Harmonic Distortion + Noise vs Output
Power
100
100
4:
8:
4:
8:
Efficiency - %
PO - Output Power - W
80
60
40
10
20
THD+N = 1%
TA = 25qC
0
10
15
RL = 4 Ω, 8 Ω
20
25
PVDD - Supply Voltage - V
THD+N = 1%
30
TA = 25qC
33
D005
TA = 25°C
Figure 5. Output Power vs Supply Voltage
10
1
10m
100m
1
10
2 Channel Output Power - W
RL = 4 Ω, 8 Ω
100
300
D006
TA = 25°C
Figure 6. System Efficiency vs Output Power
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BTL Configuration (continued)
30
0
Noise Amplitude - dB
Power Loss - W
4:
8:
20
10
TA = 25qC
-20 Vref = 21.21 V
FFT size = 16384
-40
4:
-60
-80
-100
-120
-140
TA = 25qC
0
-160
0
30
60
90
120
150
2 Channel Output Power - W
RL = 4 Ω, 8 Ω
180
210
0
D007
TA = 25°C
5k
10k
15k
20k 24k
30k
f - Frequency - Hz
8 Ω, VREF = 25.46 V (1% Output power)
AUX-0025 filter, 80 kHz analyzer BW
Figure 7. System Power Loss vs Output Power
35k
40k
45k48k
D008
FFT = 16384
TA = 25°C
Figure 8. Noise Amplitude vs Frequency
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7.9.2 SE Configuration
10
2:
3:
4:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
RL = 2 Ω, 3Ω, 4Ω
1
Po - Output Power - W
10
100
10
TA = 25qC
1W
5W
20W
1
0.1
0.01
0.001
20
100
1k
f - Frequency - Hz
D009
TA = 25°C
RL = 4Ω
Figure 9. Total Harmonic Distortion+Noise vs Output
Power
20k
D010
P = 1W, 5W, 20W
TA = 25°C
60
10
2:
3:
4:
TA = 25qC
1W
5W
20W
50
1
0.1
0.01
40
30
20
10
0.001
20
10k
Figure 10. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1 kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4 Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 15 μH, CDEM = 680 nF, MODE = 11, AES17 + AUX-0025
measurement filters, unless otherwise noted.
100
1k
f - Frequency - Hz
0
10
10k 20k
D011
RL = 4Ω
P = 1W, 5W, 20W
AUX-0025 filter, 80 kHz analyzer BW
THD+N = 10%
TA = 25qC
TA = 25°C
15
20
25
PVDD - Supply Voltage - V
RL = 2 Ω, 3Ω, 4Ω
THD+N = 10%
30
33
D012
TA = 25°C
Figure 11. Total Harmonic Distortion+Noise vs Frequency
Figure 12. Output Power vs Supply Voltage
50
PO - Output Power - W
40
2:
3:
4:
30
20
10
THD+N = 1%
TA = 25qC
0
10
15
20
25
PVDD - Supply Voltage - V
RL = 2 Ω, 3Ω, 4Ω
THD+N = 1%
30
33
D013
TA = 25°C
Figure 13. Output Power vs Supply Voltage
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7.9.3 PBTL Configuration
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
All Measurements taken at audio frequency = 1kHz, PVDD_X = 30 V, GVDD_X = 12 V, RL = 4Ω, fS = 450 kHz,
ROC = 22 kΩ, TA = 25°C, Output Filter: LDEM = 10 μH, CDEM = 1 µF, MODE = 10, outputs paralleled before LC
filter, AES17 + AUX-0025 measurement filters, unless otherwise noted.
10
2:
3:
4:
1
0.1
0.01
TA = 25qC
0.001
10m
100m
RL = 2 Ω, 3Ω, 8Ω
1
10
Po - Output Power - W
100
300
TA = 25qC
1W
40W
120W
1
0.1
0.01
0.001
0.0004
20
100
1k
f - Frequency - Hz
D014
TA = 25°C
RL = 2Ω
Figure 14. Total Harmonic Distortion+Noise vs Output
Power
20k
D015
P = 1W, 40W, 120W
TA = 25°C
220
10
TA = 25qC
1W
40W
120W
2:
3:
4:
200
180
1
0.1
0.01
160
140
120
100
80
60
40
THD+N = 10%
TA = 25qC
20
0.001
20
10k
Figure 15. Total Harmonic Distortion+Noise vs Frequency
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
10
100
1k
f - Frequency - Hz
10k
0
10
40k
D016
RL = 2Ω
P = 1W, 40W, 120W
AUX-0025 filter, 80 kHz analyzer BW
TA = 25°C
15
20
25
PVDD - Supply Voltage - V
RL = 2Ω, 3Ω, 4Ω
Figure 16. Total Harmonic Distortion+Noise vs Frequency
THD+N = 10%
30
33
D017
TA = 25°C
Figure 17. Output Power vs Supply Voltage
180
PO - Output Power - W
160
140
2:
3:
4:
120
100
80
60
40
THD+N = 1%
TA = 25qC
20
0
10
15
RL = 2Ω, 3Ω, 4Ω
20
25
PVDD - Supply Voltage - V
THD+N = 1%
30
33
D018
TA = 25°C
Figure 18. Output Power vs Supply Voltage
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8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Recommended Operating Conditions,
BTL Configuration, SE Configuration and PBTL Configuration sections.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. AES-17 + AUX-0025 pre-analyzer filters are recommended to
use for Class-D amplifier measurements. In absence of such filters, a 30-kHz low-pass filter (10 Ω + 47 nF) can
be used to reduce the out of band noise remaining on the amplifier outputs.
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3244 needs only a 12-V supply in addition to the (typical) 30-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog
circuitry, AVDD and DVDD. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate
drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.
The audio signal path including gate drive and output stage is designed as identical, independent half-bridges.
For this reason, each half-bridge has separate bootstrap pins (BST_X). Power-stage supply pins (PVDD_X) and
gate drive supply pins (GVDD_X) are separate for each full bridge. Although supplied from the same 12-V
source, separating to GVDD_AB, GVDD_CD, and VDD on the printed-circuit board (PCB) by RC filters (see
application diagram for details) is recommended. These RC filters provide the recommended high-frequency
isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as
possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to
the device pins must be kept as short as possible and with as little area as possible to minimize induction (see
reference board documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the
bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. It is recommended to use 33nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33nF capacitors ensure sufficient
energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully
turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X node is
decoupled with 1-μF ceramic capacitor placed as close as possible to the supply pins. It is recommended to
follow the PCB layout of the TPA3244 reference design. For additional information on recommended power
supply and required components, see the application diagrams in this data sheet.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V powerstage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit, but it is recommended to release RESET after the power
supply is settled for minimum turn on audible artefacts. Moreover, the TPA3244 device is fully protected against
erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are noncritical within the specified range.
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9.2 Functional Block Diagrams
/CLIP_OTW
VDD
VBG
POWERUP
RESET
PROTECTION & I/O LOGIC
/FAULT
M1
M2
/RESET
C_START
VREG
AVDD
UVP
DVDD
GND
TEMP
SENSE
GVDD_AB
GND
GVDD_CD
DIFFOC
STARTUP
CONTROL
OVER-LOAD
PROTECTIO
N
CB3C
CURRENT
SENSE
OC_ADJ
OSC_IOM
OSC_IOP
OSCILLATO
R
PPSC
FREQ_ADJ
PVDD_X
OUT_X
GND
GVDD_AB
PWM
ACTIVITY
DETECTOR
BST_A
PVDD_AB
INPUT_A
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_A
GND
GVDD_AB
BST_B
PVDD_AB
INPUT_B
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_B
GND
GVDD_CD
BST_C
PVDD_CD
INPUT_C
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_C
GND
GVDD_CD
BST_D
PVDD_CD
INPUT_D
ANALOG
LOOP
FILTER
+
PWM
RECEIVER
CONTROL
TIMING
CONTROL
GATE-DRIVE
OUT_D
GND
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Functional Block Diagrams (continued)
Capacitor for
External
Filtering
and
Startup/Stop
C_START
/CLIP_OTW
/RESET
/FAULT
System
microcontroller or
Analog circuitry
BST_A
OSC_IOP
Oscillator
Synchronization
BST_B
OSC_IOM
OUT_A
INPUT_B
FREQ_ADJ
PVDD
30V
PVDD
Power Supply
Decoupling
SYSTEM
Power
Supplies
GVDD, VDD,
DVDD and
AVDD
Power Supply
Decoupling
BST_D
Bootstrap
Capacitors
Hardwire
OverCurrent
Limit
GND
GND
12V
OC_ADJ
AVDD
VBG
M2
OUT_D
2nd Order
L-C Output
Filter for
Each
H-Bridge
BST_C
DVDD
M1
Output
H-Bridge 2
VDD
Hardwire
Mode
Control
GVDD_AB, CD
Input
H-Bridge 2
INPUT_D
GND
ANALOG_IN_D
OUT_C
INPUT_C
Input DC
Blocking
Caps
OUT_B
2nd Order
L-C Output
Filter for
Each
H-Bridge
2-CHANNEL
H-BRIDGE
BTL MODE
GND
Hardwire PWM
Frame Adjust and
Master/Slave
Mode
ANALOG_IN_C
Input
H-Bridge 1
PVDD_AB, CD
ANALOG_IN_B
Output
H-Bridge 1
INPUT_A
Input DC
Blocking
Caps
ANALOG_IN_A
Bootstrap
Capacitors
GVDD (12V)/VDD (12V)
VAC
*NOTE1: Logic AND in or outside microcontroller
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Figure 19. System Block Diagram
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9.3 Feature Description
9.3.1 Error Reporting
The FAULT, and CLIP_OTW, pins are active-low, open-drain outputs. The function is for protection-mode
signaling to a system-control device.
Any fault resulting in device shutdown is signaled by the FAULT pin going low. Also, CLIP_OTW goes low when
the device junction temperature exceeds 125°C (see Table 2).
Table 2. Error Reporting
FAULT
CLIP_OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Junction
temperature higher than 125°C (overtemperature warning)
0
0
Overload (OLP) or undervoltage (UVP). Junction temperature higher than 125°C
(overtemperature warning)
0
1
Overload (OLP) or undervoltage (UVP). Junction temperature lower than 125°C
1
0
Junction temperature higher than 125°C (overtemperature warning)
1
1
Junction temperature lower than 125°C and no OLP or UVP faults (normal operation)
Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI
recommends monitoring the CLIP_OTW signal using the system microcontroller and responding to an
overtemperature warning signal by, that is, turning down the volume to prevent further heating of the device
resulting in device shutdown (OTE).
To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and
CLIP_OTW outputs.
9.4 Device Functional Modes
9.4.1 Device Protection System
The TPA3244 device contains advanced protection circuitry carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions
such as short circuits, overload, overtemperature, and undervoltage. The TPA3244 device responds to a fault by
immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overload and overtemperature error (OTE), the device automatically recovers when the fault
condition has been removed, that is, the supply voltage has increased.
The device will handle errors, as shown in Table 3.
Table 3. Device Protection
BTL
LOCAL
ERROR IN
A
B
C
D
MODE
PBTL
TURNS OFF
LOCAL
ERROR IN
A+B
C+D
MODE
SE
MODE
TURNS OFF
LOCAL
ERROR IN
TURNS OFF
A
B
C
A
A+B+C+D
D
B
C
D
A+B
C+D
Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge (non-latching,
does not assert FAULT).
9.4.1.1 Overload and Short Circuit Current Protection
The TPA3244 device has fast reacting current sensors with a programmable trip threshold (OC threshold) on all
high-side and low-side FETs. To prevent output current to increase beyond the programmed threshold, TPA3244
has the option of either limiting the output current for each switching cycle (Cycle By Cycle Current Control,
CB3C) or to perform an immediate shutdown of the output in case of excess output current (Latching Shutdown).
CB3C prevents premature shutdown due to high output current transients caused by high level music transients
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and a drop of real speaker’s load impedance, and allows the output current to be limited to a maximum
programmed level. If the maximum output current persists, i.e. the power stage being overloaded with too low
load impedance, the device will shut down the affected output channel and the affected output is put in a highimpedance (Hi- Z) state until a RESET cycle is initiated. CB3C works individually for each half bridge output. If an
over current event is triggered, CB3C performs a state flip of the half bridge output that is cleared upon beginning
of next PWM frame.
PWM_X
RISING EDGE PWM
SETS CB3C LATCH
HS PWM
LS PWM
OC EVENT RESETS
CB3C LATCH
OC THRESHOLD
OUTPUT CURRENT
OCH
HS GATE-DRIVE
LS GATE-DRIVE
Figure 20. CB3C Timing Example
During CB3C an over load counter increments for each over current event and decrease for each non-over
current PWM cycle. This allows full amplitude transients into a low speaker impedance without a shutdown
protection action. In the event of a short circuit condition, the over current protection limits the output current by
the CB3C operation and eventually shut down the affected output if the overload counter reaches its maximum
value. If a latched OC operation is required such that the device shuts down the affected output immediately
upon first detected over current event, this protection mode should be selected. The over current threshold and
mode (CB3C or Latched OC) is programmed by the OC_ADJ resistor value. The OC_ADJ resistor needs to be
within its intentional value range for either CB3C operation or Latched OC operation.
I_OC
IOC_max
IOC_min
Not Defined
R_Latch, max,
Latching OC, min level
R_Latch, min,
Latching OC, max level
R_OC, min,
CB3C, max level
R_OC, max,
CB3C, min level
ROC_ADJ
Figure 21. OC Threshold versus OC_ADJ Resistor Value Example
OC_ADJ values outside specified value range for either CB3C or latched OC operation will result in minimum OC
threshold.
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Table 4. Device Protection
OC_ADJ Resistor Value
Protection Mode
OC Threshold
22kΩ
CB3C
16.3A
24kΩ
CB3C
15.1A
27kΩ
CB3C
13.5A
30kΩ
CB3C
12.3A
47kΩ
Latched OC
16.3A
51kΩ
Latched OC
15.1A
56kΩ
Latched OC
13.5A
64kΩ
Latched OC
12.3A
9.4.1.2 Signal Clipping and Pulse Injector
A built in activity detector monitors the PWM activity of the OUT_X pins. TPA3244 is designed to drive
unclipped output signals all the way to PVDD and GND rails. In case of audio signal clipping when applying
excessive input signal voltage, or in case of CB3C current protection being active, the amplifier feedback
loop of the audio channel will respond to this condition with a saturated state, and the output PWM signals
will stop unless special circuitry is implemented to handle this situation. To prevent the output PWM signals
from stopping in a clipping or CB3C situation, narrow pulses are injejcted to the gate drive to maintain output
activity. The injected narrow pulses are injected at every 4th PWM frame, and thus the effective switching
frequency during this state is reduced to 1/4 of the normal switching frequency.
Signal clipping is signalled on the CLIP_OTW pin and is self clearing when signal level reduces and the
device reverts to normal operation. The CLIP_OTW pulses starts at the onset to output clipping, typically at a
THD level around 0.01%, resulting in narrow CLIP_OTW pulses starting with a pulse width of ~500ns.
Figure 22. Signal Clipping PWM and Speaker Output Signals
9.4.1.3 DC Speaker Protection
The output DC protection scheme protects a speaker from excess DC current in case one terminal of the
speaker is connected to the amplifier while the other is accidentally shorted to the chassis ground. Such a short
circuit results in a DC voltage of PVDD/2 across the speaker, which potentially can result in destructive current
levels. The output DC protection detects any unbalance of the output and input current of a BTL output, and in
the event of the unbalance exceeding a programmed threshold, the overload counter increments until its
maximum value and the affected output channel is shut down. DC Speaker Protection is disabled in PBTL and
SE mode operation.
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9.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
The PPSC detection system protects the device from permanent damage in the case that a power output pin
(OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent
after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is
performed at startup that is, when VDD is supplied, consequently a short to either GND_X or PVDD_X after
system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on
the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the
startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step
ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from
OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC
filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the
device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes,
and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in BTL
and PBTL output configurations, the detection is not performed in SE mode. To make sure not to trip the PPSC
detection system it is recommended not to insert a resistive load to GND_X or PVDD_X.
9.4.1.5 Overtemperature Protection OTW and OTE
The TPA3244 device has a two-level temperature-protection system that asserts an active-low warning signal
(CLIP_OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction
temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs
being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To
clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.
9.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
The UVP and POR circuits of the TPA3244 device fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are
fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical
CharacteristicsElectrical Characteristics table. Although GVDD_X and VDD are independently monitored, a
supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs
immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device
automatically resumes operation when all supply voltages have increased above the UVP threshold.
9.4.1.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restart operation requires
resetting the device by toggling RESET. Toggling RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW signal is cleared (high). A channel fault results in shutdown of the PWM activity of the
affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults being
present. TI recommends monitoring the OTW signal using the system micro controller and responding to an over
temperature warning signal by, that is, turning down the volume to prevent further heating of the device resulting
in device shutdown (OTE).
Table 5. Error Reporting
Fault/Event
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
Power On Reset
Global
FAULT pin
Self Clearing
Allow DVDD to
rise
HI-Z
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside HighSide off
ON, VDD 12V)
PVDD_X UVP
VDD UVP
AVDD UVP
POR (DVDD UVP)
BST_X UVP
20
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SLASEC6A – APRIL 2016 – REVISED NOVEMBER 2016
Table 5. Error Reporting (continued)
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed
to Clear
Output FETs
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal operation
OTE
Thermal
Shutdown
Global
FAULT pin
Latched
Toggle RESET
HI-Z
Fault/Event
OLP (CB3C>1.7ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
Latched OC
(47kΩ
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