TPSM63603
SLVSFS5A – OCTOBER 2021 – REVISED NOVEMBER 2021
TPSM63603 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 3-A Power Module
With Enhanced HotRod™ QFN Package
1 Features
3 Description
•
The TPSM63603 synchronous buck power module
is a highly integrated 36-V, 3-A DC/DC solution that
combines power MOSFETs, a shielded inductor, and
passives in an Enhanced HotRod™ QFN package.
The module has pins for VIN and VOUT located at the
corners of the package for optimized input and output
capacitor layout placement. Four larger thermal pads
beneath the module enable a simple layout and easy
handling in manufacturing.
•
•
•
•
With an output voltage from 1 V to 16 V, the
TPSM63603 is designed to quickly and easily
implement a low-EMI design in a small PCB footprint.
The total solution requires as few as four external
components and eliminates the magnetics and
compensation part selection from the design process.
Although designed for small size and simplicity
in space-constrained applications, the TPSM63603
module offers many features for robust performance:
precision enable with hysteresis for adjustable inputvoltage UVLO, resistor-programmable switch node
slew rate and spread spectrum option for improved
EMI, integrated VCC, bootstrap and input capacitors
for increased reliability and higher density, constant
switching frequency over the full load current range,
and a PGOOD indicator for sequencing, fault
protection, and output voltage monitoring.
Device Information
PART
2 Applications
•
•
•
Test and measurement, aerospace and defense
Factory automation and control
Buck and inverting buck-boost power supplies
TPSM63603S
(1)
PACKAGE
BODY SIZE (NOM)
B0QFN (30)
4.0 mm × 6.0 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN = 3 V...36 V
VIN
CIN
CBOOT
95
RBOOT
90
PGND
85
TPSM63603
EN/SYNC
VOUT = 5 V
IOUT(max) = 3 A
VLDOIN
VOUT
PG
RFBT
VCC
COUT
FB
RT
AGND
* VOUT enters dropout
if VIN < 5.4 V
Typical Schematic
80
75
VOUT = 5 V
fSW = 1 MHz
70
65
60
RFBB
CVCC
RRT
NUMBER(1)
TPSM63603
Efficiency (%)
•
Versatile synchronous buck DC/DC module
– Integrated MOSFETs, inductor, and controller
– Wide input voltage range of 3 V to 36 V
– Adjustable output voltage from 1 V to 16 V
– 4-mm × 6-mm × 1.8-mm overmolded package
– –40°C to 125°C junction temperature range
– Frequency adjustable from 200 kHz to 2.2 MHz
using the RT pin or an external SYNC signal
– Negative output voltage capability
Ultra-high efficiency across the full load range
– 93% peak efficiency at 12 VIN, 5 VOUT,1 MHz
– External bias option for improved efficiency
– Shutdown quiescent current of 0.6 µA (typical)
Ultra-low conducted and radiated EMI signatures
– Low-noise package with dual input paths and
integrated capacitors reduces switch ringing
– Spread-spectrum modulation (S suffix)
– Resistor-adjustable switch-node slew rate
– Constant-frequency FPWM mode of operation
– Meets CISPR 11 and 32 class B emissions
Suitable for scalable power supplies
– Pin compatible with the TPSM63602 (36 V, 2 A)
Inherent protection features for robust design
– Precision enable input and open-drain PGOOD
indicator for sequencing, control, and VIN UVLO
– Overcurrent and thermal shutdown protections
Create a custom design using the TPSM63603
with the WEBENCH® Power Designer
VIN = 12 V
VIN = 24 V
VIN = 36 V
55
50
0.0
0.5
1.0
1.5
2.0
Output Current (A)
2.5
3.0
Typical Efficiency, VOUT = 5 V, FSW = 1 MHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM63603
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SLVSFS5A – OCTOBER 2021 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 System Characteristics............................................... 9
6.7 Typical Characteristics.............................................. 10
6.8 Typical Characteristics: VIN = 12 V............................11
6.9 Typical Characteristics: VIN = 24 V........................... 12
6.10 Typical Characteristics: VIN = 36 V......................... 13
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................24
8 Applications and Implementation................................ 25
8.1 Application Information............................................. 25
8.2 Typical Applications.................................................. 25
9 Power Supply Recommendations................................35
10 Layout...........................................................................36
10.1 Layout Guidelines................................................... 36
10.2 Layout Example...................................................... 36
11 Device and Documentation Support..........................37
11.1 Device Support........................................................37
11.2 Documentation Support.......................................... 38
11.3 Receiving Notification of Documentation Updates.. 38
11.4 Support Resources................................................. 38
11.5 Trademarks............................................................. 38
11.6 Electrostatic Discharge Caution.............................. 38
11.7 Glossary.................................................................. 38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
Changes from Revision * (March 2021) to Revision A (November 2021)
Page
• Changed document status from Advance Information to Production Data.........................................................1
2
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Device Comparison Table
DEVICE
ORDERABLE PART
NUMBER
MODE
SPREAD
SPECTRUM
OUTPUT
VOLTAGE
EXTERNAL
SYNC
JUNCTION
TEMPERATURE
TPSM63603
TPSM63603RDHR
FPWM
No
Adjustable
Yes
–40°C to 125°C
TPSM63603S
TPSM63603SRDHR
FPWM
Yes
Adjustable
Yes
–40°C to 125°C
TPSM63603V3
TPSM63603V3RDHR
FPWM
No
Fixed 3.3 V
Yes
–40°C to 125°C
TPSM63603V5
TPSM63603V5RDHR
FPWM
No
Fixed 5 V
Yes
–40°C to 125°C
RT
PG
FB
AGND
VCC
VLDOIN
26
25
24
23
22
5 Pin Configuration and Functions
1
21
RBOOT
20
CBOOT
19
VIN
18
VIN
17
PGND
16
PGND
15
VOUT
14
VOUT
27
AGND
EN/SYNC
2
VIN
3
28
PGND
VIN
4
PGND
5
29
PGND
PGND
6
VOUT
7
30
VOUT
9
10
11
12
13
VOUT
SW
VOUT
VOUT
8
VOUT
VOUT
Figure 5-1. 30-Pin QFN, RDH Package (Top View)
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Table 5-1. Pin Functions
PIN
NAME
1
RT
TYPE(1)
DESCRIPTION
I
Frequency setting pin. This analog pin is used to set the switching frequency between 200 kHz and
2.2 MHz by placing an external resistor from this pin to AGND. Do not leave open or connect to
ground.
2
EN/SYNC
I
Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable UVLO. It also functions as the synchronization input pin. Used
to synchronize the device switching frequency to a system clock. Triggers on the rising edge of an
external clock. A capacitor can be used to AC couple the synchronization signal to this pin. The
module can be turned off by using an open-drain or collector device to connect this pin to AGND. An
external voltage divider can be placed between this pin, AGND, and VIN to create an external UVLO.
3, 4, 18, 19
VIN
P
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device. Refer to Section 10.2 for input capacitor placement
example.
5, 6, 16, 17,
28, 29
PGND
G
Power ground. This is the return current path for the power stage of the device. Connect this pad to
the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins.
See Section 10.2 for a recommended layout.
7-10, 12–15,
30
VOUT
P
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the
output load and connect external output capacitors between these pins and PGND.
11
SW
O
Switch node. Do not place any external component on this pin or connect to any signal. The amount
of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
(1)
4
NO.
20
CBOOT
I/O
Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally
connected from this pin to SW within the module to provide the bootstrap voltage. This pin is brought
out to use in conjunction with RBOOT to effectively lower the value of the internal RBOOT resistor to
adjust the SW node slew rate, if necessary.
21
RBOOT
I/O
External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected
between this pin and the CBOOT pin. This pin is brought out to use in conjunction with CBOOT
to effectively lower the value of the internal RBOOT resistor to adjust the switch node slew rate, if
necessary.
22
VLDOIN
P
Input bias voltage. Supplies the control circuitry of the power module. Input to internal LDO. Connect
to an output voltage point to improve efficiency. Connect an optional high quality 0.1-μF to 1-μF
capacitor from this pin to ground for improved noise immunity. If the output voltage is above 12 V,
connect this pin to ground.
23
VCC
O
Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads.
Connect a high-quality 1-μF ceramic capacitor from this pin to PGND.
24, 27
AGND
G
Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. This pin must be connected to PGND at a single point. See
Section 10.2 for a recommended layout.
25
FB
I
Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor
divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired
point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. When
connecting with feedback resistor divider, keep this FB trace short and as small as possible to
avoid noise coupling. See Section 10.2 for a feedback resistor placement. For a fixed output version,
connect this pin directly to output capacitor. Do not leave open or connect to ground.
26
PG
O
Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the
specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup
voltage. If not used, this pin can be left open or connected to PGND.
P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 125°C (unless otherwise noted). (1)
Input voltage
MIN
MAX
VIN to AGND, PGND
–0.3
40
V
RBOOT to SW
–0.3
5.5
V
CBOOT to SW
–0.3
5.5
V
VLDOIN to AGND, PGND
–0.3
16
V
EN/SYNC to AGND, PGND
–0.3
40
V
RT to AGND, PGND
–0.3
5.5
V
FB to AGND, PGND
–0.3
16
V
PG to AGND, PGND
0
20
V
–1
2
V
VCC to AGND, PGND
–0.3
5.5
V
SW to AGND, PGND(2)
–0.3
40
V
VOUT to AGND, PGND
–0.3
16
V
PGND to AGND
Output voltage
UNIT
Input current
PG
–
10
mA
TJ
Junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
Tstg
Storage temperature
–55
150
°C
260
°C
Peak reflow case temperature
Maximum number of reflows allowed
3
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
(1)
(2)
1500
G
20
G
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
Input voltage
VIN (Input voltage range after start-up)
Input voltage
VLDOIN
Output voltage
VOUT(1)
Output voltage
VOUT(1)
TPSM63603V3
Output voltage
VOUT(1)
TPSM63603V5
Output current
IOUT(2)
Frequency
FSW set by RT or SYNC
Input current
PG
Output voltage
PG
TJ
TA
(1)
(2)
NOM
3
1
MAX
UNIT
36
V
12.5
V
16
V
3.3
V
5
V
0
3
200
2200
kHz
A
2
mA
0
16
V
Operating junction temperature
–40
125
°C
Operating ambient temperature
–40
105
°C
Under no conditions should the output voltage be allowed to fall below zero volts.
Maximum continuous DC current may be derated when operating with high switching frequency and/or high ambient temperature.
Refer to the Typical Characteristics section for details.
6.4 Thermal Information
TPSM63603
THERMAL METRIC(1)
RDH (QFN)
UNIT
30 PINS
RθJA
Junction-to-ambient thermal resistance (TPSM63603 EVM)
29.1
°C/W
RθJA
Junction-to-ambient thermal resistance(2)
33.5
°C/W
4.1
°C/W
21.5
°C/W
ψJT
Junction-to-top characterization
ψJB
Junction-to-board characterization parameter(4)
(1)
(2)
(3)
(4)
6
parameter(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 64-mm x 83-mm four-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information see the Layout
section.
The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
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6.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Needed to start up (over IOUT range)
VIN
Input operating voltage range
VIN_HYS
Hysteresis(1)
IQ_VIN
Input operating quiescent current (non-switching)
ISDN_VIN
VIN shutdown quiescent current
Once operating (over IOUT range)
3.95
3
36
V
36
V
1.0
V
TA = 25°C, VEN/SYNC = 3.3 V, VFB = 1.5 V
4
µA
VEN/SYNC = 0 V, TA = 25°C
3
µA
ENABLE
VEN_RISE
EN voltage rising threshold
VEN_FALL
EN voltage falling threshold
1.161
VEN_HYS
EN voltage hysteresis
0.275
VEN_WAKE
EN wake-up threshold
0.4
IEN
Input current into EN/SYNC (non-switching)
tEN
EN HIGH to start of switching delay(1)
1.263
1.365
0.91
VEN/SYNC = 3.3 V, VFB = 1.5 V
0.353
V
V
0.404
V
V
1.65
µA
0.7
ms
INTERNAL LDO VCC
VCC
VCC_UVLO
Internal LDO VCC output voltage
VCC UVLO rising threshold
hysteresis(2)
VCC_UVLO_HYS
VCC UVLO
IVLDOIN
Input current into VLDOIN pin (non-switching,
maximum at TA = 125℃)(3)
3.4 V ≤ VLDOIN ≤ 12.5 V
3.3
V
VLDOIN = 3.1 V, Non-switching
3.1
V
VLDOIN < 3.1 V(1)
3.6
V
VIN < 3.6 V(2)
3.6
V
Hysteresis below VCC_UVLO
1.1
V
VEN/SYNC = 3.3 V, VFB = 1.5 V
25
31.2
µA
16
V
FEEDBACK
Adjustable output voltage range (TPSM63603)
Fixed output voltage (TPSM63603V3)
1
Over the IOUT range
3.3
V
5
V
Feedback voltage
TA = 25°C, IOUT = 0 A
1.0
V
VFB_ACC
Feedback voltage accuracy
Over the VIN range, VOUT = 1 V, IOUT = 0
A, FSW = 200 kHz
VFB
Load Regulation
TA = 25°C, 0 A ≤ IOUT ≤ 3 A
0.1
%
VFB
Line Regulation
TA = 25°C, IOUT = 0 A, 4.0 V ≤ VIN ≤ 36 V
0.1
%
IFB
Input current into FB pin
VFB = 1.0 V
10
nA
IOUT
Output current
TA = 25°C
IOCL
Output over-current (DC) limit threshold
IL_HS
High-side switch current limit
IL_LS
Low-side switch current limit
IL_NEG
Negative current limit
VHICCUP
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
VOUT
Fixed output voltage (TPSM63603V5)
VFB
–1
+1
%
CURRENT
tW
0
3.0
4.9
Duty cycle approaches 0%
A
A
5.6
6.2
6.8
A
2.9
3.4
3.8
A
Not during soft start
Short circuit wait time ("hiccup" time before soft start)
(1)
–3
A
40
%
80
ms
SOFT-START
tSS
Time from first SW pulse to VREF at 90%
VIN ≥ 4.2 V
3.5
5
7
ms
tSS2
Time from first SW pulse to release of FPWM lockout
if output not in regulation(1)
VIN ≥ 4.2 V
9.5
13
17
ms
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6.5 Electrical Characteristics (continued)
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
107%
110%
94%
96.5%
UNIT
POWER GOOD
PGOV
PG upper threshold - rising
% of VOUT setting
105%
PGUV
PG lower threshold - falling
% of VOUT setting
92%
PGHYS
PG upper threshold hysteresis (rising & falling)
% of VOUT setting
VIN_PG_VALID
Input voltage for valid PG output
46 μA pull-up, VEN/SYNC = 0 V
VPG_LOW
Low level PG function output voltage
2 mA pullup to PG pin, VEN/SYNC = 3.3 V
IPG
Input current into PG pin when open drain output is
high
VPG = 3.3 V
IOV
Pull down current at the SW node under over voltage
condition
tPG_FLT_RISE
Delay time to PG high signal
tPG_FLT_FALL
Glitch filter time constant for PG function
1.3%
1.0
V
0.4
1.5
V
10
nA
0.5
mA
2.0
2.5
120
ms
µs
SWITCHING FREQUENCY
fSW_RANGE
Switching frequency range by RT or SYNC
200
fSW_RT1
Default switching frequency by RT
RRT = 66.5 kΩ
fSW_RT2
Default switching frequency by RT
VIN = 12 V, RRT = 5.76 kΩ
fS_SS
Frequency span of spread spectrum operation –
largest deviation from center frequency
Spread spectrum active (TPSM63603S)
fPSS
Spread spectrum pattern frequency(1)
Spread spectrum active, fSW = 2.1 MHz
2200
kHz
180
200
220
kHz
1980
2200
2420
kHz
1.5
Hz
28
µs
2%
SYNCHRONIZATION
VEN_SYNC
Edge amplitude necessary to sync using EN/SYNC
tB
Blanking of EN after rising or falling edges(1)
tSYNC_EDGE
Enable sync signal hold time after edge for
edge recognition(1)
Rise/fall time < 30 ns
2.4
V
4
100
ns
POWER STAGE
VBOOT_UVLO
Voltage on CBOOT pin compared to SW which will
turn off high-side switch
tON_MIN
Minimum ON pulse width(1)
tON_MAX
Maximum ON pulse width(1)
tOFF_MIN
Minimum OFF pulse width
2.1
VOUT = 1 V, IOUT = 1 A, RBOOT shorted to
CBOOT
55
V
70
9
VIN = 4 V, IOUT = 1 A, RBOOT shorted to
CBOOT
ns
µs
65
85
ns
168
180
°C
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (1)
THYST
Thermal shutdown hysteresis (1)
(1)
(2)
(3)
8
Temperature rising
158
10
°C
Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
Production Tested with VIN = 3 V.
This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating. For additional information, reference the Systems Characteristics Table and the Input
Supply Current Section.
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6.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IIN
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V, VEN/SYNC = VIN, VVLDOIN = VOUT, FSW = 800
kHz, IOUT = 0 A
10
mA
OUTPUT VOLTAGE
VFB
Load regulation
VOUT = 3.3 V, VIN = 24 V, IOUT = 0.1 A to full load
1
mV
VFB
Line regulation
VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 3 A
6
mV
VOUT
Load transient
VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A @ 2 A/μs, COUT(derated) =
49 uF
50
mV
VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 800 kHz
89.5
%
VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 800 kHz
87.5
%
VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
91
%
VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
88.1
%
VOUT = 12 V, VIN = 24 V, IOUT = 1.5 A, VLDOIN = VOUT, FSW = 2 MHz
94.1
%
EFFICIENCY
η
Efficiency
CAPACITANCE
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6.7 Typical Characteristics
VIN = 24 V, unless otherwise specified.
4
1.01
1.005
3
FB Voltage (V)
Shutdown Current (A)
TJ = -40C
TJ = 25C
TJ = 125C
2
1
0.995
1
0.99
-50
0
0
6
12
18
24
Input Voltage (V)
30
VEN/SYNC = 0 V
70
60
60
MOSFET RDS(on) (m)
RT Resistance (k)
70
50
40
30
20
600
110
1
105
PG Threshold (%)
Enable Threshold Voltage (V)
1.2
0.8
0.6
VEN Rising
VEN Falling
VEN_WAKE Rising
VEN_WAKE Falling
-25
High-side MOSFET
Low-side MOSFET
-25
0
25
50
75
Junction Temperature (°C)
100
Figure 6-5. Enable Thresholds
125
100
95
90
OV Tripping
OV Recovery
UV Recovery
UV Tripping
85
0
25
50
75
Junction Temperature (°C)
100
Figure 6-4. High-Side and Low-Side MOSFET
RDS(on)
115
0
-50
10
30
1.4
0.2
125
40
10
-50
800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
Figure 6-3. Switching Frequency Set by RT
Resistor
0.4
100
50
20
10
400
0
25
50
75
Junction Temperature (°C)
Figure 6-2. Feedback Voltage
Figure 6-1. Shutdown Supply Current
0
200
-25
36
125
80
-50
-25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 6-6. Power-Good (PG) Thresholds
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6.8 Typical Characteristics: VIN = 12 V
1.5
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
1.2
Power Dissipation (W)
Efficiency (%)
Refer to Section 8.2 for circuit designs.
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
0.9
0.6
0.3
0.0
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
VLDOIN = VOUT
2.5
3
Figure 6-8. Power Dissipation
22
115
VOUT, FSW
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.8 V, 600 kHz
18
105
Ambient Temperature (°C)
20
Output Voltage Ripple (mV)
1.5
2
Output Current (A)
VLDOIN = VOUT
Figure 6-7. Efficiency
16
14
12
10
95
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
8
25
6
0
0.5
1
1.5
2
Output Current (A)
2.5
0
3
115
105
105
95
95
Ambient Temperature (°C)
115
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
35
1
1.5
2
Output Current (A)
2.5
3
Figure 6-10. Safe Operating Area
VOUT = 1.8 V, FSW = 600 kHz
Figure 6-9. Output Voltage Ripple
45
0.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Ambient Temperature (°C)
1
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
0.5
1
1.5
2
Output Current (A)
2.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-11. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
3
0
0.5
1
1.5
2
Output Current (A)
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-12. Safe Operating Area
VOUT = 5.0 V, FSW = 1 MHz
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6.9 Typical Characteristics: VIN = 24 V
2.5
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
2.0
Power Dissipation (W)
Efficiency (%)
Refer to Section 8.2 for circuit designs.
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
1.5
1.0
0.5
0.0
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
VLDOIN = VOUT
3
115
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.5 V, 750 kHz
29
26
105
Ambient Temperature (°C)
32
Output Voltage Ripple (mV)
2.5
Figure 6-14. Power Dissipation
35
23
20
17
95
85
75
65
55
14
45
11
35
Airflow
400LFM
200LFM
100LFM
Nat conv
25
8
0
0.5
1
1.5
2
Output Current (A)
2.5
0
3
115
105
105
95
95
Ambient Temperature (°C)
115
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
35
1
1.5
2
Output Current (A)
2.5
3
Figure 6-16. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
Figure 6-15. Output Voltage Ripple
45
0.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Ambient Temperature (°C)
1.5
2
Output Current (A)
VLDOIN = VOUT
Figure 6-13. Efficiency
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
0.5
1
1.5
2
Output Current (A)
2.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-17. Safe Operating Area
VOUT = 5.0 V, FSW = 1 MHz
12
1
3
0
0.5
1
1.5
2
Output Current (A)
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-18. Safe Operating Area
VOUT = 12 V, FSW = 2 MHz
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6.10 Typical Characteristics: VIN = 36 V
3.0
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
2.4
Power Dissipation (W)
Efficiency (%)
Refer to Section 8.2 for circuit designs.
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
1.8
1.2
0.6
0.0
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
VLDOIN = VOUT
2.5
3
Figure 6-20. Power Dissipation
40
115
VOUT, FSW
12 V, 2.0 MHz
5.0 V, 1.0 MHz
3.3 V, 800 kHz
32
105
Ambient Temperature (°C)
36
Output Voltage Ripple (mV)
1.5
2
Output Current (A)
VLDOIN = VOUT
Figure 6-19. Efficiency
28
24
20
16
95
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
12
25
8
0
0.5
1
1.5
2
Output Current (A)
2.5
0
3
115
105
105
95
95
Ambient Temperature (°C)
115
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
35
1
1.5
2
Output Current (A)
2.5
3
Figure 6-22. Safe Operating Area
VOUT = 3.3 V, FSW = 800 kHz
Figure 6-21. Output Voltage Ripple
45
0.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
COUT = 2 × 47-µF ceramic, 25-V, 1206 case size
Ambient Temperature (°C)
1
85
75
65
55
45
Airflow
400LFM
200LFM
100LFM
Nat conv
35
25
25
0
0.5
1
1.5
2
Output Current (A)
2.5
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-23. Safe Operating Area
VOUT = 5.0 V, FSW = 1 MHz
3
0
0.5
1
1.5
2
Output Current (A)
2.5
3
Device soldered to a 64-mm × 83-mm, 4-layer PCB
Figure 6-24. Safe Operating Area
VOUT = 12 V, FSW = 2 MHz
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7 Detailed Description
7.1 Overview
The TPSM63603 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V
supply voltage. The device is intended for step-down conversions from 5-V, 12-V, and 24-V supply rails. With an
integrated power controller, inductor, and MOSFETs, the TPSM63603 delivers up to 3-A DC load current, with
high efficiency and ultra-low input quiescent current, in a very small solution size. Although designed for simple
implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop
compensation is not required, reducing design time and external component count.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,
the TPSM63603 incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI
• Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switchvoltage ringing, and radiated field coupling
• Pseudo-random spread spectrum (PRSS) modulation in the TPSM63603S reduces peak emissions
• Clock synchronization and FPWM mode enable constant switching frequency across the load current range
• Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching
• Adjustable switch-node slew rate, which allows optimization of EMI at higher frequency harmonics
The TPSM63603 module also includes inherent protection features for robust system requirements:
•
•
An open-drain PGOOD indicator for power-rail sequencing and fault reporting
Precision enable input with hysteresis, providing
– Programmable line undervoltage lockout (UVLO)
– Remote ON/OFF capability
Internally fixed output-voltage soft start with monotonic startup into prebiased loads
Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
Thermal shutdown with automatic recovery.
•
•
•
These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement
is designed for simple layout, requiring few external components. See Section 10 for layout example.
7.2 Functional Block Diagram
VLDOIN
RT
VIN
LDO bias
subregulator
Oscillator
RRT
VCC
CVCC
UVLO
SYNC
detect
RENT
Optional
external bias
(from VOUT)
OTP
VIN
VIN = 3 V to 36 V
Shutdown
logic
Precision
enable for
VIN UVLO
EN/SYNC
Enable
logic
RBOOT
100
RENB
PG
CBOOT
OCP
PGOOD
indicator
PGOOD
logic
SW
RFBT
To VOUT
sense point
Power
stage
and
control
logic
FB
UVLO
OTP
+
RFBB
VREF
OCP
Comp
2.2 µH
VOUT
CIN
VOUT = 1 V to 16 V
IOUT(max) = 3 A
Soft start
COUT
EN
PGND
Adjustable
output
variant only
14
AGND
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7.3 Feature Description
7.3.1 Input Voltage Range
With a steady-state input voltage range from 3 V to 36 V, the TPSM63603 module is intended for step-down
conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in Figure 7-1 shows all the
necessary components to implement a TPSM63603-based buck regulator using a single input supply.
VIN = 3 to 36 V
Precision
Enable UVLO
Optional
synchronization
SYNC
optional
VIN
VIN
CIN2
CIN1
PGND
RENT
TPSM63603
CSYNC
EN/SYNC
1 nF
PGND
VCC
RENB
CVCC
VLDOIN
Optional
VOUT = 1 to 16 V
external bias I
OUT(max) = 3 A
VOUT
VOUT
COUT
RPG
CBOOT
PGOOD
indicator
RRT
PG
RBOOT
RT
FB
AGND
PGND
RFBT
RFBB
Figure 7-1. TPSM63603 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
Take extra care to make sure that the voltage at the VIN pins of the module does not exceed the absolute
maximum voltage rating of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds
the absolute maximum ratings can damage the IC.
7.3.2 Adjustable Output Voltage (FB)
The TPSM63603 has an adjustable output voltage range of 1 V to 16 V. Setting the output voltage requires two
resistors, RFBT and RFBB (see Figure 7-2). Connect RFBT between VOUT, at the regulation point, and the FB pin.
Connect RFBB between the FB pin and AGND (pin 10). The recommended value of RFBB is 10 kΩ. The value for
RFBT can be calculated using Equation 1. Table 7-1 lists the standard resistor values for several output voltages
and the recommended switching frequency. The minimum required output capacitance for each output voltage is
also included in Table 7-1. The capacitance values listed represent the effective capacitance, taking into account
the effects of DC bias and temperature variation.
(1)
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VOUT
RFBT
FB
RFBB
10 kΩ
AGND
Figure 7-2. FB Resistor Divider
Table 7-1. Standard RFBT Values, Recommended FSW and Minimum COUT
VOUT (V)
RFBT (kΩ) (1)
RECOMMENDED
FSW (kHz)
COUT(MIN) (µF)
(EFFECTIVE)
VOUT (V)
RFBT (kΩ) (1)
RECOMMENDED
FSW (kHz)
COUT(MIN) (µF)
(EFFECTIVE)
1.0
Short
400
300
3.3
23.2
800
40
1.2
2
500
200
5.0
40.2
1000
25
1.5
4.99
500
160
7.5
64.9
1300
20
1.8
8.06
600
120
10
90.9
1500
15
2.0
10
600
100
12
110
2000
5
2.5
15
750
65
15
140
2200
4
3.0
20
750
50
16
150
2200
3
(1)
RFBB = 10 kΩ.
Note that higher feedback resistances consume less DC current, which is mandatory if light-load efficiency is
critical. However, RFBT larger than 1 MΩ is not recommended as the feedback path becomes more susceptible
to noise. High feedback resistance generally requires more careful layout of the feedback path. It is important to
keep the feedback trace as short as possible while keeping the feedback trace away from the noisy area of the
PCB. For more layout recommendations, see Section 10.
Fixed Output Voltage Variants
The TPSM63603V3 and TPSM63603V5 are the fixed output voltage variants of the module with 3.3-V and 5-V
fixed output voltages, respectively. In these variants, the resistor feedback dividers are located internal to the
module. Therefore, the FB pin can be connected directly to output voltage regulation point.
7.3.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the module due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over
a wide temperature range. Equation 2 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the
output current.
ICIN,rms
16
§
2
D ˜ ¨ IOUT ˜ 1 D
¨
©
2
'IL ·
¸
12 ¸
¹
(2)
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where
•
D = VOUT / VIN = the module duty cycle
Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source
and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of
amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors
conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive
component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component,
Equation 3 gives the peak-to-peak ripple voltage amplitude:
IOUT ˜ D ˜ 1 D
'VIN
FSW ˜ CIN
IOUT ˜ RESR
(3)
Equation 4 gives the input capacitance required for a particular load current:
CIN t
D ˜ 1 D ˜ IOUT
FSW ˜ 'VIN RESR ˜ IOUT
(4)
where
•
ΔVIN is the input voltage ripple specification.
The TPSM63603 requires a minimum of 2 × 4.7 µF of ceramic type input capacitance. Only use high-quality
ceramic type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a
low impedance source to the converter in addition to supplying the ripple current and isolating switching noise
from other circuits. Additional capacitance can be required for applications with transient load requirements.
The voltage rating of input capacitors must be greater than the maximum input voltage. To compensate for the
derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing
multiple capacitors in parallel. Table 7-2 includes a preferred list of capacitors by vendor.
Table 7-2. Recommended Input Capacitors
CAPACITOR CHARACTERISTICS
VENDOR(1)
DIELECTRIC
PART NUMBER
CASE SIZE
TDK
X7R
C3216X7R1H475K160AC
Murata
X7R
TDK
X7R
Murata
X7S
GCM31CC71H475KA03L
(1)
VOLTAGE RATING (V)
CAPACITANCE (2)
(µF)
1206
50
4.7
GRM31CR71H475KA12L
1206
50
4.7
CGA6P3X7R1H475K250AB
1210
50
4.7
1206
50
4.7
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
(2)
7.3.4 Output Capacitors
Table 7-1 lists the TPSM63603 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package
size, voltage rating, and dielectric material contribute to differences between the standard rated value and the
actual effective value of the capacitance.
When adding additional capacitance above COUT(MIN), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 7-3 for a preferred list of output capacitors by vendor.
Table 7-3. Recommended Output Capacitors
TEMPERATURE
COEFFICIENT
PART NUMBER
CASE SIZE
TDK
X7R
CGA5L1X7R1C106K160AC
Murata
X7R
GCM31CR71C106KA64L
VENDOR(1)
CAPACITOR CHARACTERISTICS
VOLTAGE (V)
CAPACITANCE(2) (µF)
1206
16
10
1206
16
10
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Table 7-3. Recommended Output Capacitors (continued)
TEMPERATURE
COEFFICIENT
PART NUMBER
CASE SIZE
TDK
X7R
C3216X7R1E106K160AB
Murata
X7S
GCJ31CC71E106KA15L
Murata
X6S
Murata
X7R
VENDOR(1)
(1)
(2)
CAPACITOR CHARACTERISTICS
VOLTAGE (V)
CAPACITANCE(2) (µF)
1206
25
10
1206
25
10
GRM31CC81E226K
1206
25
22
GRM32ER71E226M
1210
25
22
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
7.3.5 Switching Frequency (RT)
The switching frequency range of the TPSM63603 is 200 kHz to 2.2 MHz. The switching frequency can easily
be set by connecting a resistor (RRT) between the RT pin and AGND. Use Equation 5 to calculate the RRT value
for a desired frequency or simply select from Table 7-4. Note that a resistor value outside of the recommended
range can cause the device to shut down. This prevents unintended operation if RT pin is shorted to ground or
left open. Do not apply a pulsed signal to this pin to force synchronization. If synchronization is needed, refer to
Section 7.3.7.
The switching frequency must be selected based on the output voltage setting of the device. See Table 7-4 for
RRT resistor values and the allowable output voltage range for a given switching frequency for common input
voltages.
(5)
Table 7-4. Switching Frequency Versus Output Voltage (IOUT = 3 A)
VIN = 5 V
FSW (kHz) RRT (kΩ)
18
VIN = 12 V
VOUT RANGE (V)
VIN = 24 V
VOUT RANGE (V)
VIN = 36 V
VOUT RANGE (V)
VOUT RANGE (V)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
200
66.5
1.0
2.0
1.0
2.0
1.0
1.5
1.0
1.5
400
33.2
1.0
3.0
1.0
4.0
1.0
3.3
1.2
3.0
600
22.1
1.0
3.5
1.0
6.0
1.5
6.0
1.8
5.0
800
16.5
1.0
3.5
1.0
7.0
1.5
9.0
2.5
7.0
1000
13.0
1.0
3.0
1.0
8.0
2.0
12.0
3.0
10.0
1200
10.7
1.0
3.0
1.5
9.0
2.5
13.0
3.5
14.0
1400
9.09
1.0
3.0
1.5
9.5
3.0
14.0
4.0
16.0
1600
8.06
1.0
3.0
1.5
9.0
3.0
15.0
4.5
16.0
1800
6.98
1.0
3.0
2.0
9.0
3.5
16.0
5.0
16.0
2000
6.34
1.2
2.5
2.0
9.0
4.0
16.0
5.5
16.0
2200
5.626
1.2
2.5
2.0
9.0
4.5
16.0
6.0
16.0
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7.3.6 Output ON/OFF Enable (EN/SYNC) and VIN UVLO
The EN/SYNC pin provides precision ON and OFF control for the TPSM63603. Once the EN/SYNC pin voltage
exceeds the threshold voltage and VIN is above the minimum turn-on threshold, the device starts operation. The
simplest way to enable the TPSM63603 is to connect EN/SYNC directly to VIN. This allows the TPSM63603 to
start up when VIN is within its valid operating range. However, many applications benefit from the employment
of an enable divider network as shown in Figure 7-3, which establishes a precision input undervoltage lockout
(UVLO). This can be used for sequencing, to prevent re-triggering the device when used with long input cables,
or to reduce the occurrence of deep discharge of a battery power source. An external logic signal can also be
used to drive the enable input to toggle the output on and off and for system sequencing or protection.
VIN
VIN
RENT
EN/SYNC
RENB
AGND
Figure 7-3. VIN UVLO Using the EN/SYNC Pin
RENB can be calculated using Equation 6.
(6)
where
•
•
•
A typical value for RENT is 100 kΩ.
VEN is 1.263 V (typical).
VIN(ON) is the desired start-up input voltage.
Note
The EN/SYNC pin can also be used as an external synchronization clock input. See Section 7.3.7 for
additional information. A blanking time of 4 µs to 28 µs is applied to the enable logic after a clock edge
is detected. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs.
Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in
shutdown mode.
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7.3.7 Frequency Synchronization (EN/SYNC)
The TPSM63603 can be synchronized to an external clock using the EN/SYNC pin. The synchronization
frequency range is 200 kHz to 2.2 MHz. The internal oscillator can be synchronized by AC coupling a positive
clock edge into the EN/SYNC pin, as shown in Figure 7-4. It is recommended to keep the parallel combination
value of RENT and RENB in the 100-kΩ range. RENT is required for synchronization, but RENB can be left open.
The external clock must be off before start-up to allow proper start-up sequencing. After a valid synchronization
signal is applied for 2048 cycles, the clock frequency changes to that of the applied signal.
VIN
RENT
CSYNC
EN/SYNC
Clock
Source
RENB
AGND
AGND
Figure 7-4. Typical Synchronization Using the EN/SYNC Pin
Referring to Figure 7-5, the AC-coupled voltage edge at the EN/SYNC pin must exceed the SYNC amplitude
threshold, VEN_SYNC, of 2.4 V to trip the internal synchronization pulse detector. In addition, the minimum EN/
SYNC rising pulse and falling pulse durations must be longer than the SYNC signal hold time, tSYNC_EDGE, of
100 ns and shorter than the minimum blanking time, t B. A 3.3-V or higher amplitude pulse signal coupled through
a 1-nF capacitor, CSYNC, is suggested.
EN Voltage
VEN
tSYNC_EDGE
VEN_SYNC
0
VEN_SYNC
t
tSYNC_EDGE
Time
Figure 7-5. Typical SYNC Waveform
7.3.8 Spread Spectrum
Spread spectrum is a factory option included in part number TPSM63603S. The purpose of spread spectrum
is to eliminate peak emissions at specific frequencies by spreading these peaks across a wider range of
frequencies than a part with fixed frequency operation. In most systems with the TPSM63603S, low-frequency
conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more
difficult design criterion is reduction of emissions at higher harmonics that fall in the FM band. These harmonics
often couple to the environment through electric fields around the switch node and inductor. The TPSM63603S
uses a ±2% spread of frequencies that can spread energy smoothly across the FM and TV bands but is small
enough to limit sub-harmonic emissions below the device switching frequency. Peak emissions at the module
switching frequency are only reduced slightly, by less than 1 dB, while peaks in the FM band are typically
reduced by more than 6 dB.
20
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The TPSM63603S uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register
(LFSR). This intelligent pseudo-random generator limits cycle to cycle frequency changes to limit output ripple.
The pseudo-random pattern repeats at less than 1.5 Hz, which is below the audio band.
The spread spectrum is only available while the clock of TPSM63603S device are free running at their natural
frequency. Any of the following conditions overrides spread spectrum, turning it off:
•
•
•
•
The clock is slowed during dropout.
Spread spectrum is active even if there is no load.
At a high input voltage/low output voltage ratio when the device operates at minimum on-time, the internal
clock is slowed, disabling spread spectrum.
The clock is synchronized with an external clock.
7.3.9 Power Good Monitor (PG)
The TPSM63603 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the
PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. The
PGOOD pin voltage goes low when the feedback voltage is outside of the PGOOD thresholds. This occurs
during the following:
•
•
•
•
While the device is disabled
In current limit
In thermal shutdown
During normal start-up, when the output voltage has not reach its regulation value
A glitch filter prevents false flag operation for short excursions (
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