CYV15G0101EQ

CYV15G0101EQ Multi-Rate Video Cable Equalizer (SOIC) Features • • • • • • • • • • • • • • • • Multi-Rate Adaptive Equalization SMPTE 292M, SMPTE 344M, and SMPTE 259M Compliant Supports DVB-ASI at 270 Mbps Cable Length Indicator for HD-SDI and SD-SDI data rates Maximum Cable Length Adjustment for HD-SDI and SD-SDI data rates Carrier detect and Mute functionality for HD-SDI and SD-SDI data rates Equalizer Bypass Mode Seamless connection with HOTLink II™ Family Equalizes up to 350m of Belden 1694A coaxial cable at 270 Mbps Equalizes up to 140m of Belden 1694A coaxial cable at 1.485 Gbps Low Power 160 mW @ 3.3V Single 3.3V supply 16-pin SOIC 0.18-µm CMOS technology Pb-free and RoHS compliant Pin-compatible to existing equalizer devices Functional Description The CYV15G0101EQ is a multi-rate adaptive equalizer designed to equalize and restore signals received over 75Ω coaxial cable. The equalizer is designed to meet SMPTE 292M, SMPTE 344M, and SMPTE 259M data rates. The CYV15G0101EQ is optimized to equalize up to 350m of Belden 1694A coaxial cable at 270 Mbps and up to 140m of Belden 1694A coaxial cable at 1.485 Gbps. The CYV15G0101EQ connects seamlessly to the HOTLink II family of transceiver devices. The CYV15G0101EQ has DC restoration for compensation of the DC content of the SMPTE pathological patterns. A cable length indicator (CLI) provides an indication of the cable length being equalized at HD-SDI and SD-SDI data rates. The Maximum cable length adjust (MCLADJ) sets the approximate maximum cable length to be equalized at SD and HD data rates. The CYV15G0101EQ’s differential serial outputs (SDO, SDO) mute when the approximate cable length set by MCLADJ is reached. CD/MUTE is a bidirectional pin that provides an indication of the signal being present at the equalizer inputs. It also controls muting the outputs of the equalizer at HD and SD data rates. Power consumption is typically 160 mW at 3.3V. Equalizer System Connection Diagram HOTLink IITM Serializer Cable Driver Serial Links Copper Cable Connections CYV15G0101EQ Multi-Rate Cable Equalizer HOTLink IITM Deserializer Cypress Semiconductor Corporation Document #: 001-04184 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 11, 2006 [+] [+] Feedback CYV15G0101EQ Equalizer Block Diagram CYV15G0101EQ Multi-Rate Video Cable Equalizer Block Diagram CYV15G0101EQ Multi-Rate Video Cable Equalizer Block Diagram CLI MCLADJ Cable Length Analog Indicator and Mute Threshold Block Carrier Detect and Mute Control Block CD / MUTE DC Restore BYPASS SDI, SDI Equalizer Differential Output SDO, SDO Pin Configuration (Top View) 16-PIN SOIC Top View CLI VCC GND SDI SDI GND AGC+ AGC2 3 4 CYV15G0101EQ 5 6 7 8 12 11 10 9 SDO GND MCLADJ BYPASS 16 15 14 13 CD/MUTE VCC GND SDO Document #: 001-04184 Rev. *D Page 2 of 10 [+] [+] Feedback CYV15G0101EQ Pin Descriptions CYV15G0101EQ Single Channel Cable Equalizer Name Control Signals CLI CD/MUTE Analog Output LVTTL I/O I/O Characteristics Signal Description Cable Length Indicator: CLI provides an analog voltage proportional to the cable length being equalized. CLI works at both SD-SDI and HD-SDI data rates. Carrier Detect/Mute Indicator: Output: When the incoming data stream is present, the CD/MUTE outputs a voltage less than 0.8V. When the incoming data stream is not present, the CD/MUTE outputs a voltage greater than 2.9V. Input: When the CD/MUTE pin is tied to ground, the equalizer’s differential serial outputs are not muted and the MCLADJ setting is overwritten. When the CD/MUTE pin is tied to VCC, the equalizer’s differential serial outputs are muted and the MCLADJ setting is overwritten. MCLADJ Analog Input Maximum Cable Length Adjust: The maximum cable length to be equalized is set by the voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is reached, the differential output is muted. MCLADJ works at both SD and HD data rates. Equalizer Bypass: When BYPASS is tied to VCC, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without performing equalization. When BYPASS is tied to GND, the incoming video data stream is equalized and presented at the equalizer‘s serial differential outputs (SDO, SDO). In equalizer bypass mode, CD/MUTE is not functional. BYPASS LVTTL Input AGC± SDO, SDO SDI, SDI Analog Differential Output Differential Input Power Gnd Automatic Gain Control: A capacitor of 1 µF should be placed between the AGC± pins. Differential Serial Outputs: The equalized serial video data stream is presented at the SDO/SDO differential serial CML output. Differential Serial Inputs: SDI/SDI can accept either a single ended or differential serial video data stream over 75Ω coaxial cable. +3.3V Power. Connect to Ground. equalizer meets all pathological requirements for SMPTE 292M as defined by RP198 and for SMPTE 259M as defined by RP178. The CYV15G0101EQ multi-rate Cable Equalizer is auto-adaptive from 143 Mbps to 1.485 Gbps. The CYV15G0101EQ equalizer has variable gain and multiple equalization stages that reverse the effects of the cable. This equalization is achieved by separate regulation of the lower and higher frequency components in the signal to give a clean eye. The CYV15G0101EQ has DC restoration for compensating the DC content of the SMPTE pathological patterns. Power VCC GND Equalizer Operation The CYV15G0101EQ is a high-speed adaptive cable equalizer designed to equalize standard definition (SD) and high definition (HD) serial digital interface (SDI) video data streams. CYV15G0101EQ equalizer is optimized to equalize up to 350m of Belden 1694A cable at 270 Mbps and up to 140m of Belden 1694A cable at 1.485 Gbps. The CYV15G0101EQ equalizer contains one power supply and typically consumes 160 mW power at 3.3V. The multi-rate equalizer is designed to meet the SMPTE 259M, SMPTE 292M, SMPTE 344M and DVB-ASI video standards. The Document #: 001-04184 Rev. *D Page 3 of 10 [+] [+] Feedback CYV15G0101EQ SDI, SDI The CYV15G0101EQ accepts single-ended or differential serial video data streams over 75Ω coaxial cable. It is recommended to AC-couple the SDI, SDI inputs as they are internally biased to 1.2V. CD/MUTE Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that provides an indication of the signal being present at the equalizer’s input, or it controls the muting of the equalizer’s output. The (CD/MUTE) operates for both HD and SD data rates. If CD/MUTE is used as an output and the incoming data stream is not present, the voltage at the CD/MUTE output will be greater than 2.9V. If CD/MUTE is used as an output and the incoming data stream is present, then the voltage at the CD/MUTE output will be less than 0.8V. If CD/MUTE is used as an input and is tied to ground, the equalizer serial outputs are not muted and the MCLADJ setting is overwritten. If the CD/MUTE is used as an input and is tied to VCC, then the equalizer serial outputs are muted and the MCLADJ setting is overwritten. When an invalid signal or a signal transmitted with a launch amplitude of less than 500 mV at HD data-rates is received, the equalizer’s serial outputs are muted and the MCLADJ setting is overwritten. SDO, SDO The CYV15G0101EQ has differential serial output interface drivers that use current mode logic [CML] drivers to provide source matching for the transmission line. These outputs can be either AC coupled or DC coupled to the HOTLink II SerDes device. CLI Cable Length Indicator (CLI) is an analog output that gives an output voltage proportional to the cable length being equalized. CLI gives an approximation of the length of cable at the differential serial inputs (SDI, SDI). CLI works at high definition (HD) data rates as well as standard definition (SD) data rates. The graph in Figure 2 illustrates the CLI output voltage at various Belden 1694A cable lengths. With an increase in cable length, CLI output voltage decreases. BYPASS The CYV15G0101EQ has a bypass mode that allows the user to bypass the equalizer’s equalization and DC restoration functions. When the Bypass mode is tied to VCC, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without performing equalization. When BYPASS is tied to GND, the incoming video data stream is equalized and presented at the equalizer‘s differential serial outputs (SDO, SDO). In equalizer bypass mode, CD/MUTE is not functional. MCLADJ Maximum Cable Length Adjust (MCLADJ) sets the approximate maximum amount of cable to be equalized. When the maximum cable length set by MCLADJ is reached, the outputs are muted. MCLADJ works at SD as well HD data rates. If the MCLADJ voltage is greater than the CLI output voltage, the equalizer serial differential outputs (SDO, SDO) are muted. If the MCLADJ voltage is less than CLI voltage, then the equalizer’s differential serial outputs (SDO, SDO) are not muted and the incoming data stream is equalized. The graph in Figure 1 illustrates the voltage needed at MCLADJ input to equalize various Belden 1694A cable lengths for SD and HD data rates. The MCLADJ pin can be left unconnected in applications that do not require muting of the outputs. AGC A capacitor of 1 µF should be placed between the AGC± pins of the CYV15G0101EQ equalizer. Document #: 001-04184 Rev. *D Page 4 of 10 [+] Feedback CYV15G0101EQ Maximum Ratings Above which the useful life may be impaired. User guidelines only, not tested Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +3.8V DC Voltage Applied to Outputs in High-Z State .......................................–0.5V to VCC + 0.5V DC Input Voltage......................................–0.5V to VCC+0.5V Electro Static Discharge (ESD) HBM .......................> 2000 V (per JEDEC EIA/JESD-A114A) Latch-Up Current ....................................................> 200 mA Power-up Requirements The CYV15G0101EQ contains one power-supply. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range Range Commercial Ambient Temperature 0°C to +70°C VCC +3.3V ±5% DC Electrical Characteristics Parameter VCC PD IS VCMOUT VCMIN Power Description Supply Voltage[1] Consumption[2] Voltage[1] Supply Current[1] Output Common Mode Input Common Mode Voltage[1] [Bypass = High] Input Common Mode Voltage[1] [Bypass = Low] Test Conditions – – – Load = 50Ω – – – – – – Carrier Not Present Carrier Present Min. to Mute Max. to Activate Min. 3.135 125 38 – 1 0 2.3 1.5 1.1 0.4 2.9 – 2.5 – Typ. 3.3 160 48 VCC – ∆VSDO/2 1.24 1.24 2.65 1.9 1.3 0.72 – – – – Max. 3.465 190 58 – 1.4 2.9 2.95 2.3 1.6 1.02 – 0.8 – 1 Unit V mW mA V V V V V V V V V V V – – – – VCD/MUTE(OL) VCD/MUTE VCD/MUTE CLI DC Voltage (0m)[1] CLI DC Voltage (no MCLADJ Range[3] signal)[1] Floating MCLADJ DC Voltage[1] VCD/MUTE(OH) CD/MUTE Output Voltage[1] CD/MUTE Input Voltage Required to Force Outputs to Mute[1] CD/MUTE Input Voltage Required to Force Active[1] Notes 1. Production test. 2. Calculated results from production test. 3. Not tested. Based on characterization. Document #: 001-04184 Rev. *D Page 5 of 10 [+] [+] Feedback CYV15G0101EQ AC Electrical Characteristics Parameter – VSDI VSDI ∆VSDO – Description Serial Input Data Rate Input Voltage Swing Input Voltage Swing Output Voltage Swing[1] Maximum Equalized Cable Length[1] [1] Test Conditions – Single ended, at the transmitter, HD data rate Single ended, at the transmitter, SD data rate Differentialp-p, 50Ω load 270 Mbps, Belden 1694A, 800 mV transmit amplitude, equalizer pathological pattern, 0.2 UI equalizer output jitter 1.485 Gbps, Belden 1694A, 800 mV transmit amplitude, equalizer pathological pattern, 0.25 UI equalizer output jitter Min. 143 500[5] 500[6] 500 – Typ. – 800[1] 800[1] 700 350 Max. 1485 1200 1200 950 – Unit Mbps mV mV mV m – 140 – m – – – – – – – – – Output Rise/Fall Time[3, 4] Output Rise/Fall Time[3, 4] Mismatch in Rise/Fall Overshoot[3, 4] Input Return Loss[3] Input Resistance[3, 4] Input Capacitance[3, 4] Output Resistance[3, 4] time[3, 4] Duty cycle distortion[3, 4] 20% - 80%, HD data rate 20% - 80%, SD data rate – HD color bar pattern – – Single ended Single ended Single ended 80 80 – – – 15 – – – 120 120 – 20 – – 2.5 1 50 220 270 30 – 10 – – – – ps ps ps ps % dB kΩ pF Ω Notes 4. Not tested. Guaranteed by design simulations. 5. Based on characterization across temperature and voltage with 140m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern. 6. Based on characterization across temperature and voltage with 350m of Belden 1694A cable, transmitting SMPTE Equalizer Pathological Test Pattern. Document #: 001-04184 Rev. *D Page 6 of 10 [+] Feedback CYV15G0101EQ Typical Performance Graphs (Unless Otherwise mentioned, VCC = 3.3V, TA = 25°C) Figure 1. MCLADJ Input Voltage vs. Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates 2.7 2.6 2.5 2.4 VOLTAGE (V) 2.3 2.2 2.1 2 1.9 1.8 1.7 0 50 100 150 200 250 300 350 CABLE LENGTH (m ) Figure 2. CLI Output Voltage Vs. Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates 2.7 2.6 2.5 2.4 VOLTAGE (V) 2.3 2.2 2.1 2 1.9 1.8 1.7 0 50 100 150 200 250 300 350 CABLE LENGTH (m ) Document #: 001-04184 Rev. *D Page 7 of 10 [+] [+] Feedback CYV15G0101EQ Typical Application Circuit Figure 3. Interfacing CYV15G0101EQ to the HOTLink II SerDes CD/ MUTE CL I +3.3V LFI RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXOP RXST2 RXST1 RXST0 RXCLK+ RXCLK − RXCLKC+ RXLE SDASEL LPEN INSEL IN1+ IN1 − FRAMCHAR RFEN RFMODE DECMODE RXCKSEL RXMODE RXRATE +3.3V C12 0.01 µF Z0 2 Z0 R18 C10 0. 01 µF 16 15 14 13 12 11 10 9 Z0 CD/MUTE CLI VCC VCC VEE VEE SDO SDI SDO SDI VEE VEE MCLADJ AGC+ BYPASS AGC− 1 2 3 4 5 6 7 8 C15 1 µF 1 µF R16 BN JAC C K 75 Ω C16 L2 75Ω 6.4 n H + 1 µF 37.4 Ω R15 75 Ω R14 CYV15G0101EQ MCL ADJ C11 CYV15G0101DXB Ordering Information Ordering Code CYV15G0101EQ-SXC Package Name SZ16.15 Package Type Pb-Free16-lead 150-mil SOIC Operating Range 0 to 70°C Document #: 001-04184 Rev. *D Page 8 of 10 [+] [+] Feedback CYV15G0101EQ Package Dimension Figure 4. 16-Lead (150-Mil) SOIC S16.15 51-85068-*B Equalizer is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-04184 Rev. *D Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CYV15G0101EQ Document History Page Document Title: CYV15G0101EQ Multi-Rate Cable Equalizer Document Number: 001-04184 REV. ** *A *B *C *D ECN NO. 389196 394763 431556 504487 514998 ISSUE DATE SEE ECN SEE ECN SEE ECN SEE ECN SEE ECN ORIG. OF CHANGE BCD BCD BCD FRE FRE DESCRIPTION OF CHANGE New Preliminary Data Sheet Updated Preliminary Data Sheet for release to the internet Changed AC and DC Parameters Updated AC and DC Parameters. Changed Data Sheet status from preliminary to final Fixed typo in diagrams on page 2 Document #: 001-04184 Rev. *D Page 10 of 10 [+] [+] Feedback