13201

Freescale Semiconductor Technical Data Document Number: MC13201 Rev. 1.3, 04/2008 MC13201 MC13201 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard Device MC13201FC Package Information Plastic Package Case 1311-03 QFN -32 Ordering Information Device Marking 13201 13201 Package QFN-32 QFN-32 MC13201FCR2 (Tape and Reel) 1 Introduction Contents 1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 Data Transfer Mode . . . . . . . . . . . . . . . . . . . . 5 Electrical Characteristics . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . 10 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14 Crystal Oscillator Reference Frequency . . 18 Packaging Information . . . . . . . . . . . . . . . . . 27 The MC13201 is a short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13201 contains a complete packet data modem which is compliant with the IEEE® 802.15.4 Standard PHY (Physical) layer. This allows the development of proprietary point-to-point and star networks based on the 802.15.4 packet structure and modulation format. For full 802.15.4 Standard compliance, the MC13202 and Freescale's 802.15.4 MAC software are required. When combined with an appropriate microcontroller (MCU), the MC13201 provides a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor can be scaled to fit applications ranging from simple point-to-point systems to star networks. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008. All rights reserved. For more detailed information about MC13201 operation, refer to the MC13201 Reference Manual, (MC13201RM). Applications include, but are not limited to, the following: • Residential and commercial automation — Lighting control — Security — Access control — Heating, ventilation, air-conditioning (HVAC) — Automated meter reading (AMR) • Industrial Control — Asset tracking and monitoring — Homeland security — Process management — Environmental monitoring and control — HVAC — Automated meter reading • Health Care — Patient monitoring — Fitness monitoring • Consumer — Human interface devices (keyboard, mice, etc.) — Remote control — Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifiers (PA), onboard RF transmit/receive (T/R) switch for single port use, PLL with internal voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the 802.15.4 Standard. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control. 2 • • • • • Features Recommended power supply range: 2.0 to 3.4 V Fully compliant 802.15.4 Standard transceiver supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode Operates on one of 16 selectable channels in the 2.4 GHz band -1 to 0 dBm nominal output power, programmable from -27 dBm to +3 dBm typical Receive sensitivity of = 15 MHz Frequency Error Tolerance Symbol Rate Error Tolerance Table 5. Transmitter AC Electrical Characteristics (VBATT, VDDINT = 2.7 V, TA = 25 °C, fref = 16 MHz, unless otherwise noted.) Characteristic Power Spectral Density (-40 to +85 °C) Absolute limit Power Spectral Density (-40 to +85 °C) Relative limit Nominal Output Power 1 Symbol Min - Typ -47 47 -1 4 Max - Unit dBm Pout -5 dBm dBm Maximum Output Power2 Error Vector Magnitude Output Power Control Range Over the Air Data Rate 2nd Harmonic 3rd Harmonic 1 2 EVM - 20 30 250 TBD TBD 45 - % dB kbps dBc dBc SPI Register 12 programmed to 0x00BC which sets output power to nominal (-1 dBm typical). SPI Register 12 programmed to 0x00FF which sets output power to maximum. MC13201 Technical Data, Rev. 1.3, Freescale Semiconductor 9 Table 6. Digital Timing Specifications (VBATT, VDDINT = 2.7 V, TA = 25 °C, frequency = 16 MHz, unless otherwise noted. SPI timing parameters are referenced to Figure 8. Symbol T0 T1 T2 T3 T4 T5 T6 T7 SPICLK period Pulse width, SPICLK low Pulse width, SPICLK high Delay time, MISO data valid from falling SPICLK Setup time, CE low to rising SPICLK Delay time, MISO valid from CE low Setup time, MOSI valid to rising SPICLK Hold time, MOSI valid from rising SPICLK RST minimum pulse width low (asserted) 250 Parameter Min 125 50 50 15 15 15 15 15 Typ Max Unit nS nS nS nS nS nS nS nS nS Figure 6 shows a typical AC parameter evaluation circuit. U5 L1 PAO_M PAO_P RFIN_P RFIN_M CT_Bias MC1320x 6 5 2 1 3 L4 1.8nH 1.8nH 3 L2 6.8nH 2 4 Z1 1 5 6 LDB212G4005C-001 L3 3.9nH C1 1.0pF R2 0R Not Mounted ANT1 F_Antenna R1 0R C2 10pF 2 3 4 5 1 J1 SMA_edge_Receptac Figure 6. RF Parametric Evaluation Circuit 6 Functional Description The following sections provide a detailed description of the MC13201 functionality, including operating modes, and the Serial Peripheral Interface (SPI). 6.1 MC13201 Operational Modes The MC13201 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 7. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics. MC13201 Technical Data, Rev. 1.3, 10 Freescale Semiconductor Table 7. MC13201 Mode Definitions and Transition Times Mode Off Hibernate Doze Definition All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ Transition Time To or From Idle 10 - 25 ms to Idle Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is 7 - 20 ms to Idle retained. Crystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = (300 + 1/CLKO) µs to Idle 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Crystal Reference Oscillator On. Receiver On. Crystal Reference Oscillator On. Transmitter On. 144 µs from Idle 144 µs from Idle Idle Receive Transmit 6.2 Serial Peripheral Interface (SPI) The host microcontroller directs the MC13201, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13201 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13201. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13201 presents data to the master on the MISO output. A typical interconnection to a microcontroller is shown in Figure 7. MC13201 Technical Data, Rev. 1.3, Freescale Semiconductor 11 MCU MC13201 Shift Register RxD TxD Sclk MISO MOSI SPICLK Shift Register Baud Rate Generator Chip Enable (CE) CE Figure 7. SPI Interface Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory. 6.2.1 SPI Burst Operation The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13201 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8. SPI Burst CE 1 SPICLK T4 T6 T5 T7 MISO MOSI Valid Valid T3 Valid T2 T1 T0 2 3 4 5 6 7 8 Figure 8. SPI Single Burst Timing Diagram SPI digital timing specifications are shown in Table 6. MC13201 Technical Data, Rev. 1.3, 12 Freescale Semiconductor 6.2.2 SPI Transaction Operation Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13201 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13201 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13201 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. The number of payload bytes sent will always be an even integer. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13201 Reference Manual, (MC13201RM) for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9. CE Clock Burst SPICLK MISO Valid Valid MOSI Valid Header Read data Figure 9. SPI Read Transaction Diagram MC13201 Technical Data, Rev. 1.3, Freescale Semiconductor 13 7 Pin # 1 Pin Connections Table 8. Pin Function Description Pin Name RFIN_M Type RF Input Description RF input/output negative. Functionality When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA When used with internal T/R switch, this is a bi-directional RF port for the internal LNA and PA 2 RFIN_P RF Input RF input/output positive. 3 CT_Bias Control voltage Bias voltage/control signal for external When used with internal T/R switch, RF components provides RX ground reference and TX VDDA reference for use with external balun. Can also be used as a control signal for external LNA, PA, or T/R switch. Tie to Ground. 4 5 NC PAO_P RF Output /DC Input RF Power Amplifier Output Positive. Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used. 6 PAO_M RF Output/DC Input RF Power Amplifier Output Negative. Open drain. Connect to VDDA through a bias network when used with an external balun. Not used when internal T/R switch is used. Input Test mode pin. Must be grounded for normal operation. See Footnote 1. See Footnote 1. 7 8 9 10 SM GPIO41 GPIO31 GPIO21 Digital Input/ Output General Purpose Input/Output 4. Digital Input/ Output General Purpose Input/Output 3. Digital Input/ Output General Purpose Input/Output 2. See Footnote 1. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a “CRC Valid” indicator. Digital Input/ Output General Purpose Input/Output 1. See Footnote 1. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an “Out of Idle” indicator. Digital Input Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. 11 GPIO11 12 RST MC13201 Technical Data, Rev. 1.3, 14 Freescale Semiconductor Table 8. Pin Function Description (continued) Pin # 13 Pin Name RXTXEN2 Type Digital Input Description Active High. Low to high transition initiates RX or TX sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. Functionality See Footnote 2 14 ATTN2 Digital Input Active Low Attention. Transitions IC See Footnote 2 from either Hibernate or Doze Modes to Idle. Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. External clock input for the SPI interface. Master Out/Slave In. Dedicated SPI data input. Master In/Slave Out. Dedicated SPI data output. See Footnote 2 See Footnote 2 See Footnote 3 15 CLKO Digital Output 16 17 18 19 20 SPICLK2 MOSI2 MISO3 CE2 IRQ Digital Clock Input Digital Input Digital Output Digital Input Digital Output Active Low Chip Enable. Enables SPI See Footnote 2 transfers. Active Low Interrupt Request. Open drain device. Programmable 40 kΩ internal pull-up. Interrupt can be serviced every 6 µs with 4 kΩ. Decouple to ground. 2.0 to 3.4 V. Decouple to ground. See Footnote 1 See Footnote 1 See Footnote 1 Connect to 16 MHz crystal and load capacitor. 21 22 23 24 25 26 VDDD VDDINT GPIO51 GPIO61 GPIO71 XTAL1 Power Output Power Input Digital Input/Output Digital Input/Output Digital Input/Output Input Digital regulated supply bypass. Digital interface supply & digital regulator input. Connect to Battery. General Purpose Input/Output 5. General Purpose Input/Output 6. General Purpose Input/Output 7. Crystal Reference oscillator input. MC13201 Technical Data, Rev. 1.3, Freescale Semiconductor 15 Table 8. Pin Function Description (continued) Pin # 27 Pin Name XTAL2 Type Input/Output Description Crystal Reference oscillator output Note: Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13201 Reference Manual for details. LO2 VDD supply. Connect to VDDA externally. LO1 VDD supply. Connect to VDDA externally. VCO regulated supply bypass. Analog voltage regulators Input. Connect to Battery. Analog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a bias network. Note: Do not use this pin to supply circuitry external to the chip. External paddle / flag ground. Decouple to ground. Decouple to ground. Decouple to ground. Functionality Connect to 16 MHz crystal and load capacitor. 28 29 30 31 32 VDDLO2 VDDLO1 VDDVCO VBATT VDDA Power Input Power Input Power Output Power Input Power Output EP 1 Ground Connect to ground. The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state. 2 During low power modes, input must remain driven by MCU. 3 By default MISO is tri-stated when CE is negated. For low power operation, miso_hiz_en (Bit 11, Register 07) should be set to zero so that MISO is driven low when CE is negated. MC13201 Technical Data, Rev. 1.3, 16 Freescale Semiconductor 32 VDDA 31 VBATT 30 VDDVCO 29 VDDLO1 28 VDDLO2 27 XTAL2 26 XTAL1 25 GPIO7 1 2 3 4 5 6 7 8 RFIN_M RFIN_P CT_Bias NC GPIO6 GPIO5 24 23 22 21 20 19 18 17 VDDINT VDDD EP PAO_P PAO_M SM GPIO2 MC13201 RXTXEN GPIO1 SPICLK 16 CLKO IRQ CE MISO GPIO3 GPIO4 MOSI 9 10 11 12 RST 13 14 ATTN 15 Figure 10. Pin Connections (Top View) MC13201 Technical Data, Rev. 1.3, Freescale Semiconductor 17 8 Crystal Oscillator Reference Frequency This section provides application specific information regarding crystal oscillator reference design and recommended crystal usage. 8.1 Crystal Oscillator Design Considerations The 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13201 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. Whether or not a frequency trim step will be performed in production Freescale requires the use of a 16 MHz crystal with a