IDT70V15S15J

HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM .eatures x x PRELIMINARY IDT70V16/5S/L x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial:15/20/25ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V16/5S Active: 430mW (typ.) Standby: 3.3mW (typ.) – IDT70V16/5L Active: 415mW (typ.) Standby: 660µW (typ.) IDT70V16/5 easily expands data bus width to 18 bits or x x x x x x x x more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave Busy and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (+0.3V) power supply Available in 68-pin PLCC and an 80-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds .unctional Block Diagram OEL CEL R/WL OER CER R/WR I/O0L- I/O8L I/O Control BUSYL A13L(1) A0L (2,3) I/O0R-I/O8R I/O Control BUSYR Address Decoder 14 (2,3) MEMORY ARRAY 14 Address Decoder A13R(1) A0R CEL OEL R/WL ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEML (3) INTL NOTES: 1. A13 is a NC for IDT70V15. 2. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. M/S SEMR (3) INTR 5669 drw 01 AUGUST 2002 1 ©2002 Integrated Device Technology, Inc. DSC 5669/1 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Description The IDT70V16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM. The IDT70V16/5 is designed to be used as stand-alone Dual-Port RAMs or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 430mW of power. The IDT70V16/5 is packaged in a 64-pin PLCC (Plastic Leaded Chip Carriers) and an 80-pinTQFP (Thin Quad Flatpack). Pin Configurations(1,2,3,4) 08/26/02 INDEX I/O2L I/O3L I/O4L I/O5L VSS I/O6L I/O7L VDD VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 I/O1L I/O0L I/O8L OEL R/WL SEML CEL N/C A13L(1) VDD A12L A11L A10L A9L A8L A7L A6L 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 IDT70V16/5J J68-1(5) 68-Pin PLCC Top View(6) 55 54 53 52 51 50 49 48 47 46 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A5L A4L A3L A2L A1L A0L INTL BUSYL VSS M/S BUSYR INTR A0R A1R A2R A3R A4R 5669 drw 02 , NOTES: 1. A13 is a NC for IDT70V15. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately .95 in x .95 in x .17 in. 5. This package code is used to reference the package diagram. 6. This text does not imply orientation of Part-marking. I/O7R I/O8R OER R/WR SEMR CER N/C A13R(1) VSS A12R A11R A10R A9R A8R A7R A6R A5R 2 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3,4) (con't.) I/O1L I/O0L I/O8L NC A13L(1) R/WL SEML VDD A12L A10L OEL CEL A9L A7L A8L NC A6L 63 INDEX 79 78 77 65 62 69 68 67 75 72 76 80 74 73 71 66 64 61 70 NC NC 60 59 58 57 56 55 54 08/26/02 A11L NC I/O2L I/O3L I/O4L I/O5L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NC A5L A4L A3L A2L A1L A0L INTL BUSYL VSS I/O6L I/O7L VDD NC IDT70V16/5PF PN80-1(5) 80-Pin TQFP Top View(6) 53 52 51 50 49 48 47 46 45 44 43 42 VSS M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC VSS I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R NC 27 31 34 26 36 35 38 30 33 37 24 25 28 29 32 39 40 20 22 23 21 41 I/O7R I/O8R OER A13R(1) SEMR A10R CER NC R/WR A11R A9R A8R NC A12R A7R A6R VSS A5R NC NOTES: 1. A13 is a NC for IDT70V15. 2. All V DD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. PN80-1 package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.42 3 NC 5669 drw 03 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Pin Names Left Port CEL R/WL OEL A0L - A13L (1) Right Port CER R/WR OER A0R - A13R (1) Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power (3.3V) Ground (0V) 5669 tbl 01 I/O0L - I/O8L SEML INTL BUSYL I/O0R - I/O8R SEMR INTR BUSYR M/S VCC GND NOTE: 1. A13 is a NC for IDT70V15. Truth Table I: Non-Contention Read/Write Control Inputs(1) CE H L L X R/W X L H X OE X X L H SEM H H H X Outputs I/O0-8 High-Z DATAIN DATAOUT High-Z Deselcted: Power-Down Write to Memory Read Memory Outputs Disabled 5669 tbl 02 Mode NOTE: 1. Condition: A0L — A13L ≠ A0R — A13R Truth Table II: Semaphore Read/Write Control(1) Inputs CE H H L R/W H ↑ X OE L X X SEM L L L Outputs I/O0-8 DATAOUT DATAIN ____ Mode Read Semaphore Flag Data Out (I/O0 - I/O8) Write I/O0 into Semaphore Flag Not Allowed 5669 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A 0 - A2. 4 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) TBIAS(3) TSTG TJN IOUT Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to +3.6 -55 to +125 -65 to +150 +150 50 Unit V Maximum Operating Temperature and Supply Voltage(1) Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V 5669 tbl 05 o C C C Industrial o o NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. mA 5669 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 0.3V. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected. Recommended DC Operating Conditions Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3 (1) Typ. 3.3 0 ____ Max. 3.6 0 VDD+0.3 0.8 (2) Unit V V V V 5669 tbl 06 ____ Capacitance(1)(TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) V IN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF 5669 tbl 07 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VDD + 0.3V. NOTES: 1. This parameter is determined by device characteristics but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V . DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) 70V16/5S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current (1) 70V16/5L Min. ___ Test Conditions VDD = 3.6V, VIN = 0V to VDD CE = VIH, VOUT = 0V to VDD IOL = + 4mA IOH = -4mA Min. ___ Max. 10 10 0.4 ___ Max. 5 5 0.4 ___ Unit µA µA V V 5669 tbl 08 Output Leakage Currentt(1) Output Low Voltage Output High Voltage ___ ___ ___ ___ 2.4 2.4 NOTE: 1. At VDD < 2.0V, Input leakages are undefined. 6.42 5 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V) 70V16/5X15 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Version COM'L IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (2) 150 140 ____ ____ 70V16/5X20 Com'l & Ind Typ.(2) 140 130 140 130 20 15 20 15 80 75 80 75 1.0 0.2 1.0 0.2 80 75 80 75 Max. 200 175 225 195 30 25 45 40 110 100 130 115 5 2.5 15 5 115 100 130 115 70V16/5X25 Com'l Only Typ.(2) 130 125 ____ ____ Max. 215 185 ____ ____ Max. 190 165 ____ ____ Unit mA ISB1 Standby Current (Both Ports - TTL Level Inputs) CER and C EL = VIH SEMR = SEML = VIH f = fMAX(3) 25 20 ____ ____ 35 30 ____ ____ 16 13 ____ ____ 30 25 ____ ____ mA ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and C E"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Both Ports C EL and CER > VDD - 0.2V, V IN > V DD - 0.2V or V IN < 0.2V, f = 0 (4) SEMR = SEML > VDD - 0.2V CE"A" < 0.2V and CE"B" > V DD - 0.2V(5) SEMR = SEML > VDD - 0.2V V IN > V DD - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) 85 80 ____ ____ 120 110 ____ ____ 75 72 ____ ____ 110 95 ____ ____ mA ISB3 Full Standby Current (Both Ports CMOS Level Inputs) 1.0 0.2 ____ ____ 5 2.5 ____ ____ 1.0 0.2 ____ ____ 5 2.5 ____ ____ mA ISB4 Full Standby Current (One Port CMOS Level Inputs) 85 80 ____ ____ 125 105 ____ ____ 75 70 ____ ____ 105 90 ____ ____ mA NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t RC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5669 tbl 09 Output Loads and AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1 and 2 5669 tbl 10 , 5669 drw 04 3.3V 590Ω DATAOUT BUSY INT DATAOUT 435Ω 30pF 435Ω 3.3V 590Ω 5pF* Figure 1. AC Output Test Load Figure 2. Output Test Load (for t LZ, tHZ , tWZ, tOW) *Including scope and jig. Timing of Power-Up / Power-Down CE tPU ICC 50% ISB 5669 drw 07 tPD 50% , 6 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70V16/5X15 Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time (3) Byte Enable Access Time (3) Output Enable Access Time (3) Output Hold from Address Change Output Low-Z Time (1,2) 70V16/5X20 Com'l & Ind Min. Max. 70V16/5X25 Com'l Only Min. Max. Unit Parameter Min. Max. 15 ____ ____ 20 ____ ____ 25 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 5669 tbl 11 15 15 15 10 ____ 20 20 20 12 ____ 25 25 25 13 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 3 3 ____ 3 3 ____ 3 3 ____ ____ ____ ____ Output High-Z Time(1,2) Chip Enable to Power Up Time (1,2) Chip Disable to Power Down Time (1,2) Semaphore Flag Update Pulse (OE or SEM) Semaphore Address Access (3) 10 ____ 12 ____ 15 ____ 0 ____ 0 ____ 0 ____ 15 ____ 20 ____ 25 ____ 10 ____ 10 ____ 10 ____ 15 20 25 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = V IL. 4. 'X' in part number indicates power rating (S or L). Waveform of Read Cycles(5) tRC ADDR tAA (4) tACE tAOE OE (4) (4) CE R/W tLZ DATAOUT (1) tOH VALID DATA (4) (2) tHZ BUSYOUT tBDD(3,4) 5669 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE or CE . 2. Timing depends on which signal is de-asserted first, CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD . 5. SEM = VIH. 6.42 7 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 70V16/5X15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW tSWRD tSPS Write Cycle Time Chip Enable to End-of-Write(3) Address Valid to End-of-Write Address Set-up Time (3) Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time(1,2) Data Hold Time(4) Write Enable to Output in High-Z(1,2) Output Active from End-of-Write(1,2,4) SEM Flag Write to Read Time SEM Flag Contention Window 15 12 12 0 12 0 10 ____ ____ 70V16/5X20 Com'l & Ind Min. Max. 70V16/5X25 Com'l Only Min. Max. Unit Parameter Min. Max. 20 15 15 0 15 0 15 ____ ____ 25 20 20 0 20 0 15 ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 10 ____ 12 ____ 15 ____ 0 ____ 0 ____ 0 ____ 10 ____ 12 ____ 15 ____ 0 5 5 0 5 5 0 5 5 ____ ____ ____ ____ ____ ____ 5669 tbl 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltageand temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 8 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) tAS (6) R/W tLZ DATAOUT tWZ (7) (4) tWP (2) tWR (3) tOW (4) tDW DATAIN tDH 5669 drw 08 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS R/W tEW (2) tWR (3) tDW DATAIN tDH 5669 drw 09 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP ) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 6.42 9 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW SEM tEW tDW DATAIN VALID tAS R/W tSWRD OE Write Cycle Read Cycle 5669 drw 10 VALID ADDRESS tACE tOH tSOP DATAOUT VALID(2) tWR I/O tWP tDH tAOE NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value. Timing Waveform of Semaphore Write Condition(1,3,4) A0"A"-A2 "A" MATCH SIDE (2) "A" R/W"A" SEM"A" tSPS A0"B"-A2 "B" MATCH SIDE (2) "B" R/W"B" SEM"B" 5669 drw 11 NOTES: 1. DOR = DOL =VIH, CE R = CEL =VIH. 2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/W“A” or SEM “A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 10 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 70V16/5X15 Com'l Ony Symbol BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH BUSY Access Time from Address Match BUSY Disable Time from Address Not Matched BUSY Ac cess Time from Chip Enable LOW BUSY Disable Time from Chip Enable HIGH Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data(3) Write Hold After BUSY (5) ____ 70V16/5X20 Com'l & Ind Min. Max. 70V16/5X25 Com'l Only Min. Max. Unit Parameter Min. Max. 15 15 15 15 ____ ____ 20 20 20 17 ____ ____ 20 20 20 17 ____ ns ns ns ns ns ns ns ____ ____ ____ ____ ____ ____ ____ ____ ____ 5 ____ 5 ____ 5 ____ 18 ____ 30 ____ 30 ____ 12 15 17 BUSY TIMING (M/S = VIL) tWB tWH BUSY Input to Write(4) Write Hold After BUSY (5) 0 12 ____ 0 15 ____ 0 17 ____ ns ns ____ ____ ____ PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ____ ____ 30 25 ____ ____ 45 35 ____ ____ 50 35 ns ns 5669 tbl 13 NOTES: 1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or t DDD – tDW (actual). 4. To ensure that the write cycle is inhibited during contention. 5. To ensure that a write cycle is completed after contention. 6. 'X' in part numbers indicates power rating (S or L). Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tAPS ADDR"B" (1) tDH VALID MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" tDDD NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL. 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY “A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". (3) VALID 5669 drw 12 6.42 11 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH (1) R/W"B" (2) 5669 drw 13 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC BUSY"B" 5669 drw 14 tBDC Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" tAPS ADDR"B" tBAA BUSY"B" 5669 drw 15 (2) ADDRESS "N" MATCHING ADDRESS "N" tBDA NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 12 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 70V16/5X15 Com 'l Only Sym bol INTERRUPT TIMING tA S tW R tIN S tIN R A d d re ss Se t-up Tim e Write Re co ve ry Tim e Inte rrup t S e t Tim e Inte rrup t Re se t Tim e 0 0 ____ ____ ____ ____ 70V16/5X20 Com 'l & Ind Min. Max. 70V16/5X25 Com 'l Only Min. Max. Unit Param eter Min. Max. 0 0 ____ ____ ____ ____ 0 0 ____ ____ ____ ____ ns ns ns ns 5669 tb l 1 4 15 15 20 20 20 20 NOTES: 1. 'X' in part numbers indicates power rating (S or L). Waveform of Interrupt Timing(1) tWC ADDR"A" tAS CE"A" (3) INTERRUPT SET ADDRESS (2) (4) tWR R/W"A" tINS INT"B" 5669 drw 16 (3) tRC ADDR"B" tAS CE"B" (3) INTERRUPT CLEAR ADDRESS (2) OE"B" tINR INT"B" 5669 drw 17 (3) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 6.42 13 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Truth Table III — Interrupt .lag(1) Left Port R/WL L X X X CEL L X X L OEL X X X L A13L-A0L 3FFF(4) X X 3FFE(4) INTL X X L(3) H(2) R/ WR X X L X CER X L L X Right Port OER X L X X A13R-A0R X 3FFF(4) 3FFE(4) X INTR L(2) H(3) X X Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag 5669 tbl 15 NOTES: 1. Assumes BUSY L = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. A13 is a NC for IDT70V15, therefore Interrupt Addresses are 1FFF and 1FFE. Truth Table IV — Address BUSY Arbitration Inputs CEL X H X L CER X X H L AOL-A13L AOR-A13R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3) 5669 tbl 16 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V16/5 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSY R outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. A13 a NC for IDT70V15, Address comparison will be for A0 - A 12. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D8 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D8 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free 5669 tbl 17 Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V16/5. 2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A 0 - A2. e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table. 14 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges CE MASTER Dual Port RAM BUSY (L) BUSY (R) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) BUSY (L) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) BUSY (R) 5669 drw 18 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V16/5 RAMs. .unctional Description The IDT70V16/5 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V16/5 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V16/5 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FFE where a write is defined as the CE = R/W = VIL per Truth Table III. The left port clears the interrupt by an address location 3FFE access when CER =OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFF (1FFF for IDT70V15) and to clear the interrupt flag (INTR), the right port must access location 3FFF. The message (9 bits) at 3FFE or 3FFF (1FFE or 1FFF for IDT70V15) is user-defined since it is in an addressable SRAM location. If the interrupt function is not used, address locations 3FFE and 3FFF (1FFE and 1FFF for IDT70V15) are not used as mail boxes but are still part of the random access memory. Refer to Truth Table III for the interrupt operation. Width Expansion Busy Logic Master/Slave Arrays When expanding an IDT70V16/5 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70V16/5 RAM the BUSY pin is an output if the part is used as a master (M/S pin = H), and the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying 6.42 15 Semaphores The IDT70V16/5 are extremely fast Dual-Port 16/8Kx9 Static RAMs with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are DECODER P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT70V16/5 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V16/5's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V16/5 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore .lags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V16/5 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The 16 6.42 E L I M I N A R Y IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V16/5’s Dual-Port RAM. Say the 16K x 9 RAM was to be divided into two 8K x 9 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 8K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q R PORT SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ Figure 4. IDT70V16/5 Semaphore Logic SEMAPHORE READ 5669 drw 19 , 6.42 17 P R E L I M I N A R Y P R E IDT70V16/5S/L High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM PRELIMINARY Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) PF J 80-pin TQFP (PN80-1) 68-pin PLCC (J68-1) 15 20 25 S L 70V16 70V15 NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Commercial Only Commercial & Industrial Speed in Nanoseconds Commercial Only Standard Power Low Power 144K (16K x 9-Bit) 2.5V Dual-Port RAM 72K (8K x 9-Bit) 2.5V Dual-Port RAM 5669 drw 20 Datasheet Document History 08/26/02: Initial Public Release CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 18 6.42 for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.