LT1055AMH

LT1055/LT1056 Precision, High Speed, JFET Input Operational Amplifiers FEATURES ■ ■ ■ DESCRIPTIO ■ ■ Guaranteed Offset Voltage: 150µV Max –55°C to 125°C: 500µV Max Guaranteed Drift: 4µV/°C Max Guaranteed Bias Current 70°C: 150pA Max 125°C: 2.5nA Max Guaranteed Slew Rate: 12V/µs Min Available in 8-Pin PDIP and SO Packages The LT®1055/LT1056 JFET input operational amplifiers combine precision specifications with high speed performance. For the first time, 16V/µs slew rate and 6.5MHz gain bandwidth product are simultaneously achieved with offset voltage of typically 50µV, 1.2µV/°C drift, bias currents of 40pA at 70°C and 500pA at 125°C. The 150µV maximum offset voltage specification is the best available on any JFET input operational amplifier. The LT1055 and LT1056 are differentiated by their operating currents. The lower power dissipation LT1055 achieves lower bias and offset currents and offset voltage. The additional power dissipation of the LT1056 permits higher slew rate, bandwidth and faster settling time with a slight sacrifice in DC performance. The voltage-to-frequency converter shown below is one of the many applications which utilize both the precision and high speed of the LT1055/LT1056. For a JFET input op amp with 23V/µs guaranteed slew rate, refer to the LT1022 data sheet. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIO S ■ ■ ■ ■ ■ ■ ■ Precision, High Speed Instrumentation Logarithmic Amplifiers D/A Output Amplifiers Photodiode Amplifiers Voltage-to-Frequency Converters Frequency-to-Voltage Converters Fast, Precision Sample-and-Hold TYPICAL APPLICATIO 4.7k 15V 1Hz to 10kHz Voltage-to-Frequency Converter 3M 0.001 (POLYSTYRENE) 10kHZ TRIM 5k OUTPUT 1Hz TO 10kHz 0.005% LINEARITY 0V TO 10V INPUT 75k 0.1µF 2 – + 33pF 15V 7 LT1056 6 4 –15V 1.5k NUMBER OF UNITS 22k 3 3.3M 2N3906 = 1N4148 *1% FILM –15V 0.1µF THE LOW OFFSET VOLTAGE OF LT1056 CONTRIBUTES ONLY 0.1Hz OF ERROR WHILE ITS HIGH SLEW RATE PERMITS 10kHz OPERATION. LM329 LT1055/56 TA01 U Distribution of Input Offset Voltage (H Package) 140 120 100 80 60 40 20 0 –400 200 –200 400 0 INPUT OFFSET VOLTAGE (µV) LT1055/56 TA02 U U VS = ±15V TA = 25°C 634 UNITS TESTED FROM THREE RUNS 50% TO ± 60µV 10556fc 1 LT1055/LT1056 ABSOLUTE MAXIMUM RATINGS Supply Voltage ...................................................... ±20V Differential Input Voltage ....................................... ±40V Input Voltage ......................................................... ±20V Output Short-Circuit Duration .......................... Indefinite Operating Temperature Range LT1055AM/LT1055M/LT1056AM/ LT1056M (OBSOLETE) .............. –55°C to 125°C PACKAGE/ORDER INFORMATION TOP VIEW BAL 1 –IN 2 + IN 3 V– 4 8 7 6 5 N/C V+ OUT BAL ORDER PART NUMBER BAL 1 LT1055CN8 LT1056CN8 N8 PACKAGE 8-LEAD PDIP TJMAX = 150°C, θJA = 130°C/ W TOP VIEW NC 8 BALANCE 1 –IN 2 7 V+ 6 OUT 5 BALANCE 4 V– H PACKAGE 8-LEAD TO-5 METAL CAN + IN 3 TJMAX = 150°C, θJA = 150°C/ W, θJC = 45°C/ W OBSOLETE PACKAGE Consider the N8 Package for Alternate Source Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VOS Input Offset Voltage (Note 2) CONDITIONS LT1055 H Package LT1056 H Package LT1055 N8 Package LT1056 N8 Package Fully Warmed Up TA = 25°C. VS = ± 15V, VCM = 0V unless otherwise noted. LT1055AM/LT1056AM LT1055AC/LT1056AC MIN TYP MAX — — — — — 50 50 — — 2 150 180 — — 10 LT1055M/LT1056M LT1055CH/LT1056CH LT1055CN8/LT1056CN8 MIN TYP MAX — — — — — 70 70 120 140 2 400 450 700 800 20 IOS Input Offset Current 2 U U W WW U W (Note 1) LT1055AC/LT1055C/LT1056AC/ LT1056C ................................................ 0°C to 70°C Storage Temperature Range All Devices ...................................... – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C TOP VIEW 8 7 6 5 N/C V+ OUT BAL ORDER PART NUMBER –IN 2 + IN 3 V– 4 LT1055S8 LT1056S8 S8 PART MARKING 1055 1056 S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 150°C/ W ORDER PART NUMBER LT1055ACH LT1055CH LT1055AMH LT1055MH LT1056ACH LT1056CH LT1056AMH LT1056MH UNITS µV µV µV µV pA 10556fc LT1055/LT1056 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER IB Input Bias Current Input Resistance:Differential CONDITIONS Fully Warmed Up VCM = 10V TA = 25°C. VS = ± 15V, VCM = 0V unless otherwise noted. LT1055AM/LT1056AM LT1055AC/LT1056AC MIN TYP MAX — — — — — — — — — — — 150 130 ±11 86 90 ±12 10 12 — — — — — ±10 30 1012 1012 1011 4 1.8 2.5 28 14 1.8 400 300 ±12 100 106 ±13.2 13 16 5.0 6.5 2.8 5.0 ±5 ±50 130 — — — — — — 50 20 4 — — — — — — — — — — 4.0 6.5 — LT1055M/LT1056M LT1055CH/LT1056CH LT1055CN8/LT1056CN8 MIN TYP MAX — — — — — — — — — — — 120 100 ±11 83 88 ±12 7.5 9.0 — — — — — ±10 30 1012 1012 1011 4 2.0 2.8 30 15 1.8 400 300 ±12 98 104 ±13.2 12 14 4.5 5.5 2.8 5.0 ±5 ±50 150 — — — — — — 60 22 4 — — — — — — — — — — 4.0 7.0 — UNITS pA pA Ω Ω Ω pF µVP-P µVP-P nV/√Hz nV/√Hz fA/√Hz V/mV V/mV V dB dB V V/µs V/µs MHz MHz mA mA mV Common Mode VCM = –11V to 8V VCM = 8V to 11V Input Capacitance en Input Noise Voltage Input Noise Voltage Density In AVOL Input Noise Current Density Large-Signal Voltage Gain Input Voltage Range CMRR PSRR VOUT SR GBW IS Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing Slew Rate Gain Bandwidth Product Supply Current Offset Voltage Adjustment Range RPOT = 100k f = 1MHz VCM = ±11V VS = ±10V to ±18V RL = 2k LT1055 LT1056 LT1055 LT1056 LT1055 LT1056 0.1Hz to 10Hz LT1055 LT1056 f0 = 10Hz (Note 3) f0 = 1kHz (Note 4) f0 = 10Hz, 1kHz (Note 5) V0 = ±10V RL = 2k RL = 1k The ● denotes the specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V unless otherwise noted. LT1055AC LT1056AC TYP 100 100 — — 1.2 — 10 14 ±30 ±40 250 100 105 ±13.1 LT1055CH/LT1056CH LT1055CN8/LT1056CN8 MIN TYP MAX — — — — — — — — — — 60 82 87 ±12 140 140 250 280 1.6 3.0 16 18 ±40 ±50 250 98 103 ±13.1 750 800 1250 1350 8.0 12.0 80 100 ±200 ±240 — — — — SYMBOL PARAMETER VOS Input Offset Voltage (Note 2) CONDITIONS LT1055 H Package LT1056 H Package LT1055 N8 Package LT1056 N8 Package H Package (Note 6) N8 Package (Note 6) Warmed Up TA = 70°C Warmed Up TA = 70°C VCM = ±10.5V VS = ±10V to ±18V RL = 2k LT1055 LT1056 LT1055 LT1056 ● ● ● ● ● ● ● ● ● ● ● ● ● ● MIN — — — — — — — — — — 80 85 89 ±12 MAX 330 360 — — 4.0 — 50 70 ±150 ±80 — — — — UNITS µV µV µV µV µV/°C µV/°C pA pA pA pA V/mV dB dB V 10556fc Average Temperature Coefficient of Input Offset Voltage IOS IB AVOL CMRR PSRR VOUT Input Offset Current Input Bias Current Large-Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing VO = ±10V, RL = 2k 3 LT1055/LT1056 The ● denotes the specifications which apply over the temperature range –55°C ≤ TA ≤ 125°C. VS = ±15V, VCM = 0V, unless otherwise noted. LT1055AM LT1056AM TYP 180 180 1.3 LT1055M LT1056M TYP 250 250 1.8 ELECTRICAL CHARACTERISTICS CONDITIONS SYMBOL PARAMETER VOS Input Offset Voltage (Note 2) Average Temperature Coefficient of Input Offset Voltage IOS IB AVOL CMRR PSRR VOUT Input Offset Current Input Bias Current Large-Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing MIN LT1055 LT1056 ● ● ● MAX 500 550 4.0 MIN — — — MAX 1200 1250 8.0 UNITS µV µV µV/°C — — — (Note 6) Warmed Up TA = 125°C Warmed Up TA = 125°C VCM = ± 10.5V LT1055 LT1056 LT1055 LT1056 ● ● ● ● ● ● ● ● — — — — 40 85 88 ± 12 0.20 0.25 ± 0.4 ± 0.5 120 100 104 ± 12.9 1.2 1.5 ± 2.5 ± 3.0 — — — — — — — — 35 82 86 ± 12 0.25 0.30 ± 0.5 ± 0.6 120 98 102 ±12.9 1.8 2.4 ± 4.0 ± 5.0 — — — — nA nA nA nA V/mV dB dB V VO = ± 10V, RL = 2k VS = ±10V to ±17V RL = 2k TA = 25°C. VS = ± 15V, VCM = 0V unless otherwise noted. SYMBOL PARAMETER VOS IOS IB Input Offset Voltage (Note 2) Input Offset Current Input Bias Current Input Resistance Differential Common Mode Fully Warmed Up Fully Warmed Up VCM = 10V VCM = –11V to 8V VCM = 8V to 11V 0.1Hz to 10Hz fO = 10Hz (Note 4) fO = 1kHz (Note 4) fO = 10Hz, 1kHz (Note 5) VO = ±10V RL = 2k RL = 1k 120 100 ± 11 VCM = ±11V VS = ±10V to ±18V RL = 2K LT1055 LT1056 f = 1MHz LT1055 LT1056 LT1055 LT1056 RPOT = 100k 83 88 ± 12 7.5 9.0 LT1055 LT1056 CONDITIONS LT1055CS8/LT1056CS8 MIN TYP MAX 500 5 ± 30 30 0.4 0.4 0.05 4 2.5 3.5 35 15 2.5 400 300 ± 12 98 104 ±13.2 12 14 4.5 5.5 2.8 5.0 ±5 4.0 7.0 70 22 10 1500 30 ±100 150 UNITS µV pA pA pA TΩ TΩ TΩ pF µVP-P µVP-P nV/√Hz nV/√Hz fA/√Hz V/mV V/mV V dB dB V V/µs V/µs MHz MHz mA mA mV 10556fc Input Capacitance en Input Noise Voltage Input Noise Voltage Density in AVOL Input Noise Current Density Large-Signal Voltage Gain Input Voltage Range CMRR PSRR VOUT SR GBW IS Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing Slew Rate Gain Bandwidth Product Supply Current Offset Voltage Adjustment Range 4 LT1055/LT1056 The ● denotes the specifications which apply over the temperature range 0°C ≤ TA ≤ 70°C. VS = ±15V, VCM = 0V, unless otherwise noted. SYMBOL PARAMETER VOS IOS IB AVOL CMRR PSRR VOUT Input Offset Voltage (Note 2) Average Temperature Coefficient of Input Offset Voltage Input Offset Current Input Bias Current Large-Signal Voltage Gain Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing Warmed Up, TA = 70°C Warmed Up, TA = 70°C VO = ±10V, RL = 2k VCM = ±10.5V VS = ±10V to ±18V RL = 2K CONDITIONS ● ● ● ● ● ● ● ● 60 82 87 ± 12 LT1055CS8/LT1056CS8 MIN TYP MAX 800 4 18 ± 60 250 98 103 ±13.1 2200 15 150 ±400 UNITS µV µV/°C pA pA V/mV dB dB V ELECTRICAL CHARACTERISTICS For MIL-STD components, please refer to LTC883 data sheet for test listing and parameters. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Offset voltage is measured under two different conditions: (a) approximately 0.5 seconds after application of power; (b) at TA = 25°C only, with the chip heated to approximately 38°C for the LT1055 and to 45°C for the LT1056, to account for chip temperature rise when the device is fully warmed up. Note 3: 10Hz noise voltage density is sample tested on every lot of A grades. Devices 100% tested at 10Hz are available on request. Note 4: This parameter is tested on a sample basis only. Note 5: Current noise is calculated from the formula: in = (2qlB)1/2, where q = 1.6 • 10 –19 coulomb. The noise of source resistors up to 1GΩ swamps the contribution of current noise. Note 6: Offset voltage drift with temperature is practically unchanged when the offset voltage is trimmed to zero with a 100k potentiometer between the balance terminals and the wiper tied to V +. Devices tested to tighter drift specifications are available on request. 10556fc 5 LT1055/LT1056 TYPICAL PERFORMANCE CHARACTERISTICS Input Bias and Offset Currents vs Temperature INPUT BIAS CURRENT, TA = 25°C, TA = 70°C (pA) 1000 INPUT BIAS AND OFFSET CURRENT (pA) 300 VS = ±15V VCM = 0V WARMED UP BIAS OR OFFSET CURRENTS MAY BE POSITIVE OR NEGATIVE BIAS CURRENT 40 0 –40 – 80 100 A A 400 0 –400 TA = 25°C NUMBER OF INPUTS 30 10 OFFSET CURRENT 3 0 25 75 100 50 AMBIENT TEMPERATURE (°C) Distribution of Offset Voltage Drift with Temperature (H Package)* 140 120 CHANGE IN OFFSET VOLTAGE (µV) 80 OFFSET VOLTAGE CHANGE µV) VS = ±15V 634 UNITS TESTED FROM THREE RUNS BATTERY VOLTAGE (V) 100 80 60 40 20 0 –10 –8 –6 –4 –2 0 2 4 6 8 10 OFFSET VOLTAGE DRIFT WITH TEMPERATURE (µV/°C) *DISTRIBUTION IN THE PLASTIC (N8) PACKAGE IS SIGNIFICANTLY WIDER. 0.1Hz to 10Hz Noise 0.1Hz TO 10Hz PEAK-TO-PEAK NOISE (µV/P-P) 10 7 5 NOISE VOLTAGE (1µV/DIVISION) 70 PEAK-TO-PEAK NOISE 50 LT1056 RMS NOISE VOLTAGE DENSITY (nV/√Hz) LT1055 0 2 6 4 TIME (SECONDS) 6 UW LT1055/56 G01 Input Bias Current Over the Common Mode Range 120 80 VS = ±15V WARMED UP TA = 125°C TA = 70°C 1200 INPUT BIAS CURRENT, TA = 125°C (pA) Distribution of Input Offset Voltage (N8 Package) 160 140 800 VS = ±15V TA = 25°C 550 UNITS TESTED FROM 120 TWO RUNS (LT1056) 100 80 60 40 20 50% YIELD TO ±140µV TA = 70°C B B TA = 125°C –800 125 –120 –15 A = POSITIVE INPUT CURRENT B = NEGATIVE INPUT CURRENT 15 –1200 –5 0 5 10 –10 COMMON MODE INPUT VOLTAGE (V) 0 –800 –600 –400 –200 0 200 400 600 800 INPUT OFFSET VOLTAGE (µV) LT1055/56 G03 LT1055/56 G02 Warm-Up Drift 100 VS = ±15V TA = 25°C 50 40 30 20 10 0 –10 –20 –30 –40 –50 Long Term Drift of Representative Units VS = ±15V TA = 25°C 50% TO ±1.5µV/ °C 60 LT1056CN8 40 LT1055CN8 LT1056 H PACKAGE LT1055 H PACKAGE 0 0 1 3 4 2 TIME AFTER POWER ON (MINUTES) 5 20 0 1 3 2 TIME (MONTHS) 4 5 LT1055/56 G05 LT1055/56 GO6 LT1055/56 G04 Noise vs Chip Temperature 100 RMS NOISE VOLTAGE DENSITY (nV/√Hz) 1000 Voltage Noise vs Frequency VS = ±15V TA = 25°C 300 3 f0 = 10kHz 2 f0 = 1kHz 30 20 100 LT1056 1/f CORNER = 28HZ 30 LT1055 1/f CORNER = 20HZ 10 1 3 10 100 30 FREQUENCY (Hz) 300 1000 1 10 20 30 50 60 40 CHIP TEMPERATURE (°C) 70 8 10 10 80 LT1055/56 GO7 LT1055/56 G08 LT1055/56 G09 10556fc LT1055/LT1056 TYPICAL PERFORMANCE CHARACTERISTICS LT1056 Large-Signal Response Small-Signal Response LT1055 Large-Signal Response 5V/DIV AV = 1, CL = 100pF, 0.5µs/DIV LT1055/56 G10 20mV/DIV 5V/DIV Undistorted Output Swing vs Frequency 30 30 PEAK-TO-PEAK OUTPUT SWING (V) VS = ±15V TA = 25°C SLEW RATE (V/µS) 20 LT1055 GBW OUTPUT IMPEDANCE (Ω) 24 18 LT1055 12 LT1056 6 VS = ±15V f0 = 1MHz FOR GBW –25 25 75 TEMPERATURE (˚C) 125 LT1055/56 G14 0 0.1 1 FREQUENCY (MHz) Gain vs Frequency 140 120 100 VS = ±15V TA = 25°C GAIN (dB) GAIN (dB) 80 60 LT1055 40 20 0 –20 LT1056 LT1055 10 GAIN LT1056 VOLTAGE GAIN (V/mV) 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) LT1055/56 G16 UW LT1055/56 G13 AV = 1, CL = 100pF, 0.5µs/DIV LT1055/56 G12 AV = 1, CL = 100pF, 0.2µs/DIV LT1055/56 G11 Slew Rate, Gain Bandwidth vs Temperature 10 GAIN BANDWIDTH PRODUCT (MHz) LT1056 GBW 8 6 4 10 LT1056 SLEW LT1055 SLEW 2 100 Output Impedence vs Frequency VS = ±15V TA = 25°C AV = 100 LT1055 10 LT1055 1 LT1056 AV = 10 LT1056 LT1055 LT1056 AV = 1 0 0.1 1 10 100 FREQUENCY (kHz) 1000 LT1055/56 G15 10 Gain, Phase Shift vs Frequency 100 20 1000 Voltage Gain vs Temperature RL = 2k PHASE SHIFT (DEGREES) VS = ± 15V VO = ± 10V PHASE 120 300 RL = 1k 100 140 LT1055 0 VS = ±15V TA = 25°C –10 1 4 2 FREQUENCY (MHz) 6 8 10 160 LT1056 30 10 –75 25 –25 75 TEMPERATURE (°C) 125 LT1055/56 G18 LT1055/56 G17 10556fc 7 LT1055/LT1056 TYPICAL PERFORMANCE CHARACTERISTICS LT1055 Settling Time 10 OUTPUT VOLTAGE SWING FROM 0V (V) OUTPUT VOLTAGE SWING FROM 0V (V) 2mV 10mV 5 0.5mV 10 10mV 5 2mV BATTERY VOLTAGE (V) 5mV 0 1mV 5mV 2mV –5 10mV 1mV 0.5mV VS = ±15V TA = 25°C –10 0 1 2 3 LT1055/56 G19 SETTLING TIME (µS) Common Mode and Power Supply Rejections vs Temperature 120 VS = ± 10V TO ± 17V FOR PSRR VS = ± 15V, VCM = ± 10.5V FOR CMRR POWER SUPPLY REJECTION RATIO (dB) CMRR, PSRR (dB) 110 PSRR CMRR (dB) CMRR 100 90 –25 25 75 TEMPERATURE (˚C) 125 LT1055/56 G22 Supply Current vs Supply Voltage 8 SHORT-CIRCUIT CURRENT (mA) OUTPUT VOLTAGE SWING (V) SUPPLY CURRENT (mA) 6 LT1056 4 25°C LT1055 2 25°C TA = – 55°C TA = 125°C TA = – 55°C TA = 125°C 0 0 ± 10 ± 15 ±5 SUPPLY VOLTAGE (V) 8 UW LT1055/56 G25 LT1056 Settling Time 15 14 0.5mV Common Mode Range vs Temperature 13 12 11 ± 10 –11 –12 –13 –14 VS = ± 15V –15 50 –50 0 TEMPERATURE (°C) 5mV 0 5mV 1mV VS = ± 15V TA = 25°C ≈ ≈ –5 10mV 2mV 1mV 0.5mV –10 0 1 2 3 LT1055/56 G20 100 LT1055/56 G21 SETTLING TIME (µS) Common Mode Rejection Ratio vs Frequency 120 100 80 60 40 20 0 VS = ±15V TA = 25°C 140 120 100 80 60 40 20 0 Power Supply Rejection Ratio vs Frequency TA = 25°C POSITIVE SUPPLY NEGATIVE SUPPLY 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 10 100 100k 10k 1k FREQUENCY (Hz) 1M 10M LT1055/56 G23 LT1055/56 G24 Output Swing vs Load Resistance 15 12 9 6 3 0 –3 –6 –9 –12 TA = – 55°C 0.3 1 3 LOAD RESISTANCE (kΩ) 10 LT1055/56 G26 Short-Circuit Current vs Time 50 40 TA = – 55°C TA = 25°C TA = 125°C TA = – 55°C TA = – 25°C TA = –125°C VS = ± 15V TA = – 25°C TA = –125°C 30 20 10 0 –10 –20 –30 –40 –50 0 VS = ± 15V SINKING TA = 125°C TA = 25°C TA = – 55°C 2 1 3 TIME FROM OUTPUT SHORT TO GROUND (MINUTES) LT1055/56 G27 ± 20 –15 0.1 10556fc LT1055/LT1056 APPLICATIONS INFORMATION The LT1055/LT1056 may be inserted directly into LF155A/ LT355A, LF156A/LT356A, OP-15 and OP-16 sockets. Offset nulling will be compatible with these devices with the wiper of the potentiometer tied to the positive supply. OUTPUT N/C V+ OFFSET TRIM Offset Nulling V+ 1 RP 2 – + V– 5 7 OUT 3 4 LT1055/56 AI1 V– GUARD IN PU TS LT1055/56 AI2 LT1055 LT1056 6 No appreciable change in offset voltage drift with temperature will occur when the device is nulled with a potentiometer, RP, ranging from 10k to 200k. The LT1055/LT1056 can also be used in LF351, LF411, AD547, AD611, OPA-111, and TL081 sockets, provided that the nulling cicuitry is removed. Because of the LT1055/ LT1056’s low offset voltage, nulling will not be necessary in most applications. Achieving Picoampere/Microvolt Performance In order to realize the picoampere-microvolt level accuracy of the LT1055/LT1056 proper care must be exercised. For example, leakage currents in circuitry external to the op amp can significantly degrade performance. High quality insulation should be used (e.g. Teflon™, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be required. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: in inverting configurations the guard ring should be tied to ground, in noninverting connnections to the inverting input at pin 2. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends on the guard ring width. Teflon is a trademark of Dupont. U W U U 7 6 5 4 8 1 OFFSET TRIM 2 3 The LT1055/LT1056 has the lowest offset voltage of any JFET input op amp available today. However, the offset voltage and its drift with time and temperature are still not as good as on the best bipolar amplifiers because the transconductance of FETs is considerably lower than that of bipolar transistors. Conversely, this lower transconductance is the main cause of the significantly faster speed performance of FET input op amps. Offset voltage also changes somewhat with temperature cycling. The AM grades show a typical 20µV hysteresis (30µV on the M grades) when cycled over the –55°C to 125°C temperature range. Temperature cycling from 0°C to 70°C has a negligible (less than 10µV) hysteresis effect. The offset voltage and drift performance are also affected by packaging. In the plastic N8 package the molding compound is in direct contact with the chip, exerting pressure on the surface. While NPN input transistors are largely unaffected by this pressure, JFET device matching and drift are degraded. Consequently, for best DC performance, as shown in the typical performance distribution plots, the TO-5 H package is recommended. Noise Performance The current noise of the LT1055/LT1056 is practically immeasurable at 1.8fA/√Hz. At 25°C it is negligible up to 1G of source resistance, RS (compound to the noise of RS). Even at 125°C it is negligible to 100M of RS. 10556fc 9 LT1055/LT1056 APPLICATIONS INFORMATION The voltage noise spectrum is characterized by a low 1/f corner in the 20Hz to 30Hz range, significantly lower than on other competitive JFET input op amps. Of particular interest is the fact that with any JFET IC amplifier, the frequency location of the 1/f corner is proportional to the square root of the internal gate leakage currents and, therefore, noise doubles every 20°C. Furthermore, as illustrated in the noise versus chip temperature curves, the 0.1Hz to 10Hz peak-to-peak noise is a strong function of temperature, while wideband noise (f0 = 1kHz) is practically unaffected by temperature. Consequently, for optimum low frequency noise, chip temperature should be minimized. For example, operating an LT1056 at ± 5V supplies or with a 20°C/W case-toambient heat sink reduces 0.1Hz to 10Hz noise from typically 2.5µVP-P (±15V, free-air) to 1.5µVP-P. Similiarly, the noise of an LT1055 will be 1.8µVP-P typically because of its lower power dissipation and chip temperature. High Speed Operation Settling time is measured in the test circuit shown. This test configuration has two features which eliminate problems common to settling time measurments: (1) probe Settling Time Test Circuit 15V 15k 10µF SOLID TANTALUM 10pF (TYPICAL) 0.01 DISC + –15V 15k 0.01 DISC 2k PULSE GEN INPUT (5V MIN STEP) 50Ω 2W 10µF SOLID TANTALUM 15k 0.01 DISC 15V + 10µF 2k –15V 15k 0.01 DISC 10µF SOLID TANTALUM 10 + + SOLID TANTALUM U W + U U capacitance is isolated from the “false summing” node, and (2) it does not require a “flat top” input pulse since the input pulse is merely used to steer current through the diode bridges. For more details, please see Application Note 10. As with most high speed amplifiers, care should be taken with supply decoupling, lead dress and component placement. When the feedback around the op amp is resistive (RF), a pole will be created with RF, the source resistance and capacitance (RS, CS), and the amplifier input capacitance (CIN ≈ 4pF). In low closed-loop gain configurations and with RS and RF in the kilohm range, this pole can create excess phase shift and even oscillation. A small capacitor (CF) in parallel with RF eliminates this problem. With RS (CS + CIN) = RFCF, the effect of the feedback pole is completely removed. CF RF – RS CS CIN OUTPUT + LT1055/56 AI03 10k – LT1055 LT1056 AUT OUTPUT 4.7k 10k 15V + AMPLIFIER UNDER TEST 15V 1/2 U440 50Ω 2N3866 2N160 3Ω –15V 15V OUTPUT TO SCOPE 3Ω 2N3866 2N5160 4.7k –15V LT1055/56 AI04 HP5082-8210 HEWLETT PACKARD 1/2 U440 100Ω DC ZERO = 1N4148 –15V 10556fc LT1055/LT1056 APPLICATIONS INFORMATION Phase Reversal Protection Most industry standard JFET input op amps (e.g., LF155/ LF156, LF351, LF411, OP15/16) exhibit phase reversal at the output when the negitive common mode limit at the input is exceeded (i.e., from –12V to –15V with ±15V supplies). This can cause lock-up in servo systems. As shown below, the LT1055/LT1056 does not have this problem due to unique phase reversal protection circuitry (Q1 on simplified schematic). Input Voltage Follower with Input Exceeding the Negative Common Mode Range 15V 2 INPUT ±15V SINE WAVE Output (LF155/LF56, LF441, OP-15/OP-16) 10V/DIV 10V/DIV 0.5ms/DIV LT1055/56 AI06 0.5ms/DIV LT1055/56 AI07 10V/DIV TYPICAL APPLICATIONS † Exponential Voltage-to-Frequency Converter for Music Synthesizers INPUT 0V TO 10V EXPONENT TRIM 2500Ω* 11.3k* 5 6 3.57k* ZERO TRIM 4 2 500pF POLYSTYRENE 15V 2N3906 500k 4.7k 15V 562Ω* 1.1k 10k* 1k* 1 2 SCALE FACTOR 1V IN OCTAVE OUT *1% METAL FILM RESISTOR PIN NUMBERED TRANSISTORS = CA3096 ARRAY 3 U 3 W U U U – + 7 6 OUTPUT 2k LT1055/56 3 4 –15V LT1055/56 AI05 Output LT1055/LT1056 0.5ms/DIV LT1055/56 AI08 – + 7 LT1055 6 2N3904 500Ω* SAWTOOTH OUTPUT 1k* –15V LM329 10k* 2 4.7k 15V 7 LM301A 3 6 8 1 4 0.01µF –15V TEMPERATURE CONTROL LOOP LT1055/56 TA03 15V 3k 1N148 13 14 15 2.2k 9 8 7 33Ω – + †For ten additional applications utilizing the LT1055 and LT1056, please see the LTC1043 data sheet and Application Note 3. 10556fc 11 LT1055/LT1056 TYPICAL APPLICATIO S 12-Bit Charge Balance A/D Converter 74C00 249k* 0V TO 10V INPUT 33k LM329 10k 15V COUPLE THERMALLY 6 33k 15V 7 4 –15V 2 CIRCUIT OUTPUT fOUT (A) RATIO fCLK (B) Fast “No Trims” 12-Bit Multiplying CMOS DAC Amplifier RFEEDBACK REFERENCE IN TYPICAL 12-BIT CMOS DAC IOUT1 IOUT2 12 U 28k 0.01 14k 0.003µF CLK OUTPUT (B) 10k 6 1N4148 D 10k 1N4148 CLK Q 74C74 Q P CL 2N3904 15V 2 – + 15V 7 LT1055 OUTPUT (A) 3 4 –15V 1N4148 – LT1001 + 3 1N4148 LT1055/56 TA04 Fast, 16-Bit Current Comparator HP5082-2810 DELAY = 250ns * = 1% FILM RESISTOR 15V – LT1055 OUTPUT 15V INPUT 4.7k 50k* 100k* 2 15V – LT1056 7 6 4 3 –15V 2 + LT1055/56 TA05 + LT1011 8 7 1 4 3k OUTPUT 3 LT1009 2.5V + – –15V LT1055/56 TA06 10556fc LT1055/LT1056 TYPICAL APPLICATIO S Temperature-to-Frequency Converter 560 Ω 15V 2N2222 2N2907 LM329 6.2k* 0.01µF POLYSTYRENE 510pF 15V 10k TTL OUTPUT 0kHz TO 1kHz = 0°C TO 100°C 2N2222 15V 2 10k 6 4.7k 1k* 1k* 510 Ω 2V 137Ω* *1% FILM RESISTOR =1N4148 FREQUENCY LINEARITY = 0.1% FREQUENCY STABILITY = 150ppm/°C SETTLING TIME = 1.7µs DISTORTION = 0.25% AT 100kHz, 0.07% AT 10zHz 15V 50k 10Hz DISTORTION TRIM –15V 100kHz DISTORTION TRIM 2k 9.09k* 15V 0V TO 10V INPUT 10k* 2 – LT1056 7 6 2N4391 2N4391 5k* 4 –15V 2N4391 20pF 10k 2.5k* 2 3 + U 2.7k 500Ω 0°C ADJ 2k 100°C ADJ – + 7 LT1055 4 –15V 6.2k* 820 Ω* 3 LM134 *1% FILM RESISTOR LT1055/56 TA07 100kHz Voltage Controlled Oscillator 15V 2 – + 7 6 X1 X2 U1 U2 AD639 COM VR Y1 Y2 5k FREQUENCY TRIM 15V +V CC W Z1 Z2 GT UP –V +15V SINE OUT 2VRMS 0kHs TO 100kHs LT1056 3 22.1k 1k 68k FINE DISTORTION TRIMS 22M POLYSTYRENE 500pF 10k 68k 15pF –15V 15V 7 LT1056 3 6 4 –15V 22k 4.5k 4 –15V –15 – + 10k* 2 10k + LT1011 8 7 1 4 –15V 1k 1k HP50822810 3 – 0.01µF LM329 4.7k –15V 4.7k 15V LT1055/56 TA08 10556fc 13 LT1055/LT1056 TYPICAL APPLICATIO S 12-Bit Voltage Output D/A Converter 12-BIT CURRENT OUTPUT D/A CONVERTER (e.g., 6012,565 OR DAC-80) CF 2 0 TO 2 OR 4mA CF = 15pF TO 33pF SETTLING TIME TO 2mV (0.8 LSB) = 1.5µs TO 2µs SI PLIFIED SCHE ATIC NULL 5 7 V+ 7k NULL 1 J5 –INPUT 2 + INPUT 3 J1 J2 Q12 Q11 Q10 20 Ω 6 OUTPUT J3 J8 Q1 8k 200Ω 14k 14k 9pF Q3 120µA* (160) Q4 120µA* (160) 800µA* (1000) 400µA* (1100) J4 Q2 Q13 Q14 Q5 Q16 J6 300Ω 7.5pF Q9 Q15 J7 7k Q8 Q7 *CURRENTS AS SHOWN FOR LT1055. (X) = CURRENTS FOR LT1056. LT1055/56 SCHM 14 U – + 15V 7 LT1056 6 4 –15V LT1055/56 TA09 3 OUTPUT 0V TO 10V W W 3k 50Ω 4 V– 10556fc LT1055/LT1056 PACKAGE DESCRIPTIO 0.040 (1.016) MAX SEATING PLANE 0.010 – 0.045* (0.254 – 1.143) 0.016 – 0.021** (0.406 – 0.533) 45°TYP 0.028 – 0.034 (0.711 – 0.864) 0.110 – 0.160 (2.794 – 4.064) INSULATING STANDOFF .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) NOTE: 1. DIMENSIONS ARE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U H Package 8-Lead TO-5 Metal Can (.200 Inch PCD) (Reference LTC DWG # 05-08-1320) 0.335 – 0.370 (8.509 – 9.398) DIA 0.305 – 0.335 (7.747 – 8.509) 0.050 (1.270) MAX GAUGE PLANE 0.165 – 0.185 (4.191 – 4.699) REFERENCE PLANE 0.500 – 0.750 (12.700 – 19.050) 0.027 – 0.045 (0.686 – 1.143) PIN 1 0.200 (5.080) TYP *LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND 0.045" BELOW THE REFERENCE PLANE 0.016 – 0.024 **FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS (0.406 – 0.610) H8(TO-5) 0.200 PCD 1197 OBSOLETE PACKAGE N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 .255 ± .015* (6.477 ± 0.381) 1 2 3 4 .130 ± .005 (3.302 ± 0.127) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 (0.457 ± 0.076) N8 1002 ) .100 (2.54) BSC 10556fc 15 LT1055/LT1056 TYPICAL APPLICATIO INPUT PACKAGE DESCRIPTIO .050 BSC 8 .245 MIN .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 0°– 8° TYP NOTE: 1. DIMENSIONS IN INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) RELATED PARTS PART NUMBER LT1122 LT1792 DESCRIPTION Fast Settling JFET Op Amp Low Noise JFET Op Amp COMMENTS 340ns Settling Time, GBW = 14MHz, SR = 60V/µs en = 6nV/√Hz Max at f = 1kHz 10556fc LT 0406 REV C • PRINTED IN USA 16 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● U U ±120V Output Precision Op Amp 125V 1µF 10k ± 25mA OUTPUT HEAT SINK OUTPUT TRANSISTORS 100pF 50k 2 10k 3 1M 2N2222 1N4148 6 4 50k 1M 1N4148 1k 2N2907 2N5415 2N3440 1N965 10k 510Ω 330Ω 27Ω 1k 27Ω OUTPUT 510Ω 330Ω 2N5415 2N3440 1N965 10k – LT1055 7 + 100k 33pF 1µF –125V LT1055/56 TA10 S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .045 ±.005 .189 – .197 (4.801 – 5.004) NOTE 3 7 6 5 .160 ±.005 .228 – .244 (5.791 – 6.197) .150 – .157 (3.810 – 3.988) NOTE 3 1 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .016 – .050 (0.406 – 1.270) .014 – .019 (0.355 – 0.483) TYP .050 (1.270) BSC SO8 0303 www.linear.com © LINEAR TECHNOLOGY CORPORATION 1994