CLC532AJE

CLC532 High Speed 2:1 Analog Multiplexer December 2001 CLC532 High Speed 2:1 Analog Multiplexer General Description The CLC532 is a high speed 2:1 multiplexer with active input and output stages. The CLC532 innovative design employs a closed loop design which dramatically improves accuracy. This monolithic device is constructed using an advanced high performance bipolar process. The CLC532 has been specifically designed to provide settling times of 17ns to 0.01%. Fast settling time, coupled with the adjustable bandwidth, and channel-to-channel isolation is better than 80dB @10MHz. Low distortion (−80dBc) makes the CLC532 an ideal choice for infrared and CCD imaging systems and spurious signal levels make the CLC532 a very suitable choice for both I/Q processors and receivers. The CLC532 is offered in two industrial versions, CLC532AJP\AJE, specified from −40˚C to +85˚C and packaged in 14-pin plastic DIP14-pin and SOIC packages. Enhanced Solutions (Military/Aerospace) SMD Number: 5962-92035 *Space level versions also available. *For more information, visit http://www.national.com/mil n Adjustable bandwidth–190MHz(max) Applications n n n n n Infrared system multiplexing CCD sensor signals Radar I/Q switching High definition video HDTV Test and calibration Settling Time vs. RL Features n n n n 17ns 12-bit settling time to .01% Low noise – 32µVrms High isolation – 80dB @ 10MHz Low distortion – 80dBc @ 5MHz DS012716-24 Typical Application Connection Diagram DS012716-2 DS012716-4 Pinout DIP & SOIC Ordering Information Package 14-Pin Plastic DIP 14-Pin Plastic SOIC Temperature Range Industrial −40˚C to +85˚C −40˚C to +85˚C Part Number CLC532AJP CLC532AJE Package Marking CLC532AJP CLC532AJE NSC Drawing N14E M14A © 2001 National Semiconductor Corporation DS012716 www.national.com CLC532 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (+VCC) Negative Supply Voltage (−VEE) Differential Voltage between any two GND’s Analog Input Voltage Range Digital Input Voltage Range Output Short Circuit Duration (Output Shorted to GND) Operating Temperature Range Storage Temperature Range Lead Solder Duration (+300˚C) ESD Rating −0.5V to +7.0V +0.5V to −7.0V 200mV −VEE to +VCC −VEE to +VCC Infinite −40˚C to +85˚C −65˚C to +150˚C 10 sec < 500V Operating Ratings Positive Supply Voltage (+VCC) Negative Supply Voltage (−VEE) Differential Voltage between any two GDN’s Analog Input Voltage Range SELECT Input Voltage Range (TTL Mode) SELECT Input Voltage Range (ECL Mode) CCOMPRange (Note 3) Thermal Resistance (θJC) MDIP SOIC Thermal Resistance (θJA) MDIP SOIC +5v −5.2V or −5.0V 10mV ± 2V 0.0V to +3.0V −2.0V to 0.0V 5pF to 100pF 55˚C/W 35˚C/W 100˚C/W 105˚C/W Electrical Characteristics (+VCC = +5.0V; −VEE = −5.2V; RIN = 50Ω; RL = 500Ω; CCOMP = 10pF; ECL Mode, pin 6 = NC) Symbol Case Temperature Frequency Domain Response SSBW LSBW Gain Flatness GFP GFR LPD DG DP CT10 CT20 CT30 Time Domain Performance TRS TRL TS14 TSP TSS OS SR SWT10 SWT90 ST HD2 HD3 SNF Overshoot Slew Rate Channel to Channel Switching Time (2V Step at Output) Switching Transient 2nd Harmonic Distortion 3rd Harmonic Distortion Equivalent Input Noise Spot Noise Voltage 2VPP, 5MHz 2VPP, 5MHz 50% SELECT to 10% VOUT 50% SELECT to 90% VOUT Settling Time 2V Step; from 50% VOUT Rise and Fall Time 0.5V Step 2V Step 2.7 10 35 17 13 2 160 5 15 30 80 86 3.1 67 68 67 68 67 68 24 18 5 130 7 20 24 18 5 130 7 20 27 21 6 110 8 23 3.3 12.5 3.3 12.5 3.8 14.5 ns ns ns ns ns % V/µs ns ns mV dBc dBc nV/ Peaking Rolloff Linear Phase Deviation Differential Gain Differential Phase Crosstalk Rejection -3dB Bandwidth VOUT < 0.1VPP VOUT = 2VPP VOUT < 0.1VPP 0.1MHz to 200MHz 0.1MHz to 100MHz DC to 100MHz CCOMP = 5pF; RL = 150Ω CCOMP = 5pF; RL = 150Ω 2VPP, 10MHz 2VPP, 20MHz 2VPP, 30MHz 0.2 1.0 2.0 0.05 0.01 80 74 68 75 69 63 75 69 63 74 68 62 0.7 1.8 0.7 1.8 0.8 2.6 dB dB deg % deg dB dB dB 190 45 140 35 140 35 110 30 MHz MHz Parameter Conditions CLC532AJP/AJE Typ +25˚C Max/Min Ratings (Note 2) −40˚C +25˚C +85˚C Units ± 0.0025% ± 0.01% ± 0.1% 2.0V Step Switch Performance Distortion And Noise Performance > 1MHz www.national.com 2 CLC532 Electrical Characteristics Symbol Parameter (Continued) (+VCC = +5.0V; −VEE = −5.2V; RIN = 50Ω; RL = 500Ω; CCOMP = 10pF; ECL Mode, pin 6 = NC) Conditions Typ Max/Min Ratings (Note 2) 42 42 46 Units Distortion And Noise Performance INV SNC Integrated Noise Spot Noise Current 1MHz to 100MHz 32 3 µVrms pA/ Static And DC Performance VOS DVIO VOSM IBN DIBN IBNM RIN CIN GA GAM ILIN VO IO RO Analog Output Offset Voltage (Note 5) Temperature Coefficient Analog Output Voltage Matching Analog Input Bias Current Temperature Coefficient Analog Input Bias Current Matching (Note 5) Analog Input Resistance Analog Input Capacitance Gain Accuracy (Note 5) Gain Matching Integral Endpoint Non-Linearity Output Voltage Output Current Output Resistance ECL Mode (Pin 6 Floating) VIH1 VIL1 IIH1 IIL1 VIH2 VIL2 IIH2 IIL2 ICC IEE PD PSRR Input Voltage Logic HIGH Input Voltage Logic LOW Input Current Logic HIGH Input Current Logic LOW TTL Mode (pin 6 = +5V) Input Voltage Logic HIGH Input Voltage Logic LOW Input Current Logic HIGH Input Current Logic LOW Supply Current (+VCC = +5.0V) (Note 5) Supply Current (−VEE = −5.2V) (Note 5) Nominal Power Dissipation Power Supply Rejection Ratio (Note 5) No Load No Load No Load 14 50 23 24 240 73 60 64 64 2.0 0.8 50 270 30 31 2.0 0.8 30 110 28 30 2.0 0.8 30 110 25 26 V V µA µA mA mA mW dB 14 50 −1.1 −1.5 50 270 −1.1 −1.5 30 110 −1.1 −1.5 30 110 V V µA µA DC 1 15 TBD 50 0.3 TBD 200 2 90 3.0 0.998 0.05 2.4 20 4.0 120 2.5 0.998 0.03 2.8 30 2.5 120 2.5 0.998 0.03 2.8 30 2.5 250 2.0 120 120 0.8 6.5 90 3.5 5.5 20 mV µV/˚C mV µA µA/˚C µA kΩ pF V/V V/V %FS V mA Ω ± 2V ± 2V ± 1V (Full Scale) No Load 0.998 TBD 0.02 ± 3.4 45 1.5 Digital Input Performance Power Requirements Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: The CLC532 does not require external CCOMP capacitors for proper operation. Note 4: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit maybe impaired. functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Note 5: AJ: 100% tested at +25˚C, sample tested at +85˚C 3 www.national.com CLC532 Typical Performance Characteristics Small Signal/Phase vs. Load (+25˚C unless otherwise specified) Recommended compensation Capacitance vs. Load DS012716-5 DS012716-6 Small Signal Gain/Phase vs. Load with Recommended CCOMP Large Signal Frequency Response vs. Load DS012716-8 DS012716-7 SFRD vs. Input Frequency Output Impedance DS012716-9 DS012716-10 www.national.com 4 CLC532 Typical Performance Characteristics Channel to Channel Crosstalk (+25˚C unless otherwise specified) (Continued) Digitized Pulse Response DS012716-12 DS012716-11 Input Impedance Small Signal Pulse Response DS012716-14 DS012716-13 Large Signal Pulse Response vs. Ccomp Large Signal Pulse Response vs. RL DS012716-15 DS012716-16 5 www.national.com CLC532 Typical Performance Characteristics Settling Time vs Ccomp (+25˚C unless otherwise specified) (Continued) Settling Time vs. RL DS012716-17 DS012716-24 2nd and 3rd Harmonic Distortion 2nd Harmonic Distortion vs. VOUT; RL = 100Ω DS012716-18 DS012716-19 3rd Harmonic Distortion vs. VOUT; RL = 100Ω Reverse Transmission (S12) DS012716-20 DS012716-21 www.national.com 6 CLC532 Typical Performance Characteristics 2nd Harmonic Distortion vs. VOUT; RL = 500Ω (+25˚C unless otherwise specified) (Continued) 3nd Harmonic Distortion vs. VOUT; RL = 500Ω DS012716-22 DS012716-23 Differential Phase vs. Frequency (Negative Sync) Differintial Gain vs. Frequency (Negative Sync) DS012716-25 DS012716-26 2- Tone, 3rd Order Intermodulation Intercept Transient Isolation DS012716-28 DS012716-27 7 www.national.com CLC532 Typical Performance Characteristics Equivalent Input Noise (+25˚C unless otherwise specified) (Continued) Integral Linearity Error DS012716-29 DS012716-30 Switching Transient (Grounded Inputs) Large signal Channel-to-Channel Switching DS012716-31 DS012716-32 Typical DS Error vs. Temperature DS012716-33 www.national.com 8 CLC532 Application Information Digital Interface and Channel SELECT System Timing Diagram SETTLING ERROR WINDOW A SELECT B SWT9 0 SWT1 0 90% OUTPUT 10% CHANNEL A = +1V CHANNEL B = - 1V TRx TSx TRx The CLC532 functions with ECL, TTL and CMOS logic families, DREF controls logic compatibility. In normal operation, DREF is left floating, and the channel SELECT responds to ECL level signals, Figure 2. For TTL or CMOS level SELECT inputs (Figure 3), DREF should be tied to +5V (the CLC532 incorporates an internal 2300Ω series isolation resistor for the DREF input). For TTL or CMOS operation, the channel SELECT requires a resistor input network to prevent saturation of the channel select circuitry. Without this input network, channel SELECT logic levels above 3V will cause internal junction saturation and slow switching speeds. OS ... where TSx i s TS14 or TSP or TSS, and TRx i s TRS ro TSL. DS012716-34 System Transient Timing Diagram A SELECT B ~ 2ns ~ ST OUTPUT Channel A = 0V Channel B = 0V DS012716-35 DS012716-37 Operation The CLC532 is a 2:1 analog multiplexer with high impedance buffered inputs, and a low distortion, output stage. The CLC532 employs a closed-loop design, which dramatically improves distortion performance. The channel SELECT control Figure 1 determines which of the two inputs (INA or INB) is present at the OUTPUT. Beyond the basic multiplexer function, the CLC532 offers compatibility with either TTL or ECL logic families, as well as adjustable bandwidth. +5V +6.8 µ F 0.1 µ F FIGURE 2. ECL Level Channel SELECT Configuration DS012716-38 CHANNEL A 2 INA 1 RIN 13 14 12 CCOMP1 FIGURE 3. TTL/CMOS Level Channel SELECT Configuration VOUT CLC532 CHANNEL B 4 INB 3 DGND 10 6 11 RL 5 7 8 9 DREF RIN CCOMP2 +6.8 µ F CHANNEL SELECT 0.1 µF -5. 2V DS012716-36 Compensation The CLC532 incorporates compensation nodes that allow both its bandwidth and its settling time/slew rate to be adjusted. Bandwidth and settling time/slew adjustments are linked, meaning that lowering the bandwidth also lowers slew rate and lengthens settling time. Proper compensation is necessary to optimize system performance. Time domain applications should generally be optimized for lowest RMS noise at the CLC532 output, while maintaining settling time and slew rate at adequate levels to meet system needs. Frequency Domain applications should generally be optimized for maximally flat frequency response. FIGURE 1. Standard CLC532 Circuit Configuration 9 www.national.com CLC532 Application Information (Continued) Figure 4 below describes the basic relationship between settling time (TS) and RS for various values of load capacitance, CL, where CCOMP = 10pF plane will provide the best performance. In those special cases requiring separate ground planes, the following table indicates the signal and supply ground connections. Pin 1,3 5 Functions Shield/Supply Returns DREF Ground Ground Return Supplies and Inputs DREF Currents only Input Shielding The CLC532 has been designated for use in high speed wide dynamic range systems. Guarding traces and the use of the ground pins separating the analog inputs are recommended to maintain high isolation (Figure 6). Likely sources of noise and interference that may couple onto the inputs, are the logic signals and power supplies to the CLC532. Other types if clock and signal traces should not be overlooked, however. DS012716-39 Channel A Connector FIGURE 4. Settling Time and RS vs. CL Pin 1 Figure 5 shows the resulting changes in bandwidth and slew rate for increasing values of CCOMP. The RMS noise at the CLC532 output can be approximated as: Chip Resistors where.... nV = input spot noise voltage; BW−3dB = Bandwidth is from Figure 5. Channel B Connector DS012716-42 FIGURE 6. Alternate Layout Using Guard Ring The general rule in maintaining isolation has two facets, minimize the primary return ground current path impedances back to the respective signal sources, while maximizing the impedance associated with common or secondary ground current return paths. Success or failure to optimize input signal isolation can be measured directly as the isolation between the input channels with the CLC532 removed from circuit. The channel-to -channel isolation of the CLC532 can never be better than the isolation level present at its inputs. Special attention must be paid to input termination resistors. Minimizing the return current path that is common to both of the input termination resistors is essential. In the event that a ground return current from one input termination resistor is able to find a secondary path back to its signal source (which also happens to be common with either the primary or secondary return path for the second input termination resistor), a small voltage can appear across the second input termination resistor. The small voltage seen across the second input termination resistor will be highly correlated with the signal generating the initial return currents. This situation will severely degrade channel-to-channel isolation at the input of the CLC532, even if the CLC532 were removed from circuit. Poor isolation at the input will be transmitted directly to the output. Use of “small” value input termination resistors will also improve channel-to-channel isolation. However, extremely low values ( < 25Ω) tend to stress the driving source’s ability to provide a high-quality input signal to the CLC532. Higher values tend to aggravate any layout dependent crosstalk. 75Ω to 50Ω is a reasonable target, but the lower the better. DS012716-41 FIGURE 5. CCOMP for Maximally Flat Frequency Response Power Supplies and Grounding Proper power supply bypassing and grounding is essential to the CLC532’s operation. 0.1µF to .1µF ceramic chip capacitor should be located very close to the individual power supply pins. Larger +6.8µF tantalum capacitors should be used within a few inches of the CLC532. The ground connections for these larger by-pass capacitors should be symmetrically located relative the CLC532 output load ground connection. Harmonic distortion can be heavily influenced by non-symmetric decoupling capacitor grounding. The smaller chip capacitors located directly at the power supply pins are not particularly susceptible to this effect. Separation of analog and digital ground planes is not recommended. In most cases, a single low impedance ground www.national.com 10 CLC532 Application Information (Continued) 50 45 40 Combining Two Signals in ADC Applications The CLC532 is applicable in a wide range of circuits and applications. A classic example of this flexibility is combining two or more signals for digitization by an analog-to-digital converter (ADC). A clear understanding of both the multiplexer and the ADC’S operation is needed to optimize this configuration. To obtain the best performance from the combination, the output of the CLC532 must be an accurate representation of the selected input during the ADC conversion cycle. The time at which the ADC saples the input varies with the type is ADC that is being used. Subranging ADCs usually have a Track-and-Hold (T/H) at their input. For a successful combination of the multiplexer and the ADC, the multiplexer timing and the T/H timing must be compatible. When the ADC is given a converter command, the T/H transitions from all caps Track mode to all caps Hold mode. The delay between the converter command and this transition is usually specified as Aperture Delay or as Sampling Time Offset. To maximize the time that the multiplexer output has to settle, and that the T/H has to acquire the signal, the multiplexer should begin its transition from one input to the other immediately after the T/H transition into HOLD mode. Unfortunately it is during the initial portion of the HOLD period that a subranging ADC performs analog processing of the sampled signal. High slew rate transitions on the input during this time may have a detrimental effect on the conversion accuracy. To minimize the effects of high input slew rates, one of two strategies that can employed. Strategy one applies when the sampling rate of the system is below the rated speed of the ADC. For this case, the CLC532 SELECT timing is delayed until after the multiplexer transition takes place, while the A/D has completed one conversion cycle and is waiting for the next convert command. As an example, if a CLC935 (15MSPS) ADC is being used at 10MSPS, the conversion takes place in the first 67ns after the CONVERT command. The next 33ns are spent waiting for the next CONVERT command. This quite period would be an ideal place to switch the multiplexer from one channel to the next. Ccomp (pF) 35 30 25 20 15 10 5 10 11 12 13 14 15 16 17 Sample Rate (MSPS) 18 19 20 DS012716-43 FIGURE 7. Recommend CCOMP vs. ADC Sample Rate Strategy two involves lowering the slew rate at the input of the ADC so that less high frequency to feed through to the hold capacitor during HOLD mode. The CLC532 output signal can be slew limited by increasing its compensation capacitors. This approach also has the advantage of limiting the excess noise passed through the CLC532 to the ADC. Figure 7 shows the recommended CCOMP values as a function of ADC sample rate. Since the optimal values will change from one ADC type to the next, this graph should be used as a starting point for CCOMP selection. Both CCOMP capacitors should be the same value to maintain output symmetry. Flash ADCs are similar to subranging ADCs in that the sampling period is very brief. The primary difference is that the acquisition time of a flash converter is much shorter than that of a subranging ADC. It is only during this period that a flash converter is susceptible to interference from a rapidly changing analog input signal. With a flash ADC, the transition of the CLC532 output should be after the sampling instant (”See timing diagram for ADC Aperture Delay” after the CONVERT command). Gain selection for an ADC In many applications, such as RADAR, the dynamic range requirements may exceed the accuracy requirements. Since wide dynamic range ADC are also typically high accuracy ADCs, this often leads the designer into wrongly selecting an ADC which is a technical overkill and a budget buster. By using the CLC532 as a selectable-gain stage, a less expensive ADC can be used. As an example, if an application calls for 80dB of dynamic Range and 0.05% accuracy, rather than using a 14-bit converter, a 12-bit converter combined with the circuit in Figure 8 will meet the same objective. The CLC532 is used to select between the analog input signal and a version of the input signal attenuated by 12dB. The circuit affords 14-bit dynamic range, 12-bit accuracy and 12-bit ease of implementation. 11 www.national.com CLC532 Application Information (Continued) +5V +6.8µ F 0.1µF To 0Ω Input Source 50 Ω R7 2 INA 1 13 14 12 10pF 200 Ω R6 CLC532 4 IN 3B 10 6 11 48.7 Ω R OUT To 50 Ω Load 66.6 Ω R INB To 50 Ω Source 5 7 8 9 DREF 10pF DGND Gain SELECT +6.8 µ F 0.1µF 50 Ω -5.2V DS012716-44 FIGURE 8. Selectable Gain Stage Improves ADC Dynamic Range Full Wave Rectifier Circuit The use of a diode rectifierintroduces significant distortion for signals that are small compared to the diode forward bias voltage. Therefore, when low distortion performance is needed, standard diode based circuits do not work well. The CLC532 can be configured to provide a very low distortion full wave rectifier. The circuit inFigure 9 is used to select between an analog input signal and an inverted version of the input signal. The resulting output exhibits very little distortion for small scale signals up to several hundred kilohertz. +1 RECTIFIER INPUT INA CLC532 -1 INB VOUT RL +20 50Ω 0.1µF 101 14 VBB 50Ω 50Ω 50Ω -2V Zero Crossing Tr eshold Detector DS012716-45 FIGURE 9. Low Distortion Full Wave Rectifier Use of the CLC532 as a Mixer A double balanced diode bridge mixer, as shown in Figure 10, operates by multiplying the RFsignal input by the LO input signal . This is done by using the LO signal phase to select either the forward or reverse path through the diode bridge. The result is an output where IF=RF when LO > 0 and IF=−RF for LO < 0. The same function can be obtained withthe CLC532 circuit shown in Figure 11. The CLC532 based circuit uses a digital LO making system design easier in those cases where the LO is digitally derived. Another advantage of the CLC532 based approach is excellent isolation between all three ports. (See the RF design awards article by Thomas Hack in January 1993 of RF Design.) www.national.com 12 CLC532 Application Information (Continued) DS012716-46 FIGURE 10. Typical Double-Balanced Mixer DS012716-47 FIGURE 11. High-Isolation Mixer Implementation Evaluation Board An evaluation board (part number 730028) for CLC532 is available. This board can be used for fast, trouble-free, evaluation and characterization of the CLC532. Additionally, this board serves as a template for layout and fabrication information. 13 www.national.com CLC532 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number M14A NS Package Number N14A www.national.com 14 CLC532 High Speed 2:1 Analog Multiplexer Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.