LMK02002ISQ

LMK02002 Precision Clock Conditioner with Integrated PLL PRELIMINARY August 2007 LMK02002 Precision Clock Conditioner with Integrated PLL General Description The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family. Features ■ 20 fs additive jitter ■ Integrated Integer-N PLL with outstanding normalized ■ ■ ■ ■ ■ ■ phase noise contribution of -224 dBc/Hz Clock output frequency range of 1 to 800 MHz 4 LVPECL clock outputs Dedicated divider and delay blocks on each clock output Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Target Applications ■ ■ ■ ■ ■ ■ Data Converter Clocking Networking, SONET/SDH, DSLAM Wireless Infrastructure Medical Test and Measurement Military / Aerospace Functional Block Diagram 30023301 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300233 www.national.com LMK02002 Connection Diagram 48-Pin LLP Package 30023302 Pin Descriptions Pin # 1, 25 2, 7, 14, 15, 17, 18, 20, 21, 23, 24 Pin Name GND NC I/O I I I I O I I O I I O O O O Ground No Connection to these pins Power Supply MICROWIRE Clock Input MICROWIRE Data Input MICROWIRE Latch Enable Input LDO Bypass Global Output Enable Lock Detect and Test Output Global Clock Output Synchronization Oscillator Clock Input; Must be AC coupled Charge Pump Output Frequency Input; Must be AC coupled Bias Bypass LVPECL Clock Output 0 LVPECL Clock Output 1 LVPECL Clock Output 2 LVPECL Clock Output 3 Die Attach Pad is Ground Description 3, 8, 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, 30, 31, 33, 37, 40, 43, 46 Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, Vcc13, Vcc14 4 5 6 9, 10 11 12 27 28, 29 32 34, 35 36 38, 39 41, 42 44, 45 47, 48 DAP CLKuWire DATAuWire LEuWire LDObyp1, LDObyp2 GOE LD SYNC* OSCin, OSCin* CPout Fin, Fin* Bias CLKout0, CLKout0* CLKout1, CLKout1* CLKout2, CLKout2* CLKout3, CLKout3* DAP www.national.com 2 LMK02002 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Symbol VCC VIN TSTG TL TJ Ratings -0.3 to 3.6 -0.3 to (VCC + 0.3) -65 to 150 +260 125 Units V V °C °C °C Recommended Operating Conditions Parameter Ambient Temperature Power Supply Voltage Symbol TA VCC Min -40 3.15 Typ 25 3.3 Max 85 3.45 Units °C V Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2 kV, a MM-ESD of > 200 V, and a CDM-ESD of > 1.2 kV. Package Thermal Resistance Package 48-Lead LLP (Note 3) θJA 27.4° C/W θJ-PAD (Thermal Pad) 5.8° C/W Note 3: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout. Electrical Characteristics (Note 4) (3.15 V ≤ Vcc ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C, Differential Inputs/Outputs; except as specified. Typical values represent most likely parametric norms at Vcc = 3.3 V, TA = 25 °C, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed). Symbol Parameter Conditions Current Consumption Power Supply Current (Note 5) Power Down Current Reference Oscillator Input Frequency Range for Square Wave Square Wave Input Voltage for OSCin and OSCin* Frequency Input Frequency Range Frequency Input Slew Rate Frequency Input Duty Cycle Input Power Range for Fin or Fin* AC coupled (Notes 6, 10) Entire device; CLKout0 & CLKout3 enabled in Bypass Mode Entire device; All Outputs Off (no emitter resistors placed) POWERDOWN = 1 Reference Oscillator fOSCin square VOSCinsquare 1 AC coupled; Differential (VOD) 0.2 Frequency Input fFin SLEWFin DUTYFin PFin 1 0.5 40 -13 60 8 800 MHz V/ns % dBm 1.6 Vpp 200 MHz 159 mA 70 1 mA Min Typ Max Units ICC ICCPD 3 www.national.com LMK02002 Symbol fCOMP Parameter PLL Phase Detector Frequency Conditions Min Typ Max 40 Units MHz VCPout = Vcc/2, PLL_CP_GAIN = 1x ISRCECPout Charge Pump Source Current VCPout = Vcc/2, PLL_CP_GAIN = 4x VCPout = Vcc/2, PLL_CP_GAIN = 16x VCPout = Vcc/2, PLL_CP_GAIN = 32x VCPout = Vcc/2, PLL_CP_GAIN = 1x ISINKCPout Charge Pump Sink Current VCPout = Vcc/2, PLL_CP_GAIN = 4x VCPout = Vcc/2, PLL_CP_GAIN = 16x VCPout = Vcc/2, PLL_CP_GAIN = 32x ICPoutTRI ICPout%MIS Charge Pump TRI-STATE® Current Magnitude of Charge Pump Sink vs. Source Current Mismatch 0.5 V < VCPout < Vcc - 0.5 V VCPout = Vcc / 2 TA = 25°C 0.5 V < VCPout < Vcc - 0.5 V TA = 25°C 100 400 1600 3200 -100 -400 -1600 -3200 2 3 10 nA % μA µA Magnitude of Charge Pump ICPoutVTUNE Current vs. Charge Pump Voltage Variation ICPoutTEMP PN10kHz PN1Hz Magnitude of Charge Pump Current vs. Temperature Variation PLL 1/f Noise at 10 kHz Offset (Note 7) Normalized to 1 GHz Output Frequency Normalized Phase Noise Contribution (Note 8) 4 % 4 PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x CLKoutX_MUX = Bypass CLKoutX_MUX = Divided CLKoutX_DIV = 4 -30 -117 -122 -219 -224 % dBc/Hz dBc/Hz Clock Distribution Section (Note 9) - LVPECL Clock Outputs (CLKout0 to CLKout3) RL = 100 Ω Distribution Path = 800 MHz Bandwidth = 12 kHz to 20 MHz 20 fs 75 JitterADD Additive RMS Jitter (Note 9) tSKEW VOH VOL VOD VIH VIL IIH IIL VOH VOL CLKoutX to CLKoutY (Note 10) Equal loading and identical clock configuration Termination = 50 Ω to Vcc - 2 V ±3 Vcc 0.98 Vcc 1.8 30 ps Output High Voltage Output Low Voltage Differential Output Voltage Digital LVTTL Interfaces (Note 11) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage VIH = Vcc VIL = 0 IOH = +500 µA IOL = -500 µA -5.0 -40.0 Vcc 0.4 2.0 Termination = 50 Ω to Vcc - 2 V CLKoutX output frequency = 200 MHz 660 V V 965 Vcc 0.8 5.0 5.0 mV V V µA µA V 0.4 V 810 www.national.com 4 LMK02002 Symbol VIH VIL IIH IIL tCS tCH tCWH tCWL tES tCES tEWH Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable to Clock Set Up Time Enable Pulse Width High VIH = Vcc VIL = 0 Conditions Digital MICROWIRE Interfaces (Note 12) Min 1.6 -5.0 -5.0 25 8 25 25 25 25 25 Typ Max Vcc 0.4 5.0 5.0 Units V V µA µA ns ns ns ns ns ns ns MICROWIRE Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing Note 4: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 5: See 3.4 for more current consumption / power dissipation calculation information. Note 6: For all frequencies the slew rate, SLEWFin, is measured between 20% and 80%. Note 7: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high phase detector frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker (f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). Note 8: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as PN1Hz = LPLL_flat(f) – 20log(N) – 10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. LPLL_flat(f) can be masked by the reference oscillator performance if a low power or noisy source is used. Note 9: The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution section only. Note 10: Specification is guaranteed by characterization and is not tested in production. Note 11: Applies to GOE, LD, and SYNC*. Note 12: Applies to CLKuWire, DATAuWire, and LEuWire. Serial Data Timing Diagram 30023303 Data bits set on the DATAuWire signal are clocked into a shift register, MSB first, on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. 5 www.national.com LMK02002 Charge Pump Current Specification Definitions 30023331 I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = Vcc - ΔV I5 = Charge Pump Source Current at VCPout = Vcc/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage 30023332 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch 30023333 Charge Pump Output Current Magnitude Variation vs. Temperature 30023334 www.national.com 6 LMK02002 1.0 Functional Description The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family. 1.1 BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. 1.2 LDO BYPASS To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor. 1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) The purpose of OSCin is to provide the PLL with a reference signal. The OSCin port must be AC coupled, refer to the System Level Diagram in the Application Information section. The OSCin port may be driven single endedly by AC grounding OSCin* with a 0.1 µF capacitor. 1.4 FREQUENCY INPUT PORT (Fin, Fin*) The purpose of Fin is to provide the PLL with a feedback signal from an external oscillator. The Fin port may be driven single endedly by AC grounding Fin*. 1.5 CLKout DELAYS Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay. 1.6 LVPECL OUTPUTS Each LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0. 1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* pin synchronizes the clock outputs. When the SYNC* pin is held in a logic low state, the divided outputs are also held in a logic low state. When the SYNC* pin goes high, the divided clock outputs are activated and will transition to a high state simultaneously. Clocks in the bypassed state are not affected by SYNC* and are always synchronized with the divided outputs. The SYNC* pin must be held low for greater than one clock cycle of the Frequency Input port, also known as the distribution path. Once this low event has been registered, the outputs will not reflect the low state for four more cycles. Similarly once the SYNC* pin becomes high, the outputs will not simultaneously transition high until four more distribution path clock cycles have passed. See the timing diagram below for further detail. In the timing diagram below the clocks are programmed as CLKout0_MUX = Bypassed, CLKout1_MUX = Divided, CLKout1_DIV = 2, CLKout2_MUX = Divided, and CLKout2_DIV = 4. SYNC* Timing Diagram 30023304 The SYNC* pin provides an internal pull-up resistor as shown on the functional block diagram. If the SYNC* pin is not terminated externally the clock outputs will operate normally. If the SYNC* function is not used, clock output synchronization is not guaranteed. 1.8 CLKout OUTPUT STATES Each clock output may be individually enabled with the CLKoutX_EN bits. Each individual output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Global is set to 0. CLKoutX _EN bit 1 Don't care 0 1 EN_CLKout _Global bit 1 0 Don't care 1 GOE pin Low Don't care Don't care High / No Connect Clock X Output State Low Off Off Enabled When an LVPECL output is in the Off state, the outputs are at a voltage of approximately 1 volt. 1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT The GOE pin provides an internal pull-up resistor. If it is not terminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN) and the EN_CLKout_Global bit. By programming the PLL_MUX register to Digital Lock Detect Active High (See 2.5.2), the Lock Detect (LD) pin can be connected to the GOE pin in which case all outputs are set low automatically if the synthesizer is not locked. 1.10 POWER ON RESET When supply voltage to the device increases monotonically from ground to Vcc, the power on reset circuit sets all registers to their default values, see 2.3.1 for more information on default register values. Voltage should be applied to all Vcc pins simultaneously. 7 www.national.com LMK02002 2.0 General Programming Information The LMK02002 device is programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. During programming, LEuWire is low and serial data is clocked in on the rising edge of clock (MSB first). When LEuWire goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7, R11, R14, and R15 need to be programmed for proper device operation. It is required to program register R14. 2.1 RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to ensure the device is in a default state. It is not necessary to program R0 again. Registers are programmed in order with R15 being the last register programmed. An example programming sequence is shown below. • Program R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. • Program R4 to R7 as necessary with desired clocks with appropriate enable, mux, divider, and delay settings. • Program R11 with DIV4 setting if necessary. • Program R14 with global clock output bit, power down setting, PLL mux setting, and PLL R divider. It is required to program register R14. — R14 must be programmed in accordance with the register map as shown in the register map (see 2.2). • Program R15 with PLL charge pump gain, and PLL N divider. www.national.com 8 2.2 LMK02002 REGISTER MAP 25 Data [27:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 A2 A1 0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A0 0 R4 RESET R0 Register 31 30 29 28 27 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout0 _MUX [1:0] CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 1 0 0 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout1 _MUX [1:0] CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 1 0 1 R6 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout2 _MUX [1:0] CLKout2_DIV [7:0] CLKout2_DLY [3:0] 0 1 1 0 TRI-STATE R15 PLL_ CP_ GAIN [1:0] 0 0 EN_CLKout_Global 0 POWERDOWN 0 PLL_CP_POL R14 0 0 1 0 DIV4 R11 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout3_EN CLKout2_EN CLKout1_EN CLKout0_EN LMK02002 9 R7 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout3 _MUX [1:0] 0 0 0 0 CLKout3_DIV [7:0] CLKout3_DLY [3:0] 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 PLL_MUX [3:0] PLL_R [11:0] 0 0 0 0 1 1 1 0 PLL_N [17:0] 0 0 0 0 1 1 1 1 www.national.com LMK02002 2.3 REGISTER R4 to R7 Registers R4 through R7 control the eight clock outputs. Register R4 controls CLKout0, Register R5 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 3. 2.3.1 RESET bit -- R0 only This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and RESET = 0. Def aul t Bit Val ue 0 Bit Re Lo gis cati ter on R0 31 blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed below. CLKoutX_MUX [1:0] 0 1 Mode Added Delay Relative to Bypass Mode 0 ps 100 ps 400 ps (In addition to the programmed delay) 500 ps (In addition to the programmed delay) Bypassed (default) Divided 2 Delayed 3 Bit Description Divided and Delayed Bit Name Bit State RESET No reset, normal operation Bypassed Disabled Divide by 2 0 ps PDF ≤ 20 MHz Normal CLKouts normal Normal Device active Normal - PLL active Negative Polarity CP Disabled Reset to power on defaults CLKoutX mux mode CLKoutX enable CLKoutX clock divide CLKoutX clock delay Phase Detector Frequency Global clock output enable Device power down TRI-STATE PLL charge pump Polarity of charge pump Multiplexer control for LD pin CLKoutX_ MUX CLKoutX_E N CLKoutX_ DIV CLKoutX_ DLY DIV4 0 0 1 0 0 18: 17 16 R4 to 15: R7 8 7:4 2.3.3 CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.3.2) bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are aligned (See 1.7). The Clock Output Dividers follow the VCO Divider so the final clock divide for an output is VCO Divider × Clock Output Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. The actual Clock Output Divide value is twice the binary value programmed as listed in the table below. CLKoutX_DIV[7:0] 0 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 1 1 . 1 0 0 1 1 0 0 . 1 0 1 0 1 0 1 . 1 Clock Output Divider value Invalid 2 (default) 4 6 8 10 ... 510 R1 1 15 0 0 0 0 0 . 1 EN_CLKou t_Global POWERD OWN PLL_CP_T RI PLL_CP_P OL PLL_MUX 1 27 0 0 26 25 R1 4 0 0 24 23: 20 19: 8 2.3.4 CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output. In order for these delays to be active, the respective CLKoutX_MUX (See 2.3.2) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurred in addition to the delay shown in the table below. CLKoutX_DLY[3:0] 0 1 2 3 4 5 6 7 8 10 Delay (ps) 0 (default) 150 300 450 600 750 900 1050 1200 PLL_R PLL_CP_G AIN PLL_N 10 R divider = 10 PLL R divide value 0 100 uA Charge pump current PLL N divide value 760 N divider = 760 31: R1 30 5 25: 8 2.3.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes changes the www.national.com LMK02002 CLKoutX_DLY[3:0] 9 10 11 12 13 14 15 Delay (ps) 1350 1500 1650 1800 1950 2100 2250 PLL_MUX[3:0] 0 1 2 3 4 5 Output Type Hi-Z Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Open Drain NMOS Open Drain PMOS LD Pin Function Disabled (default) Logic High Logic Low Digital Lock Detect (Active High) Digital Lock Detect (Active Low) Analog Lock Detect Analog Lock Detect Analog Lock Detect N Divider Output/2 (50% Duty Cycle) Invalid R Divider Output/2 (50% Duty Cycle) Invalid 2.3.5 CLKoutX_EN bit -- Clock Output Enables These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See 2.5.4) is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. See 1.8 for more information on CLKout states. CLKoutX_EN bit 0 1 Conditions CLKoutX State EN_CLKout_Global Disabled (default) bit = 1 GOE pin = High / No Enabled Connect 1 6 7 8 9 10 11 12 to 15 Invalid Push-Pull Push-Pull 2.4 REGISTER R11 This register only has one bit and only needs to be programmed in the case that the phase detector frequency is greater than 20 MHz and digital lock detect is used. Otherwise, it is automatically defaulted to the correct values. 2.4.1 DIV4 This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable output from the digital lock detect output in the case of a phase detector frequency greater than 20 MHz. DIV4 0 1 Digital Lock Detect Circuitry Mode Not divided; Phase detector frequency 2.5.3 POWERDOWN bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire device and all blocks, regardless of the state of any of the other bits or pins. POWERDOWN bit 0 1 Mode Normal Operation (default) Entire Device Powered Down ≤ 20 MHz (default) Divided by 4; Phase detector frequency > 20 MHz 2.5.4 EN_CLKout_Global bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits (See 2.3.5). When this bit is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. See 1.8 for more information on CLKout states. EN_CLKout_Global bit 0 1 Clock Outputs All Off Normal Operation (default) 2.5 REGISTER R14 The LMK02002 requires register R14 to be programmed as shown in the register map (see 2.2). 2.5.1 PLL_R[11:0] -- R Divider Value These bits program the PLL R Divider and are programmed in binary fashion. PLL_R[11:0] 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 0 . 1 0 0 0 . 1 . 1 0 0 0 . 0 . 1 0 0 1 . 1 . 1 0 1 0 . 0 . 1 PLL R Divide Value Invalid 1 2 ... 10 (default) ... 4095 2.5.5 PLL_CP_TRI bit -- PLL Charge Pump TRI-STATE This bit sets the PLL charge pump TRI-STATE. PLL_CP_TRI 0 1 PLL Charge Pump Normal operation (default) TRI-STATE 2.5.6 PLL_CP_POL bit -- PLL Charge Pump Polarity This bit sets the polarity of the charge pump to either negative or positive. A negative charge pump is used with a VCO or VCXO which decreases frequency with increasing tuning voltage. A positive charge pump is used with a VCO or VCXO which increases frequency with increasing tuning voltage. PLL_CP_POL 0 1 PLL Charge Pump Polarity Negative (default) Positive 2.5.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes. 11 www.national.com LMK02002 2.6 Register R15 2.6.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL phase detector. Since the VCO Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value, N Total, is also influenced by the VCO Divider value. NTotal = PLL N Divider × VCO Divider. The VCO frequency is calculated as, fVCO = fOSCin × PLL N Divider × VCO Divider / PLL R Divider. Since the PLL N divider is a pure binary counter, there are no illegal divide values for PLL_N [17:0] except for 0. PLL_N[17:0] PLL N Divider Value Invalid 1 ... 760 (default) ... 262143 2.6.2 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain These bits set the charge pump gain of the PLL. PLL_CP_GAIN[1:0] 0 1 2 3 Charge Pump Gain 1x (default) 4x 16x 32x 000000000000000000 000000000000000001 .................. 000000001011111000 .................. 111111111111111111 www.national.com 12 LMK02002 3.0 Application Information 3.1 SYSTEM LEVEL DIAGRAM The following shows the LMK02002 in a typical application. In this setup the clock may be multiplied, reconditioned, and redistributed. 30023370 FIGURE 1. Typical Application 3.2 BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. 3.3 LDO BYPASS To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor. 13 www.national.com LMK02002 3.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to Table 3.4 - Block Current Consumption calculate estimated current consumption of the LMK02002. Unless otherwise noted Vcc = 3.3 V, TA = 25 °C. Block Condition Current Consumption at 3.3 V (mA) 70 9 40 17.4 0 5.3 8.5 5.8 9.9 159 Power Dissipated in device (mW) 231 29.7 72 38.3 0 17.5 28.0 19.1 32.7 404.7 Power Dissipated in LVPECL emitter resistors (mW) 60 19.1 120 Entire device, core current Clock buffers (internal) All outputs off; No LVPECL emitter resistors connected The low clock buffer is enabled anytime one of CLKout0 through CLKout3 are enabled LVPECL output, bypass mode (includes 120 Ω emitter resistors) Output buffers LVPECL output, disabled mode (includes 120 Ω emitter resistors) LVPECL output, disabled mode. No emitter resistors placed; open outputs Divide circuitry per output Delay circuitry per output Entire device Divide enabled, divide = 2 Divide enabled, divide > 2 Delay enabled, delay < 8 Delay enabled, delay > 7 CLKout0 & CLKout3 enabled in bypass mode From Table 3.4 the current consumption can be calculated in any configuration. For example, the current for the entire device with two LVPECL (CLKout0 and CLKout3) outputs in bypass mode can be calculated by adding up the following blocks: core current, clock buffers, and two LVPECL output buffer currents. There will also be two LVPECL outputs drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switched in, then the additional current for these stages needs to be added as well. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of two LVPECL (CLKout0 and CLKout3) operating at 3.3 volts, we calculate 3.3 V × (70 + 9 + 40 + 40) mA = 3.3 V × 159 mA = 524.7 mW. Because the LVPECL outputs have emitter resistors hooked up and the power dissipated by these resistors is 60 mW for each clock, the total device power dissipation is 524.7 mW - 120 mW = 404.7 mW. When an LVPECL output is active, ~1.9 V is the average voltage on each output as calculated from the LVPECL VOH & VOL typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.9 V)2 / 120 Ω = 30 mW. When an LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW. 3.5 THERMAL MANAGEMENT Power consumption of the LMK02002 can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to the printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 2. More information on soldering LLP packages can be obtained at www.national.com. www.national.com 14 LMK02002 30023373 FIGURE 2. To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 2 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated. 15 www.national.com LMK02002 Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Order Number LMK02002ISQ LMK02002ISQX Package Marking K02002 I K02002 I Packing 250 Unit Tape and Reel 2500 Unit Tape and Reel LVPECL Outputs 4 4 www.national.com 16 LMK02002 Notes 17 www.national.com LMK02002 Precision Clock Conditioner with Integrated PLL Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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