LP5551SQX

LP5551 PowerWise™ Technology Compliant Energy Management Unit December 2006 LP5551 PowerWise™ Technology Compliant Energy Management Unit General Description The LP5551 is a PWI 1.0 compliant Energy Management System for reducing power consumption of stand-alone mobile phone processors such as base-band or applications processors. The LP5551 contains two advanced, digitally controlled switching regulators for supplying variable voltage to processor core and memory. Two regulators provide P- and N- well biasing for threshold scaling applications. The device also integrates 4 programmable LDO-regulators for powering I/O, PLLs and maintaining memory retention in shutdown-mode. The device is controlled via the PWI open-standard interface. The LP5551 operates cooperatively with PowerWise™ technology compatible processors to optimize supply voltages adaptively over process and temperature variations or dynamically using frequency/voltage pre-characterized look-up tables and provides P- and N-well biasing for threshold scaling. Features ■ 2 300 mA buck regulators operate 180 degrees out of phase for reduced EMI ■ 1 MHz PWM switching frequency ■ 4 programmable LDOs ideal for I/O (two of these), PLL, and memory retention supply generation. Adaptive Voltage Scaling ■ Supports high-efficiency PowerWise Technology ■ PWI open standard interface for system power ■ ■ ■ ■ ■ management Digitally controlled intelligent voltage scaling Auto or PWI controlled PFM mode transition Internal soft start/startup sequencing. Adjustable P- and N- well bias supply for threshold scaling Power OK output. Applications ■ ■ ■ ■ ■ ■ Dual core processors GSM/GPRS/EDGE & UMTS cellular handsets Hand-held radios PDAs Battery powered devices Portable instruments System Diagram 20172163 FIGURE 1. System Diagram © 2007 National Semiconductor Corporation 201721 www.national.com LP5551 Connection Diagrams and Package Mark Information 36 - Pin LLP NS Package Number SQA36A 20172102 FIGURE 2. LP5551 Pinout Package Mark 20172146 Note: The actual physical placement of the package marking will vary from part to part. FIGURE 3. Top View www.national.com 2 LP5551 Typical Application 20172130 FIGURE 4. Typical Application Circuit Pin Descriptions Pin # 0 1 2 3 4 5 Name DAP GP3 GP2 GP1 GP0 PWROK I/O G O O O O O Type G D D D D D Description Connect Die Attach Pad to ground General purpose output pin General purpose output pin General purpose output pin General purpose output pin Power OK, active high output signal 3 www.national.com LP5551 Pin # 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name RESETN EN SPWI SCLK LDO2 LDO4 LDO1 NC LDO3 NC FB1 PGND1 PGND1 PGND1 SW1 PVDD1 VDD_D VDD_A NC PVDD2 SW2 PGND2 PGND2 PGND2 FB2 NC SCAN VPWELL NC VNWELL NC I/O I I I/O I P P P P P G G G P P P P P P G G G P Type D D D D P P P P P G G G P P P P P P G G G P Description Reset, active low Enable, active high PowerWise Interface (PWI) bi-directional data PowerWise Interface (PWI) clock input LDO2 output, for supplying the I/O voltage on the SoC LDO4 output, for supplying a fixed voltage to a PLL etc. on the SoC LDO1 output, user defined LDO3 output, on-chip memory supply voltage AVS switcher feedback Power ground for the AVS switcher Power ground for the AVS switcher Power ground for the AVS switcher AVS Switcher switch node; connected to inductor Battery supply voltage for the AVS switcher Battery supply voltage for digital Battery supply voltage for analog Battery supply voltage for the DVS switcher DVS Switcher switch node; connected to inductor Power ground for the DVS switcher Power ground for the DVS switcher Power ground for the DVS switcher DVS switcher feedback P P P P P-well bias voltage N-well bias voltage A: Analog Pin D: Digital Pin I: Input Pin O: Output Pin I/O: Input/Output Pin P: Power Pin G: Ground Pin Ordering Information Voltage Option Order Number LP5551SQ LP5551SQX *Released. Samples available. Package Marking LP5551SQ LP5551SQ Supplied As 1000 units, Tape-and-Reel 4500 units, Tape-and-Reel www.national.com 4 LP5551 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VDD_A, VDD_D, PVDD1, and -0.3 to + 6.0V PVDD2 LDO1, LDO2, LDO3, LDO4, -0.3 to VDD_A + 0.3V VNWELL to GND, VPwell, ENABLE, RESETN, FB1, FB2, SW_AVS, SW_DVS,GP0, GP1, GP2, and GP3 SPWI, SCLK, PWROK -0.3 to VDD_D + 0.3V GND, PGND1, PGND2, to GND ±0.3V SLUG Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Continuous Power Dissipation (PD-MAX) (Note 5) 150°C -65°C to 150°C TBD W Maximum Lead Temperature (Soldering) ESD Rating (Note 3) Human Body Model: All pins (Note 4) 2.0kV (Notes 1, 2) 2.7 V to 5.5 V −40°C to +125°C −40°C to +85°C Operating Ratings VDD_A, VDD_D, PVDD1, and PVDD2 Junction Temperature (TJ) Range Ambient Temperature (TA) Range(Note 5) Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) (Note 6) 39.8°C/W General Electrical Characteristics Symbol IQ Parameter Shutdown Supply current Unless otherwise noted, VDD_A, _D , VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Conditions VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off. -40°C ≤ TJ ≤ 125°C VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off. -40°C ≤ TJ ≤ 85°C Sleep State Supply Current VDD_A, _D ,VPVDD1,2= 3.6 V, LDO3 on, LDO2 on (no load). All other circuits off. VDD_A, _D, VPVDD1,2 = 3.6 V, all outputs on, no load 135 186 µA 1 12 µA Min Typ 0.44 Max 4 Units µA Acitve State Supply Current UVLO high UVLO low TSD Under Voltage Lockout, high threshold Under Voltage Lockout, low threshold Thermal Shutdown Threshold Thermal Shutdown Hysteresis 431 742 2.7 µA 2.5 160 10 °C LDO1 (PLL/Fixed Voltage) Characteristics Symbol VOUT Accuracy VOUT Range IOUT IQ Parameter Output Voltage Conditions IOUT = 50 mA, Unless otherwise noted, VDD_A, _D, VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Min -3.5% Typ 1.2 Max 3.1% Units V VOUT = 1.2 V, 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage Programming Resolution=100 mV Range Rated Output Current Output Current Limit Quiescent Current 2.7 V ≤ VDD_A, _D ,PVDD1,2≤ 5.5 V VOUT = 0 V IOUT = 0 mA(Note 11) 0.7 0 1.2 2.2 100 347 V mA 35 µA 5 www.national.com LP5551 Symbol ΔVOUT Parameter Line Regulation Load Regulation Conditions 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V, VDD_A, _D, VPVDD1,2 = 3.6 V, 1 mA ≤ IOUT ≤ 100 mA 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, TRISE,FALL = 10 µs VDD_A, _D, VPVDD1,2= 3.6 V, 10 mA ≤ IOUT ≤ 90 mA, TRISE,FALL = 100 ns IOUT = 50 mA Min -0.083 -0.013 Typ Max 0.316 0.013 Units %/V %/mA Line Transient Regulation Load Transient Regulation 27 86 mV mV eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, 0.103 56 36 1 5 54 2.2 20 500 COUT = 2.2 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 2.2 µF f = 10 kHz, COUT = 2.2 µF Output Capacitance Output Capacitor ESR 0 mA ≤ IOUT ≤ 100 mA mVRM S dB dB µF mΩ µs COUT tSTART-UP Start-Up Time from Shut-down COUT = 1 µF, IOUT = 100 mA LDO2 (I/O Voltage) Characteristics Symbol Parameter Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6 V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Conditions IOUT = 125 mA, Min -3.7% Typ 3.3 Max 2.8% Units V VOUT Accuracy Output Voltage VOUT Range IOUT VOUT = 3.3 V, 3.6 V ≤ VDD_A, _D ≤ 5.5 V Programmable Output Voltage 1.5-2.3 V =100 mV step, 2.5 V, 2.8 V, Range 3.0 V and 3.3 V Rated Output Current Output Current Limit Dropout Voltage(Note 10) 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V VOUT = 0V IOUT = 125 mA IOUT = 0 mA (Note 11) 3.6 V ≤ VDD_A, _D ≤ 5.5 V, VDD_A, _D, VPVDD1,2 = 3.6 V, 1 mA ≤ IOUT ≤ 250 mA 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, TRISE,FALL = 10 us VDD_A, _D, VPVDD1,2 = 3.6 V, 25 mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns IOUT = 125 mA 1.5 0 3.3 3.3 250 615 V mA 65 55 -0.08 -0.018 192 0.312 0.018 mV µA %/V %/mA IQ ΔVOUT Quiescent Current Line Regulation Load Regulation Line Transient Regulation Load Transient Regulation 24 246 mV mV eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, 0.120 46 34 COUT = 4.7 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 4.7 µF f = 10 kHz, COUT = 4.7 µF mVRM S dB www.national.com 6 LP5551 Symbol COUT tSTART-UP Parameter Output Capacitance Output Capacitor ESR Conditions 0 mA ≤ IOUT ≤ 250 mA Min 2 5 Typ 4.7 144 Max 20 500 Units µF mΩ µs Start-Up Time from Shut-down COUT = 4.7 µF, IOUT = 250 mA LDO3 (Memory Retention Voltage) Characteristics Symbol VOFFSET Parameter Active State Buffer offset (= VO3-VFB) Output Conditions 25 mA≤IOUT ≤ 50 mA, VDD_A, _D, VPVDD1,2 = 3.6V, AVS switcher VOUT = 1.2 V, IOUT = 5 mA,VOUT = 1.2 V, Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Min 0 Typ 12 Max 82 Units mV 200 mA ≤ AVS switcher IOUT ≤ 300 mA VOUT Accuracy VOUT Range Sleep state: Memory retention voltage regulation -3.6% 0.6 1.2 1.2 3.6% V 1.35 V 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage Programming Resolution=50 mV Range (Sleep state) Quiescent Current Active mode, IOUT = 10 µA (Note 11) Sleep mode, IOUT = 10 µA (Note 11) IOUT Rated Output Current, Active state Rated Output Current, Sleep state Output Current Limit, Active state eN PSRR COUT Output Voltage Noise 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V VOUT = 0 V 10 Hz ≤ f ≤ 100 kHz, 0.0158 36 0.7 5 1 2.2 500 IQ 33 10 44 16 50 5 397 µA µA mA mVRMS dB µF mΩ COUT = 1µF Power Supply Ripple Rejection f = 217 Hz, COUT = 1.0 µF Ratio Output Capacitance Output Capacitor ESR 0 mA ≤ IOUT ≤ 5 mA LDO4 Characteristics Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Symbol Parameter Conditions IOUT = 125 mA, Min -3.7% Typ 3.3 Max 3.1% Units V VOUT Accuracy Output Voltage VOUT Range IOUT VOUT = 3.3 V, 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V Programmable Output Voltage 1.5-2.3 V =100 mV step, 2.5 V, 2.8V, Range 3.0 V and 3.3 V Rated Output Current Output Current Limit Dropout Voltage(Note 10) 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V VOUT = 0 V IOUT = 125 mA IOUT = 0 mA (Note 11) 1.5 0 3.3 3.3 250 629 V mA 65 55 246 mV µA IQ Quiescent Current 7 www.national.com LP5551 Symbol ΔVOUT Parameter Line Regulation Load Regulation Line Transient Regulation Load Transient Regulation Conditions 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V, VIN = 3.6 V, 1 mA ≤ IOUT ≤ 250 mA 3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V, TRISE,FALL = 10 us VDD_A, _D, VPVDD1,2 = 3.6 V, 25 mA ≤ IOUT ≤ 225 mA, TRISE,FALL = 100 ns IOUT = 125 mA Min -0.081 -0.018 Typ Max 0.306 0.018 Units %/V %/mA mV mV 24 246 eN PSRR Output Noise Voltage 10 Hz ≤ f ≤ 100 kHz, 0.120 46 34 2 5 144 4.7 20 500 COUT = 4.7 µF Power Supply Ripple Rejection f = 1 kHz, Ratio COUT = 4.7 µF f = 10 kHz, COUT = 4.7 µF Output Capacitance Output Capacitor ESR 0 mA ≤ IOUT ≤ 250 mA mVRM S dB COUT tSTART-UP µF mΩ µs Start-Up Time from Shut-down COUT = 4.7 µF, IOUT = 250 mA AVS/DVS Switcher Characteristics Symbol Parameter Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8) Conditions IOUT = 200 mA, VOUT = 1.2 V, Min -4.1% 0.6 Typ 1.2 1.2 0.18 0.011 15 425 345 350 805 5 0 mA ≤ IOUT ≤ 300 mA 150 4.7 440 520 1000 22 500 690 635 750 1125 Max 4.3% 1.2 Units V V %/V %/mA µA mΩ mΩ mA kHz µF mΩ µH kΩ VOUT Accuracy Output Voltage VOUT Range ΔVOUT VDD_A, _D, VPVDD1,2 = 3.6 V Programmable Output Voltage Programming Resolution = 4.7 mV Range Line regulation Load regulation 2.7V < VDD_A, _D, VPVDD1,2 VOUT(NOM) - 15 mV(Note 12) VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 01 VOUT > VOUT(NOM) - 15 mV(Note 12) VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 10 VOUT > VOUT(NOM) - 15 mV(Note 12) VDD_A, _D, PVDD1,2 = 3.6 V Bias Current Control bits = 11 VOUT > VOUT(NOM) - 15 mV(Note 12) Min 8 Typ Max Units uA 36 52 80 ISOURCE CLOAD Output Source Capability Output Capacitance of Load VDD_A, _D, PVDD1,2 = 2.7 V 0µA ≤ IOUT ≤ 3 uA 100 0.1 1 5 uA nF Logic and Control Inputs Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Symbol PWICLOCK VIL VIH VIH_PWI IIL IIL_PWI RPD_PWI TEN_LOW Parameter Rated frequency Input Low Level Input High Level Conditions 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V ENABLE, RESETN, SPWI, SCLK 2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V VPVDD1,2 ≤ 5.5 V Input High Level, PWI Logic Input Current ENABLE, RESETN 2.7 V ≤ VDD_A, _D, SPWI, SCLK, 1.5 V ≤VO2 ≤ 3.3 V ENABLE, RESETN, 0 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V SPWI, SCLK, 1.5 V ≤ VO2 ≤ 3.3 V 2 V Min Typ Max 15 0.4 Units MHz V VO2-0.4V -5 5 V µA Logic Input Current, PWI Pull-down resistance for PWI signals Minimum low pulse width to enter STARTUP state -5 0.5 1 10 15 2 µA MΩ µsec ENABLE pulsed high - low - high Logic and Control Outputs Symbol VOL VOH VOH_PWI Parameter Output low level Output high level Output high level, PWI Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to +125°C. (Notes 2, 7, 8, 9) Conditions PWROK, GPOx, SPWI, ISINK ≤ 1 mA PWROK, GPOx, ISOURCE ≤ 1 mA VBAT1-0.4V SPWI, ISOURCE ≤ 1 mA VO2-0.4V Min Typ Max 0.4 Units V V V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The amount of Absolute Maximum power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ – TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.). www.national.com 10 LP5551 Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package (LLP) (AN-1187). Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 6: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet. Note 7: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 8: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Note 9: Guaranteed by design. Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 2.7V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V Note 11: Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference. Note 12: The output voltage is guaranteed not to drop more than 15 mV (VOUT < VOUT(NOM) - 15 mV) while sinking the specified current. 11 www.national.com LP5551 Simplified Functional Diagram 20172132 FIGURE 5. Simplified Functional Diagram www.national.com 12 LP5551 Typical Performance Characteristics IQ vs. VIN Sleep, no load on LDO3 Unless otherwise stated: VIN=3.6V IQ vs. VIN Shutdown 20172104 20172105 Start-up Sequence All Outputs at Maximum Rated Load Line Transient Response VOSW, VO3 20172106 20172109 Line Transient Response VO1, VO2/4 Load Transient Response VO2/4 20172153 20172154 13 www.national.com LP5551 Load Transient Resoponse VO1 LDO1 PSRR 20172155 20172157 LDO2/4 PSRR LDO3 PSRR 20172158 20172159 Switching Frequency vs. VIN Load Transient Response AVS/DVS Switcher, Automatic PWM/PFM Transition 20172113 20172110 www.national.com 14 LP5551 Load Trainsiet Response AVS/DVS Switcher, PWM only Load Transient Response AVS/DVS Switcher, PFM only 20172114 20172115 VOUT Transient Response Min to Max Transient VOUT Transient Response Max to Min Transient 20172116 20172117 Switch Current Limit vs. VIN Efficiency vs. Load (Switcher) 20172118 20172119 15 www.national.com LP5551 Switching Waveforms PWM Switching Waveforms PFM 20172120 20172121 LP5551 PWI Register Map The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers and shows default register bit values after reset. The following sub-sections provide additional detail on the use of each individual register. Summary Register Address 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Register Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Register Usage Core voltage Unused Memory retention voltage Status register PWI version number N-well Bias P-well Bias LDO2 voltage LDO1 voltage PFM/PWM force SW_DVS voltage Enable Control LDO 4 voltage GPO Control Reserved Reserved Type R/W R/W R/W R/O R/O R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Default Value 7 0 0 0 0 0 0 0 0 0 0 0 6 1 1 0 0 0 0 1 0 0 1 0 5 1 1 0 0 0 0 1 1 1 1 0 4 1 0 0 0 0 0 1 0 1 1 0 3 1 0 1 0 0 0 1 1 1 1 0 2 1 1 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 1 0 - R0 - Core Voltage Register Address 0x0 Type R/W Reset Default 8h’7F www.national.com 16 LP5551 Bit 7 6:0 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. Core voltage value. Default value is in bold. Voltage Data Code [7:0] 7h’00 7h’xx 7h’7f Voltage Value (V) 0.6 Linear scaling 1.2 (default) R1 - Unused Register Address 0x1 Type R/W Reset Default 8h’00 Bit 7:0 Field Name Unused Description or Comment Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification). R2 – VO3 Voltage Register (Memory Retention Voltage) Address 0x2 Type R/W Reset Default 8h’60 Bit 7 6:3 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. Voltage Data Code [6:3] 4h’0 4h’1 4h’2 4h’3 4h’4 4h’5 4h’6 4h’7 4h’8 4h’9 4h’A 4h’B 4h’C 4h’D 4h’E 4h’F 2:0 Unused These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. Voltage Value (volts) 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.20 (default) 1.25 1.3 1.35 17 www.national.com LP5551 R3 - Status Register Address 0x3 Type Read Only Reset Default 8h’0F Bit 7 6 5 4 3 2 1 0 Field Name Reserved Reserved User Bit User Bit Fixed OK IO OK Memory OK Core OK Description or Comment Reserved, read returns 0 Reserved, read returns 0 Unused, read returns 0 Unused, read returns 0 Unused, read returns 1 Unused, read returns 1 Unused, read returns 1 Unused, read returns 1 R4 - PWI Version Number Register Address 0x4 Type Read Only Reset Default 8h’01 Bit 7:0 Field Name Version Description or Comment Read transaction will return 8h’01 indicating PWI 1.0 specification. Write transactions to this register are ignored. R5 - N-Well Bias Register Address 0x5 Type R/W Reset Default 8h’00 Bit 7 6:2 Field Name Sign Voltage Description or Comment 1: Negative offset 0: Positive offset Sign Data Code [7] 0 Voltage Data Code [6:2] Voltage Offset from core voltage 5h’19 – 5h’1f 5h’01 – 5h’18 5h’00 1 5h’00 5h’01 – 5h’0f 5h’10 –5h’1f 0:1 Unused 1V 0.042 - 1 V, 0.042 V steps Active clamp to SW_AVS (default) 0V -0.021 – -0.315V, -0.021 V steps -0.315 V R6 - P-Well Bias Register Address 0x6 Type R/W Reset Default 8h’00 www.national.com 18 LP5551 Bit 7 6:2 Field Name Sign Voltage Description or Comment 1: Negative offset 0: Positive offset Sign Data Code [7] 0 Voltage Data Code [6:2] Voltage Offset from ground 5h’10 –5h’1f 5h’01 – 5h’0f 5h’00 1 5h’00 5h’01 – 5h’18 5h’19 – 5h’1f 0.3 V 0.021 – 0.3V, 0.021 V steps Active clamp to ground (default) 0V -0.042 - -1 V, -0.042 V steps -1 V 0:1 Unused R7 – VO2 Voltage Register (I/O Voltage) Address 0x7 Type R/W Reset Default 8h’78 Bit 7 6:3 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. Voltage Data Code [6:3] 4h’0 4h’1 4h’2 4h’3 4h’4 4h’5 4h’6 4h’7 4h’8 4h’9 4h’A 4h’B 4h’C 4h’D 4h’E 4h’F 2:0 Unused Voltage Value (volts) 1.5 1.5 1.5 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.5 2.8 3 3.3 (default) These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into these bits using the Register Write command is ignored. R8 – VO1 Voltage Register (PLL/Fixed Voltage) Address 0x8 Type R/W Reset Default 8h’28 19 www.national.com LP5551 Bit 7 6:3 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ’0’. Any data written into this bit position using the Register Write command is ignored. Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. Voltage Data Code [6:3] 4h’0 4h’1 4h’2 4h’3 4h’4 4h’5 4h’6 4h’7 4h’8 4h’9 4h’A 4h’B 4h’C 4h’D 4h’E 4h’F Voltage Value (volts) 0.7 0.8 0.9 1 1.1 1.2 (default) 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2:0 Unused These bits are fixed to ‘0’. Reading these bits will result in a 3b’000. Any data written into these bits using the Register Write command is ignored. R9– PFM/PWM Force Register Address 0x9 Type R/W Reset Default 8h’00 Bit 7:4 3:2 Field Name Unused AVS PFM/ PWM Force Description or Comment These bits are fixed to ‘0’. Reading these bits will result in a ‘000000’. Any data written into these bits using the Register Write command is ignored. PFM Force (bit 3) Automatic Transition Automatic Transition Forced PFM Mode Forced PWM Mode 1:0 DVS PFM/ PWM Force Automatic Transition Automatic Transition Forced PFM Mode Forced PWM Mode 0 1 1 0 PFM Force (bit 1) 0 1 1 0 PWM Force (bit 2) 0 1 0 1 PWM Force (bit 0) 0 1 0 1 R10 – SW_DVS Voltage Register Address 0xA Type R/W Reset Default 8h’7F www.national.com 20 LP5551 Bit 7 6:0 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. DVS voltage value. Default value is in bold. Voltage Data Code [6:0] 7h’00 7h’xx 7h’7f Voltage Value (V) 0.6 Linear scaling 1.2 (default) R11 – Enable Control Register Address 0xB Type R/W Reset Default 8h’3F Bit 7:6 5 4 3 2 Field Name Unused R10 Enable (DVS Switcher) R9 Enable (LDO 4) R8 Enable (LDO 1) R6 Enable (P-Well bias) 1: DVS switching regulator is enabled 0: DVS switching is disabled 1: LDO 4 regulator is enabled 0: LDO 4 regulator is disabled 1: LDO 1 regulator is enabled 0: LDO 1 regulator is disabled 1: P-Well bias is enabled 0: P-Well bias is clamped to ground 1 R5 Enable (N-Well bias) 1: N-Well bias is enabled 0: N-Well bias tracks register R0 (AVS switcher voltage) 0 R2 Enable (Memory Retention) 1: Memory Retention regulator is enabled 0: Memory Retention regulator is disabled Description or Comment R12 – LDO4 Voltage Register Address 0xC Type R/W Reset Default 8h’78 21 www.national.com LP5551 Bit 7 6:3 Field Name Sign Voltage Description or Comment This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit position using the Register Write command is ignored. Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero indicates minimum voltage. Default value is in bold. Voltage Data Code [6:3] 4h’0 4h’1 4h’2 4h’3 4h’4 4h’5 4h’6 4h’7 4h’8 4h’9 4h’A 4h’B 4h’C 4h’D 4h’E 4h’F Voltage Value (volts) 1.5 1.5 1.5 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.5 2.8 3 3.3 (default) 2:0 Unused R13 – GPO Control Address 0xD Type R/W Reset Default 8h’00 Bit 7:6 5:4 Field Name Unused P-Well Sink Current Control Nominal 36 uA 52 uA 80 uA 3 2 1 0 GPO_3 control GPO_2 control GPO_1 control GPO_0 control These bits set the maximum sink current capability for the P-Well regulator bit 5 0 0 1 1 bit 4 0 1 0 1 Description or Comment Drives high to VDD_D Drives high to VDD_D Drives high to VDD_D Drives high to VDD_D R14 – Reserved Address 0xE Type R/W Reset Default 8h’00 www.national.com 22 LP5551 Bit 7:0 Field Name Unused Description or Comment Write transactions to this register are ignored. Read transactions will return a “No Response Frame.” A no response frame contains all zeros (see PWI 1.0 specification) frame. 23 www.national.com LP5551 R15 – Manufacturer Register Adress 0xF Bit 7:0 Field Name Reserved Type R/W Reset Default 8h'00 Description or Comment Do not write to this register www.national.com 24 LP5551 Operation Description DEVICE INFORMATION The LP5551 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or baseband processors in mobile phones or other portable equipment. It operates cooperatively with processors using National Semiconductor’s Advanced Power Controller (APC) to provide Adaptive or Dynamic Voltage Scaling (AVS, DVS) which drastically improves processor efficiencies compared to conventional power delivery methods. The LP5551 consists of a high efficiency switching DC/DC buck converter to supply the AVS or DVS voltage domain, three LDOs for supplying the logic, PLL, and memory, and PWI registers and logic. OPERATION STATE DIAGRAM The LP5551 has four operating states: Start-up, Active, Sleep and Standby. The Start-up state is the default state after reset. All regulators are off and PWROK output is ‘0’. The device will power up when the external enable-input is pulled high. After the powerup sequence LP5551 enters the Active state. In the Active state all regulators are on and PWROK-output is ‘1’. Immediately after Start-up the output voltages are at their default levels. LP5551 can be turned off by supplying the Shutdown command over PWI, or by setting ENABLE and/or RESETN to '0'. The LP5551 can be switched to the Sleep state by issuing the Sleep command. In the Sleep state the core voltage regulator is off, but the PWROK output is still ‘1’. The memory voltage regulator (VO3) provides the programmed memory retention voltage. LDO1 and LDO2 are on. The LP5551 can be activated from the Sleep state by giving the Wake-up command. This resumes the last programmed Active state configuration. The device can also be switched off by giving the Shutdown command, or by setting ENABLE and/or RESETN to ‘0’ In the Shutdown-state all output voltages are ‘0’, and PWROK-signal is ‘0’ as well. The LP5551 can exit the Shutdown-state if either ENABLE or RESETN is ‘0’. In either case the device moves to the Start-up state. See Figure 8. Figure 6 shows the LP5551 state diagram. The figure assumes that supply voltage to the regulator IC is in the valid range. 20172145 FIGURE 6. LP5551 State Diagram 25 www.national.com LP5551 VOLTAGE SCALING The LP5551 is designed to be used in a voltage scaling system to lower the power dissipation of baseband or application processors in mobile phones or other portable equipment. By scaling supply voltage with the clock frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported, dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). DVS systems switch between pre-characterized voltages which are paired to clock frequencies used for frequency scaling in the processor. AVS systems track the processor performance and optimize the supply voltage to the required performance. AVS is a closed loop system that provides process and temperature compensation such that for any given processor, temperature, or clock frequency, the minimum supply voltage is delivered. DIGITALLY CONTROLLED VOLTAGE SCALING The LP5551 delivers fast, controlled voltage scaling transients with the help of a digital state machine. The state machine automatically optimizes the control loop in the LP5551 switching regulator to provide large signal transients with minimal over- and undershoot. This is an important characteristic for voltage scaling systems that rely on minimal over- and undershoot to set voltages as low as possible and save energy. LARGE SIGNAL TRANSIENT RESPONSE The switching converter in the LP5551 is designed to work in a voltage scaling system. This requires that the converter has a well controlled large signal transient response. Specifically, the under- and over-shoots have to be minimal or zero while maintaining settling times less than 100 usec. Typical response plots are shown in the Typical Performance section. PowerWise™ INTERFACE To support DVS and AVS, the LP5551 is programmable via the low power, 2 wire PowerWise Interface (PWI). This serial interface controls the various voltages and states of all the regulators in the LP5551. In particular, the switching regulator voltage can be controlled between 0.6V and 1.2V in 128 steps (linear scaling). This high resolution voltage control affords accurate temperature and process compensation in AVS. The LDO voltages can also be set, however they are not intended to be dynamic in operation. The LP5551 supports the full command set as described in PWI 1.0 specification: • • • • • • • • • Core Voltage Adjust Reset Sleep Shutdown Wakeup Register Read Register Write Authenticate Synchronize modulation (PFM). In PWM the converter switches at 1MHz. Each period can be split into two cycles. During the first cycle, the high-side switch is on and the low-side switch is off, therefore the inductor current is rising. In the second cycle, the high-side switch is off and the low-side switch is on causing the inductor current to decrease. The output ripple voltage is lowest in PWM mode Figure 7. As the load current decreases, the converter efficiency becomes worse due to the increased percentage of overhead current needed to operate in PWM mode. The LP5551 can operate in PFM mode to increase efficiency at low loads. By default, the part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor valley current goes below 0 A B. The peak PMOS switch current drops below the IMODE level: During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typ) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The peak current in PFM mode is: PWM/PFM OPERATION The switching converter in the LP5551 has two modes of operation: pulse width modulation (PWM) and pulse frequency 20172103 FIGURE 7. Operation in PFM Mode and Transfer to PWM Mode www.national.com 26 LP5551 Application Information PWM/PFM FORCE REGISTER (R9) By default, the LP5551 automatically transitions between PFM and PWM to optimize efficiency. The PWM/PFM force register (R9) provides the option to override the automatic transition and force PFM or PWM operation (see R9 – PWM/ PFM Force Register declaration). Note that if the operating mode of the regulator is forced to be PFM then the switch current limit is reduced to 100 mA (50 mA average load current). EN/RESETN The LP5551 can be shutdown via the ENABLE or RESETN pins, or by issuing a shutdown command from PWI. To disable the LP5551 via hardware (as opposed to the PWI shutdown command), pull the ENABLE and/or the RESETN pin (s) low. To enable the LP5551, both the ENABLE and the RESETN pins must be high. Once enabled, the LP5551 engages the power-up sequence and all voltages return to their default values. When using PWI to issue a shutdown command, the PWI will be disabled along with the regulators in the LP5551. To reenable the part, either the ENABLE, RESETN, or both pins must be toggled (high – low – high). The part will then enter the power-up sequence and all voltages will return to their default values. Figure 8 summarizes the ENABLE/RESETN control. The ENABLE and RESETN pins provide flexibility for system control. In larger systems such as a mobile phone, it can be advantageous to enable/disable a subsystem independently. For example, the LP5551 may be powering the applications processor in a mobile phone. The system controller can power down the applications processor via the ENABLE pin, but leave on other subsystems. When the phone is turned off or in a fault condition, the system controller can have a global reset command that is connected to all the subsystems (RESETN for the LP5551). However, if this type of control is not needed, the ENABLE and RESETN pins can be tied together and used as a single enable/disable pin. INDUCTOR A 4.7uH inductor should be used with the LP5551. The inductor should be rated to handle the peak load current plus the ripple current: CURRENT LIMIT The switching converter in the LP5551 detects the peak inductor current and limits it for protection (see Electrical Characteristics table and/or Typical Performance section). To determine the average current limit from the peak current limit, the inductor size, input and output voltage, and switching frequency must be known. The LP5551 is designed to work with a 4.7uH inductor, so: INPUT CAPACITOR The input capacitor to the switching converter supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle this current: The power dissipated in the input capacitor is given by: The input capacitor must be rated to handle both the RMS current and the dissipated power. A 22 µF ceramic capacitor is recommended for the LP5551. OUTPUT CAPACITOR The switching converters in the LP5551 are designed to be used with a 22uF ceramic output capacitor. The dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. The output capacitor of the switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the 27 www.national.com 20172151 FIGURE 8. ENABLE and RESETN operation LP5551 ripple current. Ceramic capacitors are predominately used in portable systems and have very low ESR and remain capacitive up to high frequencies. The switcher peak - to - peak output voltage ripple in steady state can be calculated as: LDO LOADING CAPABILITY The LDOs in the LP5551 can regulate to a variety of output voltages, depending on the need of the processor. These voltages can be programmed through the PWI. Table 1 summarizes the parameters of the LP5551 LDOs. LDO INFORMATION The LDOs included in the LP5551 provide static supply voltages for various functions in the processor. Use the following sections to determine loading and external components. TABLE 1. LDO Parameters PWI Register Output voltage range Recommended Maximum Output Current LDO1 R8 LDO2 R7 LDO3 R2 LDO4 R12 0.6 V – 2.2 V 1.5 V – 3.3 V VOSW + 0.05 V1 0.7 V – 1.35 1.5 V – 3.3 V V2 250 mA 150 mV 100 mA 250 mA 50 mA Dropout Voltage (typical) 200 mV 150 mV 200 mV Typical Load PLL I/O Memory/Memory retention User defined 1. LDO3 tracks the switching converter output voltage (VOSW) plus a 50 mV offset when the LP5551 is in active state. 2. LDO3 regulates at the set memory retention voltage when the LP5551 is in shutdown state. LDO OUTPUT CAPACITOR ments. The LDOs in the LP5551 are designed to be used with ceramic output capacitors. The dielectric should be X5R, The output capacitor sets a low frequency pole and a high X7R, or comparable material to maintain proper tolerances. frequency zero in the control loop of an LDO. The capacitance Use the following table to choose a suitable output capacitor: and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requireTABLE 2. Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) LDO1 LDO2 LDO3 LDO4 1 µF – 20 µF (2.2 µF) 2 µF – 20 µF (4.7 µF) 0.7 µF – 2.2 µF (1.0 µF) 2 µF – 20 µF (4.7 µF) ESR range 5 mohm – 500 mohm 5 mohm – 500 mohm 5 mohm– 500 mohm 5 mohm – 500 mohm www.national.com 28 LP5551 BOARD LAYOUT CONSIDERATIONS 20172161 FIGURE 9. Board Layout Design Recommendations for the LP5551 29 www.national.com LP5551 Physical Dimensions inches (millimeters) unless otherwise noted 36-Lead LLP Package NS Package Number SQA36A www.national.com 30 LP5551 Notes 31 www.national.com LP5551 PowerWise™ Technology Compliant Energy Management Unit Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com