LP5551
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SNVS417B – DECEMBER 2006 – REVISED APRIL 2013
LP5551 PowerWise™ Technology Compliant Energy Management Unit
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FEATURES
DESCRIPTION
•
The LP5551 is a PWI 1.0 compliant Energy
Management
System
for
reducing
power
consumption of stand-alone mobile phone processors
such as base-band or applications processors.
1
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•
•
•
•
•
•
•
•
•
2 300 mA Buck Regulators Operate 180
Degrees out of Phase for Reduced EMI
1 MHz PWM Switching Frequency
4 Programmable LDOs Ideal for I/O (Two of
These), PLL, and Memory Retention Supply
Generation
Supports High-Efficiency PowerWise
Technology Adaptive Voltage Scaling
PWI Open Standard Interface for System
Power Management
Digitally Controlled Intelligent Voltage Scaling
Auto or PWI Controlled PFM Mode Transition
Internal Soft Start/Startup Sequencing
Adjustable P- and N- Well Bias Supply for
Threshold Scaling
Power OK Output
APPLICATIONS
•
•
•
•
•
•
The LP5551 contains two advanced, digitally
controlled switching regulators for supplying variable
voltage to processor core and memory. Two
regulators provide P- and N- well biasing for
threshold scaling applications. The device also
integrates 4 programmable LDO-regulators for
powering I/O, PLLs and maintaining memory
retention in shutdown-mode.
The device is controlled via the PWI open-standard
interface. The LP5551 operates cooperatively with
PowerWise™ technology compatible processors to
optimize supply voltages adaptively over process and
temperature variations or dynamically using
frequency/voltage pre-characterized look-up tables
and provides P- and N-well biasing for threshold
scaling.
Dual Core Processors
GSM/GPRS/EDGE & UMTS Cellular Handsets
Hand-Held Radios
PDAs
Battery Powered Devices
Portable Instruments
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerWise is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LP5551
SNVS417B – DECEMBER 2006 – REVISED APRIL 2013
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System Diagram
VBAT
LP5551
SW_DVS
+
SW_DVS
FB_DVS
SoC
-
VO3
LDO3
Embedded Memory
SW_AVS
SW_AVS
ENABLE
RESETN
Processor Core
AVS/DVS domain
FB_AVS
AVS
SCLK
Slave Power
Controller
(SPC)
Hardware Performance
Monitor (HPM)
SPWI
Hardware
Accelerator or
nd
2 Processor
Core
PWROK
PWI
Advanced Power
Controller (APC)
VO4
LDO4
User Defined
VO1
PLL
LDO1
VO2
LDO2
I/O Ring
P-WELL
P-Well Substrate
N-Well Substrate
N-WELL
Figure 1. System Diagram
SCLK
SPWI
EN
RESETN
PWROK
GP0
GP1
GP2
GP3
9
8
7
6
5
4
3
2
1
Connection Diagram
LDO2
10
36
NC
LDO4
11
35
VNWELL
LD01
12
34
NC
33
VPWELL
32
SCAN
GND
13
LDO3
14
NC
15
LP5551
LLP-36
31
NC
22
23
24
25
26
27
VDD_D
NC
PVDD2
SW_DVS
PGND2
PGND2
VDD_A
28
21
PGND2
18
20
29
PGND1
PVDD1
17
SW_AVS
30
PGND1
19
16
FB2
PGND1
FB1
Top View
Figure 2. LP5551 Pinout
36 - Pin WQFN Package
See Package Number NJK0036A
Note: The actual physical placement of the package marking will vary from part to part.
2
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SNVS417B – DECEMBER 2006 – REVISED APRIL 2013
Typical Application
Advanced
Power
Controller
System
Controller
Connect Die Attach Pad
(DAP) to GND
DAP
9
SCLK
8
7
EN
SPWI
1.5 - 3.3V
250 mA
6
5
4
3
2
1
PWROK
GPO1
GPO3
GPO2
RESETN
GPO0
10 LDO2
NC 36
11 LDO4
VNWELL 35
12 LD01
NC 34
4.7 PF
1.5 - 3.3V
250 mA
-0.3 - +1.0V offset
(w.r.t. AVS)
10 uA
4.7 PF
0.7 - 2.2V
100 mA
2.2 PF
0.6 - 1.35V
25 mA
-1 - +0.3V offset
(w.r.t. GND)
10 uA
VPWELL 33
13 NC
LP5551
LLP-36
14 LDO3
1.0 PF
15 NC
SCAN 32
NC 31
FB2 30
16 FB1
PGND2 29
17 PGND1
PGND2 28
18 PGND1
SW_AVS
NC
VDD_A
SW_DVS
PVDD1
VDD_D
PVDD2
PGND2
PGND1
19
20
21
22
23
24
25
26
27
22 PF
AVS
Supply
0.6V - 1.2V
300 mA
22 PF
4.7 PH
VIN
2.7V - 5.5 V
+
-
22 PF
4.7 PH
0.1 PF
0.1 PF
DVS
Supply
0.6V - 1.2V
300 mA
0.1 PF
Figure 3. Typical Application Circuit
Pin Descriptions
Pin #
I/O
Type
0
DAP
Name
G
G
Connect Die Attach Pad to ground
Description
1
GP3
O
D
General purpose output pin
2
GP2
O
D
General purpose output pin
3
GP1
O
D
General purpose output pin
4
GP0
O
D
General purpose output pin
5
PWROK
O
D
Power OK, active high output signal
6
RESETN
I
D
Reset, active low
7
EN
I
D
Enable, active high
8
SPWI
I/O
D
PowerWise Interface (PWI) bi-directional data
9
SCLK
I
D
PowerWise Interface (PWI) clock input
10
LDO2
P
P
LDO2 output, for supplying the I/O voltage on the SoC
11
LDO4
P
P
LDO4 output, for supplying a fixed voltage to a PLL etc. on the SoC
12
LDO1
P
P
LDO1 output, user defined
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Pin Descriptions (continued)
Pin #
Name
I/O
Type
P
P
LDO3 output, on-chip memory supply voltage
FB1
P
P
AVS switcher feedback
17
PGND1
G
G
Power ground for the AVS switcher
18
PGND1
G
G
Power ground for the AVS switcher
19
PGND1
G
G
Power ground for the AVS switcher
20
SW1
P
P
AVS Switcher switch node; connected to inductor
21
PVDD1
P
P
Battery supply voltage for the AVS switcher
22
VDD_D
P
P
Battery supply voltage for digital
23
VDD_A
P
P
Battery supply voltage for analog
24
NC
25
PVDD2
P
P
Battery supply voltage for the DVS switcher
26
SW2
P
P
DVS Switcher switch node; connected to inductor
27
PGND2
G
G
Power ground for the DVS switcher
28
PGND2
G
G
Power ground for the DVS switcher
29
PGND2
G
G
Power ground for the DVS switcher
30
FB2
P
P
DVS switcher feedback
31
NC
32
SCAN
33
VPWELL
P
P
P-well bias voltage
34
NC
35
VNWELL
P
P
N-well bias voltage
36
NC
13
NC
14
LDO3
15
NC
16
Description
A: Analog Pin
D: Digital Pin
I: Input Pin
O: Output Pin
I/O: Input/Output Pin
P: Power Pin
G: Ground Pin
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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SNVS417B – DECEMBER 2006 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2) (3)
VDD_A, VDD_D, PVDD1, and PVDD2
-0.3 to + 6.0V
LDO1, LDO2, LDO3, LDO4, VNWELL to GND, VPwell, ENABLE, RESETN, FB1, FB2, SW_AVS,
SW_DVS,GP0, GP1, GP2, and GP3
-0.3 to VDD_A + 0.3V
SPWI, SCLK, PWROK
-0.3 to VDD_D + 0.3V
GND, PGND1, PGND2, to GND SLUG
±0.3V
Junction Temperature (TJ-MAX)
150°C
Storage Temperature Range
-65°C to 150°C
Maximum Continuous Power Dissipation (PD-MAX)
(4)
TBD W
See (5)
Maximum Lead Temperature (Soldering)
ESD Rating
(1)
(2)
(3)
(4)
(5)
(6)
(6)
Human Body Model: All Pins
2.0kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
For detailed soldering specifications and information, please refer to TI Application Note 1187: Leadless Leadframe Package (LLP)
(SNOA401).
The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.The amount of Absolute Maximum
power dissipation allowed for the device depends on the ambient temperature and can be calculated using the formula P = (TJ –
TA)/θJA, (1) where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.Internal thermal shutdown circuitry protects
the device from permanent damage. Thermal shutdown engages at TJ=150°C (typ.) and disengages at TJ=140°C (typ.).
Operating Ratings (1) (2)
VDD_A, VDD_D, PVDD1, and PVDD2
2.7 V to 5.5 V
−40°C to +125°C
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
−40°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For specified performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAXOP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance
of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Thermal Properties (4)
Junction-to-Ambient Thermal Resistance (θJA)
(4)
39.8°C/W
Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102mm x 76mm x 1.6mm with a 2x1 array of
thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm/18µm/36µm
(1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W.Junction-to-ambient thermal
resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care
must be paid to thermal dissipation issues in board design.The value of θJA of this product can vary significantly, depending on PCB
material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT),
special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187:
Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet.
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General Electrical Characteristics
Unless otherwise noted, VDD_A, _D , VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3) (4)
Symbol
Parameter
IQ
Shutdown Supply current
Typ
Max
VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off.
-40°C ≤ TJ ≤ 125°C
Conditions
Min
0.44
4
µA
VDD_A, _D, PVDD1,2 = 3.6 V, all circuits off.
-40°C ≤ TJ ≤ 85°C
1
12
µA
Sleep State Supply Current
VDD_A, _D ,VPVDD1,2= 3.6 V, LDO3 on, LDO2
on (no load). All other circuits off.
135
186
µA
Acitve State Supply Current
VDD_A, _D, VPVDD1,2 = 3.6 V, all outputs on,
no load
431
742
µA
UVLO high
Under Voltage Lockout, high
threshold
UVLO low
Under Voltage Lockout, low
threshold
TSD
Thermal Shutdown Threshold
160
Thermal Shutdown Hysteresis
10
(1)
(2)
(3)
(4)
6
Units
2.7
2.5
°C
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Specified by design.
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LDO1 (PLL/Fixed Voltage) Characteristics
Unless otherwise noted, VDD_A, _D, VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3)
Symbol
Min
Typ
Max
Units
Output Voltage
IOUT = 50 mA, VOUT = 1.2 V,
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
-3.5%
1.2
3.1%
V
VOUT Range
Programmable Output Voltage
Range
Programming Resolution = 100 mV
0.7
1.2
2.2
V
IOUT
Rated Output Current
2.7 V ≤ VDD_A, _D ,PVDD1,2≤ 5.5 V
Output Current Limit
VOUT = 0 V
Quiescent Current
IOUT = 0 mA (4)
Line Regulation
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V,
IOUT = 50 mA
-0.083
0.316
%/V
Load Regulation
VDD_A, _D, VPVDD1,2 = 3.6 V,
1 mA ≤ IOUT ≤ 100 mA
-0.013
0.013
%/mA
Line Transient Regulation
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V,
TRISE,FALL = 10 µs
27
mV
Load Transient Regulation
VDD_A, _D, VPVDD1,2= 3.6 V,
10 mA ≤ IOUT ≤ 90 mA,
TRISE,FALL = 100 ns
86
mV
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz, COUT = 2.2 µF
0.103
mVRMS
PSRR
Power Supply Ripple Rejection
Ratio
f = 1 kHz, COUT = 2.2 µF
56
dB
f = 10 kHz, COUT = 2.2 µF
36
COUT
Output CapacitanceOutput
Capacitor ESR
0 mA ≤ IOUT ≤ 100 mA
tSTART-UP
Start-Up Time from Shut-down
COUT = 1 µF, OUT = 100 mA
VOUT Accuracy
IQ
ΔVOUT
(1)
(2)
(3)
(4)
Parameter
Conditions
0
100
mA
347
35
1
2.2
5
µA
dB
20
µF
500
mΩ
54
µs
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference.
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LDO2 (I/O Voltage) Characteristics
Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6 V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-3.7%
3.3
2.8%
V
1.5
3.3
3.3
V
VOUT Accuracy
Output Voltage
IOUT = 125 mA, VOUT = 3.3 V,
3.6 V ≤ VDD_A, _D ≤ 5.5 V
VOUT Range
Programmable Output Voltage
Range
1.5-2.3 V = 100 mV step, 2.5 V, 2.8 V,
3.0 V and 3.3 V
IOUT
Rated Output Current
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
Output Current Limit
VOUT = 0V
Dropout Voltage (4)
IOUT = 125 mA
65
Quiescent Current
IOUT = 0 mA (5)
55
Line Regulation
3.6 V ≤ VDD_A, _D ≤ 5.5 V,
IOUT = 125 mA
-0.08
0.312
%/V
Load Regulation
VDD_A, _D, VPVDD1,2 = 3.6 V,
1 mA ≤ IOUT ≤ 250 mA
-0.018
0.018
%/mA
Line Transient Regulation
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V,
TRISE,FALL = 10 us
24
mV
Load Transient Regulation
VDD_A, _D, VPVDD1,2 = 3.6 V,
25 mA ≤ IOUT ≤ 225 mA,
TRISE,FALL = 100 ns
246
mV
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz,COUT = 4.7 µF
0.120
mVRMS
Power Supply Ripple Rejection
Ratio
f = 1 kHz, COUT = 4.7 µF
46
dB
f = 10 kHz, COUT = 4.7 µF
34
IQ
ΔVOUT
eN
PSRR
COUT
Output Capacitance
Output Capacitor ESR
tSTART-UP
(1)
(2)
(3)
(4)
(5)
8
Start-Up Time from Shut-down
0 mA ≤ IOUT ≤ 250 mA
COUT = 4.7 µF, IOUT = 250 mA
0
250
615
2
4.7
5
144
192
mA
mV
µA
20
µF
500
mΩ
µs
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification
does not apply in cases it implies operation with an input voltage below the 2.7V minimum appearing under Operating Ratings. For
example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input
voltage at or about 1.5V
Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference.
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LDO3 (Memory Retention Voltage) Characteristics
Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3)
Symbol
Parameter
VOFFSET
Active State Buffer offset
(= VO3-VFB) Output
Conditions
25 mA≤IOUT ≤ 50 mA,
VDD_A, _D, VPVDD1,2 = 3.6V,
AVS switcher VOUT = 1.2 V,
200 mA ≤ AVS switcher IOUT ≤ 300 mA
Min
Typ
Max
Units
0
12
82
mV
VOUT Accuracy Sleep state: Memory retention
voltage regulation
IOUT = 5 mA,VOUT = 1.2 V,
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
-3.6%
1.2
3.6%
V
VOUT Range
Programming Resolution = 50 mV
0.6
1.2
1.35
V
Active mode, IOUT = 10 µA (4)
33
44
µA
Sleep mode, IOUT = 10 µA (4)
10
16
µA
IQ
Programmable Output Voltage
Range (Sleep state)
Quiescent Current
IOUT
Rated Output Current, Active
state
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
50
Rated Output Current, Sleep
state
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
5
Output Current Limit, Active state
VOUT = 0 V
eN
Output Voltage Noise
10 Hz ≤ f ≤ 100 kHz, COUT = 1µF
PSRR
Power Supply Ripple Rejection
Ratio
f = 217 Hz, COUT = 1.0 µF
COUT
Output Capacitance
Output Capacitor ESR
(1)
(2)
(3)
(4)
0 mA ≤ IOUT ≤ 5 mA
mA
397
0.7
5
0.0158
mVRMS
36
dB
1
2.2
µF
500
mΩ
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference.
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LDO4 Characteristics
Unless otherwise noted, VDD_A, _D , VPVDD1,2 RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-3.7%
3.3
3.1%
V
1.5
3.3
3.3
V
VOUT Accuracy
Output Voltage
IOUT = 125 mA, VOUT = 3.3 V,
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
VOUT Range
Programmable Output Voltage
Range
1.5-2.3 V =100 mV step, 2.5 V, 2.8V,
3.0 V and 3.3 V
IOUT
Rated Output Current
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
Output Current Limit
VOUT = 0 V
Dropout Voltage (4)
IOUT = 125 mA
65
Quiescent Current
IOUT = 0 mA (5)
55
Line Regulation
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V,
IOUT = 125 mA
-0.081
0.306
%/V
Load Regulation
VIN = 3.6 V, 1 mA ≤ IOUT ≤ 250 mA
-0.018
0.018
%/mA
Line Transient Regulation
3.6 V ≤ VDD_A, _D, VPVDD1,2 ≤ 3.9 V,
TRISE,FALL = 10 us
24
mV
Load Transient Regulation
VDD_A, _D, VPVDD1,2 = 3.6 V,
25 mA ≤ IOUT ≤ 225 mA,
TRISE,FALL = 100 ns
246
mV
eN
Output Noise Voltage
10 Hz ≤ f ≤ 100 kHz, COUT = 4.7 µF
0.120
mVRMS
PSRR
Power Supply Ripple Rejection
Ratio
f = 1 kHz, COUT = 4.7 µF
46
f = 10 kHz, COUT = 4.7 µF
34
IQ
ΔVOUT
COUT
Output Capacitance
Output Capacitor ESR
tSTART-UP
(1)
(2)
(3)
(4)
(5)
10
Start-Up Time from Shut-down
0 mA ≤ IOUT ≤ 250 mA
COUT = 4.7 µF, IOUT = 250 mA
0
250
629
2
4.7
5
144
246
mA
mV
µA
dB
20
µF
500
mΩ
µs
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification
does not apply in cases it implies operation with an input voltage below the 2.7V minimum appearing under Operating Ratings. For
example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input
voltage at or about 1.5V
Quiescent current for LDO1, LDO2, LDO3, and LDO4 do not include shared functional blocks such as the bandgap reference.
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AVS/DVS Switcher Characteristics
Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3)
Symbol
VOUT Accuracy
Parameter
Conditions
Min
Typ
Max
Units
-4.1%
1.2
4.3%
V
0.6
1.2
1.2
V
Output Voltage
IOUT = 200 mA, VOUT = 1.2 V,
VDD_A, _D, VPVDD1,2 = 3.6 V
VOUT Range
Programmable Output Voltage
Range
Programming Resolution = 4.7 mV
ΔVOUT
Line regulation
2.7V < VDD_A, _D, VPVDD1,2 VOUT(NOM) - 15 mV (4)
8
VDD_A, _D, PVDD1,2 = 3.6 V
Bias Current Control bits = 01
VOUT > VOUT(NOM) - 15 mV (4)
36
VDD_A, _D, PVDD1,2 = 3.6 V
Bias Current Control bits = 10
VOUT > VOUT(NOM) - 15 mV (4)
52
VDD_A, _D, PVDD1,2 = 3.6 V
Bias Current Control bits = 11
VOUT > VOUT(NOM) - 15 mV (4)
80
100
ISOURCE
Output Source Capability
VDD_A,
CLOAD
Output Capacitance of Load
0µA ≤ IOUT ≤ 3 uA
(3)
(4)
Typ
Output Voltage Tolerance
ISINK
(1)
(2)
Min
VOUT = 0 V, IOUT = 10 µA
2.7 ≤ VDD_A, _D, PVDD1,2 ≤ 5.5 V
Bias Current Control bits = 00
_D,
PVDD1,2 = 2.7 V
0
0.035
V
0
0.3
V
150
270
uA
uA
0.1
uA
1
5
nF
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
The output voltage is specified not to drop more than 15 mV (VOUT < VOUT(NOM) - 15 mV) while sinking the specified current.
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Logic and Control Inputs
Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Rated frequency
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
15
MHz
VIL
Input Low Level
ENABLE, RESETN, SPWI, SCLK
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
0.4
V
VIH
Input High Level
ENABLE, RESETN
2.7 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
VIH_PWI
Input High Level, PWI
IIL
PWICLOCK
2
V
SPWI, SCLK, 1.5 V ≤VO2 ≤ 3.3 V
VO2-0.4V
V
Logic Input Current
ENABLE, RESETN,
0 V ≤ VDD_A, _D, VPVDD1,2 ≤ 5.5 V
-5
5
µA
IIL_PWI
Logic Input Current, PWI
SPWI, SCLK, 1.5 V ≤ VO2 ≤ 3.3 V
-5
15
µA
RPD_PWI
Pull-down resistance for PWI
signals
2
MΩ
TEN_LOW
Minimum low pulse width to enter
STARTUP state
(1)
(2)
0.5
ENABLE pulsed high - low - high
1
10
µsec
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Specified by design.
(3)
(4)
Logic and Control Outputs
Unless otherwise noted, VDD_A, _D, VPVDD1,2 , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type
apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to
+125°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
VOL
Output low level
PWROK, GPOx, SPWI, ISINK ≤ 1 mA
VOH
Output high level
PWROK, GPOx, ISOURCE ≤ 1 mA
VOH_PWI
Output high level, PWI
SPWI, ISOURCE ≤ 1 mA
(1)
(2)
(3)
(4)
14
Min
Typ
Max
Units
0.4
V
VBAT1-0.4V
V
VO2-0.4V
V
All voltages are with respect to the potential at the GND pin.
All limits are ensured by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested
during production with TJ = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics
Specified by design.
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Simplified Functional Diagram
VBAT_SW
FB_AVS/DVS
LP5551
Input Voltage
Feed Forward
SW_AVS/
DVS
+
4.7 PH
FB_AVS/
DVS
PWM
Driver
+
-
22 PF
PWM REF
PWI Control
x2 Switching Regulators
VBAT1
LDO1/2/4
VBAT2
PWI Control
+
VREF
x3 LDOs
LDO3
PWI Control
SCLK
1 PF
SPWI
PWI
LOGIC
+
-
EN
PWI Control
2
VREF
1: Active
2: Sleep 1
RESET
+
6
50 mV
PWROK
P-WELL
DAC
+
FB_AVS
+
-
PWI Control
+
+
PWI Control
AGND
DGND
PGND
DAC
+
6
N_WELL
+
-
PGND
Figure 4. Simplified Functional Diagram
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Typical Performance Characteristics
Unless otherwise stated: VIN = 3.6V
IQ vs. VIN
Sleep, no load on LDO3
93.0
9.0
86.6
7.6
80.2
6.2
TA = -40oC
Iq (PA)
TA = 85oC
Iq (PA)
IQ vs. VINShutdown
73.8
4.8
67.4
TA = 85oC
3.4
TA = 25oC
TA = 25oC
o
TA = -40 C
61.0
3.0
3.5
4.0
4.5
5.0
2.0
3.0
5.5
3.5
4.0
4.5
5.0
5.5
VIN (V)
VIN (V)
Figure 5.
Figure 6.
Start-up Sequence
All Outputs at Maximum Rated Load
Line Transient Response VOSW, VO3
VIN
5V
3.6V
VOSW
AC Coupled,
50 mV/DIV
VO3
AC Coupled,
2 mV/DIV
50 Ps/DIV
VIN
Figure 7.
Figure 8.
Line Transient Response VO1, VO2/4
Load Transient Response VO2/4
5V
3.6V
VO1
AC Coupled,
2 mV/DIV
VO2
AC Coupled,
2 mV/DIV
50 Ps/DIV
Figure 9.
16
Figure 10.
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Typical Performance Characteristics (continued)
Unless otherwise stated: VIN = 3.6V
Load Transient Response VO1
LDO1 PSRR
0
-10
VO1
MAGNITUDE (dB)
-20
20 mV/DIV
100 mA
-30
-40
-50
No Load
-60
IOUT
100 mA/DIV
-70
-80
2
10
100 Ps/DIV
10
3
10
4
5
10
10
6
FREQUENCY (Hz)
Figure 11.
Figure 12.
LDO3 PSRR
0
-10
-10
-20
-20
-30
MAGNITUDE (dB)
MAGNITUDE (dB)
LDO2/4 PSRR
0
200 mA
-40
No Load
-50
-30
-40
-60
-60
-70
-70
-80
10
2
10
3
10
4
5
10
10
No Load
-50
-80
6
10
FREQUENCY (Hz)
2
10
3
10
4
5
10
10
6
FREQUENCY (Hz)
Figure 13.
Figure 14.
Switching Frequency vs. VIN
Load Transient Response
AVS/DVS Switcher, Automatic PWM/PFM Transition
1.10M
T = 85°C
SWITCHING FREQUENCY (Hz)
A
1.07M
TA = 25°C
1.05M
1.02M
996.00k
TA = -40°C
970.00k
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
Figure 15.
Figure 16.
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Typical Performance Characteristics (continued)
Unless otherwise stated: VIN = 3.6V
570.0
Load Transient Response
AVS/DVS Switcher, PWM only
Load Transient Response
AVS/DVS Switcher, PFM only
Figure 17.
Figure 18.
VOUT Transient Response
Min to Max Transient
VOUT Transient Response
Max to Min Transient
Figure 19.
Figure 20.
Switch Current Limit vs. VIN
Efficiency vs. Load (Switcher)
95.0
TA = 85°C
VIN = 3V
TA = 25°C
90.0
EFFICIENCY (%)
ICL (mA)
554.0
538.0
522.0
TA = -40°C
85.0
VIN = 3.6V
80.0
VIN = 4.2V
506.0
490.0
3.0
75.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
70.0
1.0e1
1.0e2
1.0e3
IOUT (mA)
Figure 21.
18
VIN = 5.5V
Figure 22.
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Typical Performance Characteristics (continued)
Unless otherwise stated: VIN = 3.6V
Switching Waveforms PWM
Switching Waveforms PFM
VSW
VSW
2V/DIV
2V/DIV
VOUT
20 mV/DIV
IL
100 mA/DIV
VOUT
20 mV/DIV
IL
1 Ps/DIV
100 mA/DIV
2 Ps/DIV
Figure 23.
Figure 24.
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LP5551 PWI Register Map
The PWI standard supports sixteen 8-bit registers on the PWI slave. The table below summarizes these registers
and shows default register bit values after reset. The following sub-sections provide additional detail on the use
of each individual register.
Table 1. Summary
Register
Address
Register
Name
0x0
R0
Core voltage
0x1
R1
Unused
0x2
R2
0x3
Register Usage
Type
Reset Default Value
7
6
5
4
3
2
1
0
R/W
0
1
1
1
1
1
1
1
R/W
-
-
-
-
-
-
-
-
Memory retention voltage
R/W
0
1
1
0
0
-
-
-
R3
Status register
R/O
0
0
0
0
1
1
1
1
0x4
R4
PWI version number
R/O
0
0
0
0
0
0
0
1
0x5
R5
N-well Bias
R/W
0
0
0
0
0
0
-
-
0x6
R6
P-well Bias
R/W
0
0
0
0
0
0
-
-
0x7
R7
LDO2 voltage
R/W
0
1
1
1
1
-
-
-
0x8
R8
LDO1 voltage
R/W
0
0
1
0
1
-
-
-
0x9
R9
PFM/PWM force
R/W
0
0
-
-
-
-
-
-
0xA
R10
SW_DVS voltage
R/W
-
-
-
-
-
-
-
-
0xB
R11
Enable Control
R/W
-
-
1
1
1
1
1
1
0xC
R12
LDO 4 voltage
R/W
0
1
1
1
1
-
-
-
0xD
R13
GPO Control
R/W
0
0
0
0
0
0
0
0
0xE
R14
Reserved
R/W
-
-
-
-
-
-
-
-
0xF
R15
Reserved
R/W
-
-
-
-
-
-
-
-
R0 - Core Voltage Register
Address 0x0
Type R/W
Reset Default 8h’7F
Bit
Field Name
7
Sign
6:0
Voltage
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit
position using the Register Write command is ignored.
Core voltage value. Default value is in bold.
Voltage Data Code [7:0]
Voltage Value (V)
7h’00
0.6
7h’xx
Linear scaling
7h’7f
1.2 (default)
R1 - Unused Register
Address 0x1
Type R/W
Reset Default 8h’00
20
Bit
Field Name
7:0
Unused
Description or Comment
Write transactions to this register are ignored. Read transactions will return a
“No Response Frame.” A no response frame contains all zeros (see PWI 1.0
specification).
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R2 – VO3 Voltage Register (Memory Retention Voltage)
Address 0x2
Type R/W
Reset Default 8h’60
Bit
Field Name
7
Sign
6:3
Voltage
2:0
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit
position using the Register Write command is ignored.
Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero
indicates minimum voltage. Default value is in bold.
Unused
Voltage Data Code [6:3]
Voltage Value (volts)
4h’0
0.6
4h’1
0.65
4h’2
0.7
4h’3
0.75
4h’4
0.8
4h’5
0.85
4h’6
0.9
4h’7
0.95
4h’8
1
4h’9
1.05
4h’A
1.1
4h’B
1.15
4h’C
1.20 (default)
4h’D
1.25
4h’E
1.3
4h’F
1.35
These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into
these bits using the Register Write command is ignored.
R3 - Status Register
Address 0x3
Type Read Only
Reset Default 8h’0F
Bit
Field Name
7
Reserved
Reserved, read returns 0
Description or Comment
6
Reserved
Reserved, read returns 0
5
User Bit
Unused, read returns 0
4
User Bit
Unused, read returns 0
3
Fixed OK
Unused, read returns 1
2
IO OK
Unused, read returns 1
1
Memory OK
Unused, read returns 1
0
Core OK
Unused, read returns 1
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R4 - PWI Version Number Register
Address 0x4
Type Read Only
Reset Default 8h’01
Bit
Field Name
7:0
Version
Description or Comment
Read transaction will return 8h’01 indicating PWI 1.0 specification. Write
transactions to this register are ignored.
R5 - N-Well Bias Register
Address 0x5
Type R/W
Reset Default 8h’00
Bit
Field Name
7
Sign
6:2
Voltage
Description or Comment
1: Negative offset
0: Positive offset
Sign Data Code [7]
Voltage Data Code [6:2]
Voltage Offset from core
voltage
0
5h’19 – 5h’1f
1V
5h’01 – 5h’18
0.042 - 1 V, 0.042 V steps
5h’00
Active clamp to
SW_AVS (default)
5h’00
0V
5h’01 – 5h’0f
-0.021 – -0.315V, -0.021
V steps
5h’10 –5h’1f
-0.315 V
1
0:1
Unused
R6 - P-Well Bias Register
Address 0x6
Type R/W
Reset Default 8h’00
Bit
Field Name
7
Sign
6:2
Voltage
Description or Comment
1: Negative offset
0: Positive offset
Sign Data Code [7]
Voltage Data Code [6:2]
Voltage Offset from
ground
0
5h’10 –5h’1f
0.3 V
5h’01 – 5h’0f
0.021 – 0.3V, 0.021 V
steps
5h’00
Active clamp to ground
(default)
5h’00
0V
5h’01 – 5h’18
-0.042 - -1 V, -0.042 V
steps
5h’19 – 5h’1f
-1 V
1
0:1
22
Unused
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R7 – VO2 Voltage Register (I/O Voltage)
Address 0x7
Type R/W
Reset Default 8h’78
Bit
Field Name
7
Sign
6:3
Voltage
2:0
Unused
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit
position using the Register Write command is ignored.
Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero
indicates minimum voltage. Default value is in bold.
Voltage Data Code [6:3]
Voltage Value (volts)
4h’0
1.5
4h’1
1.5
4h’2
1.5
4h’3
1.5
4h’4
1.6
4h’5
1.7
4h’6
1.8
4h’7
1.9
4h’8
2
4h’9
2.1
4h’A
2.2
4h’B
2.3
4h’C
2.5
4h’D
2.8
4h’E
3
4h’F
3.3 (default)
These bits are fixed to ‘0’. Reading these bits will result in a ‘000’. Any data written into
these bits using the Register Write command is ignored.
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R8 – VO1 Voltage Register (PLL/Fixed Voltage)
Address 0x8
Type R/W
Reset Default 8h’28
Bit
Field Name
7
Sign
6:3
Voltage
2:0
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ’0’. Any data written into this bit
position using the Register Write command is ignored.
Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero
indicates minimum voltage. Default value is in bold.
Unused
Voltage Data Code [6:3]
Voltage Value (volts)
4h’0
0.7
4h’1
0.8
4h’2
0.9
4h’3
1
4h’4
1.1
4h’5
1.2 (default)
4h’6
1.3
4h’7
1.4
4h’8
1.5
4h’9
1.6
4h’A
1.7
4h’B
1.8
4h’C
1.9
4h’D
2
4h’E
2.1
4h’F
2.2
These bits are fixed to ‘0’. Reading these bits will result in a 3b’000. Any data written into
these bits using the Register Write command is ignored.
R9– PFM/PWM Force Register
Address 0x9
Type R/W
Reset Default 8h’00
Bit
Field Name
7:4
Unused
3:2
AVS PFM/PWM
Force
1:0
24
DVS PFM/PWM
Force
Description or Comment
These bits are fixed to ‘0’. Reading these bits will result in a ‘000000’. Any data written into these bits
using the Register Write command is ignored.
PFM Force (bit 3)
PWM Force (bit 2)
Automatic Transition
0
0
Automatic Transition
1
1
Forced PFM Mode
1
0
Forced PWM Mode
0
1
PFM Force (bit 1)
PWM Force (bit 0)
Automatic Transition
0
0
Automatic Transition
1
1
Forced PFM Mode
1
0
Forced PWM Mode
0
1
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R10 – SW_DVS Voltage Register
Address 0xA
Type R/W
Reset Default 8h’7F
Bit
Field Name
7
Sign
6:0
Voltage
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit
position using the Register Write command is ignored.
DVS voltage value. Default value is in bold.
Voltage Data Code [6:0]
Voltage Value (V)
7h’00
0.6
7h’xx
Linear scaling
7h’7f
1.2 (default)
R11 – Enable Control Register
Address 0xB
Type R/W
Reset Default 8h’3F
Bit
Field Name
7:6
Unused
5
R10 Enable (DVS Switcher)
4
R9 Enable (LDO 4)
3
R8 Enable (LDO 1)
Description or Comment
1: DVS switching regulator is enabled
0: DVS switching is disabled
1: LDO 4 regulator is enabled
0: LDO 4 regulator is disabled
1: LDO 1 regulator is enabled
0: LDO 1 regulator is disabled
2
R6 Enable (P-Well bias)
1
R5 Enable (N-Well bias)
1: P-Well bias is enabled
0: P-Well bias is clamped to ground
1: N-Well bias is enabled
0: N-Well bias tracks register R0 (AVS switcher
voltage)
0
R2 Enable (Memory Retention)
1: Memory Retention regulator is enabled
0: Memory Retention regulator is disabled
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R12 – LDO4 Voltage Register
Address 0xC
Type R/W
Reset Default 8h’78
Bit
Field Name
7
Sign
6:3
Voltage
2:0
Description or Comment
This bit is fixed to ‘0’. Reading this bit will result in a ‘0’. Any data written into this bit
position using the Register Write command is ignored.
Fixed voltage value. A code of all ones indicates maximum voltage while a code of all zero
indicates minimum voltage. Default value is in bold.
Voltage Data Code [6:3]
Voltage Value (volts)
4h’0
1.5
4h’1
1.5
4h’2
1.5
4h’3
1.5
4h’4
1.6
4h’5
1.7
4h’6
1.8
4h’7
1.9
4h’8
2
4h’9
2.1
4h’A
2.2
4h’B
2.3
4h’C
2.5
4h’D
2.8
4h’E
3
4h’F
3.3 (default)
Unused
R13 – GPO Control
Address 0xD
Type R/W
Reset Default 8h’00
26
Bit
Field Name
7:6
Unused
5:4
P-Well Sink
Current Control
Description or Comment
These bits set the maximum sink current capability for the P-Well regulator
bit 5
bit 4
Nominal
0
0
36 uA
0
1
52 uA
1
0
80 uA
1
1
3
GPO_3 control
Drives high to VDD_D
2
GPO_2 control
Drives high to VDD_D
1
GPO_1 control
Drives high to VDD_D
0
GPO_0 control
Drives high to VDD_D
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R14 – Reserved
Address 0xE
Type R/W
Reset Default 8h’00
Bit
Field Name
7:0
Unused
Description or Comment
Write transactions to this register are ignored. Read transactions will return a
“No Response Frame.” A no response frame contains all zeros (see PWI 1.0
specification) frame.
R15 – Manufacturer Register
Adress 0xF
Type R/W
Reset Default 8h'00
Bit
Field Name
7:0
Reserved
Description or Comment
Do not write to this register
Operation Description
DEVICE INFORMATION
The LP5551 is a PowerWise Interface (PWI) compliant power management unit (PMU) for application or
baseband processors in mobile phones or other portable equipment. It operates cooperatively with processors
using TI’s Advanced Power Controller (APC) to provide Adaptive or Dynamic Voltage Scaling (AVS, DVS) which
drastically improves processor efficiencies compared to conventional power delivery methods. The LP5551
consists of a high efficiency switching DC/DC buck converter to supply the AVS or DVS voltage domain, three
LDOs for supplying the logic, PLL, and memory, and PWI registers and logic.
OPERATION STATE DIAGRAM
The LP5551 has four operating states: Start-up, Active, Sleep and Standby.
The Start-up state is the default state after reset. All regulators are off and PWROK output is ‘0’. The device will
power up when the external enable-input is pulled high. After the power-up sequence LP5551 enters the Active
state.
In the Active state all regulators are on and PWROK-output is ‘1’. Immediately after Start-up the output voltages
are at their default levels. LP5551 can be turned off by supplying the Shutdown command over PWI, or by setting
ENABLE and/or RESETN to '0'. The LP5551 can be switched to the Sleep state by issuing the Sleep command.
In the Sleep state the core voltage regulator is off, but the PWROK output is still ‘1’. The memory voltage
regulator (VO3) provides the programmed memory retention voltage. LDO1 and LDO2 are on. The LP5551 can
be activated from the Sleep state by giving the Wake-up command. This resumes the last programmed Active
state configuration. The device can also be switched off by giving the Shutdown command, or by setting
ENABLE and/or RESETN to ‘0’
In the Shutdown-state all output voltages are ‘0’, and PWROK-signal is ‘0’ as well. The LP5551 can exit the
Shutdown-state if either ENABLE or RESETN is ‘0’. In either case the device moves to the Start-up state. See
Figure 27.
Figure 25 shows the LP5551 state diagram. The figure assumes that supply voltage to the regulator IC is in the
valid range.
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RESET (Command or External)
From any state
ENABLE = µ0¶
SHUTDOWN
All regulators disabled
Power OK = ¶0¶
ENABLE = µ0¶
Shutdown
command
STARTUP
All regulators disabled
Power OK = '0'
ENABLE = µ0¶
Shutdown
command
Wakeup command
ENABLE = µ1¶
SLEEP
AVS regulator disabled
memory supply at retention level
enabled regulators on
Power OK = '1'
ACTIVE
Enabled regulators on
Power OK = '1'
Sleep command
Figure 25. LP5551 State Diagram
VOLTAGE SCALING
The LP5551 is designed to be used in a voltage scaling system to lower the power dissipation of baseband or
application processors in mobile phones or other portable equipment. By scaling supply voltage with the clock
frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported,
dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). DVS systems switch between precharacterized voltages which are paired to clock frequencies used for frequency scaling in the processor. AVS
systems track the processor performance and optimize the supply voltage to the required performance. AVS is a
closed loop system that provides process and temperature compensation such that for any given processor,
temperature, or clock frequency, the minimum supply voltage is delivered.
DIGITALLY CONTROLLED VOLTAGE SCALING
The LP5551 delivers fast, controlled voltage scaling transients with the help of a digital state machine. The state
machine automatically optimizes the control loop in the LP5551 switching regulator to provide large signal
transients with minimal over- and undershoot. This is an important characteristic for voltage scaling systems that
rely on minimal over- and undershoot to set voltages as low as possible and save energy.
LARGE SIGNAL TRANSIENT RESPONSE
The switching converter in the LP5551 is designed to work in a voltage scaling system. This requires that the
converter has a well controlled large signal transient response. Specifically, the under- and over-shoots have to
be minimal or zero while maintaining settling times less than 100 usec. Typical response plots are shown in the
Typical Performance Characteristics section.
28
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PowerWise™ INTERFACE
To support DVS and AVS, the LP5551 is programmable via the low power, 2 wire PowerWise Interface (PWI).
This serial interface controls the various voltages and states of all the regulators in the LP5551. In particular, the
switching regulator voltage can be controlled between 0.6V and 1.2V in 128 steps (linear scaling). This high
resolution voltage control affords accurate temperature and process compensation in AVS. The LDO voltages
can also be set, however they are not intended to be dynamic in operation. The LP5551 supports the full
command set as described in PWI 1.0 specification:
• Core Voltage Adjust
• Reset
• Sleep
• Shutdown
• Wakeup
• Register Read
• Register Write
• Authenticate
• Synchronize
PWM/PFM OPERATION
The switching converter in the LP5551 has two modes of operation: pulse width modulation (PWM) and pulse
frequency modulation (PFM). In PWM the converter switches at 1MHz. Each period can be split into two cycles.
During the first cycle, the high-side switch is on and the low-side switch is off, therefore the inductor current is
rising. In the second cycle, the high-side switch is off and the low-side switch is on causing the inductor current
to decrease. The output ripple voltage is lowest in PWM mode Figure 26. As the load current decreases, the
converter efficiency becomes worse due to the increased percentage of overhead current needed to operate in
PWM mode. The LP5551 can operate in PFM mode to increase efficiency at low loads.
By default, the part will automatically transition into PFM mode when either of two conditions occurs for a
duration of 32 or more clock cycles:
A. The inductor valley current goes below 0 A
B. The peak PMOS switch current drops below the IMODE level:
VIN
(typ)
IMODE < 26 mA +
50:
(1)
During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage
during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy
load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output
FETs such that the output voltage ramps between 0.8% and 1.6% (typ) above the nominal PWM output voltage.
If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It
remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level
set for PFM mode. The peak current in PFM mode is:
VIN
(typ)
IPFM = 117 mA +
64:
(2)
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Figure 26. Operation in PFM Mode and Transfer to PWM Mode
APPLICATION INFORMATION
PWM/PFM FORCE REGISTER (R9)
By default, the LP5551 automatically transitions between PFM and PWM to optimize efficiency. The PWM/PFM
force register (R9) provides the option to override the automatic transition and force PFM or PWM operation (see
R9– PFM/PWM Force Register declaration). Note that if the operating mode of the regulator is forced to be PFM
then the switch current limit is reduced to 100 mA (50 mA average load current).
EN/RESETN
The LP5551 can be shutdown via the ENABLE or RESETN pins, or by issuing a shutdown command from PWI.
To disable the LP5551 via hardware (as opposed to the PWI shutdown command), pull the ENABLE and/or the
RESETN pin(s) low. To enable the LP5551, both the ENABLE and the RESETN pins must be high. Once
enabled, the LP5551 engages the power-up sequence and all voltages return to their default values.
When using PWI to issue a shutdown command, the PWI will be disabled along with the regulators in the
LP5551. To re-enable the part, either the ENABLE, RESETN, or both pins must be toggled (high – low – high).
The part will then enter the power-up sequence and all voltages will return to their default values. Figure 27
summarizes the ENABLE/RESETN control.
The ENABLE and RESETN pins provide flexibility for system control. In larger systems such as a mobile phone,
it can be advantageous to enable/disable a subsystem independently. For example, the LP5551 may be
powering the applications processor in a mobile phone. The system controller can power down the applications
processor via the ENABLE pin, but leave on other subsystems. When the phone is turned off or in a fault
condition, the system controller can have a global reset command that is connected to all the subsystems
(RESETN for the LP5551). However, if this type of control is not needed, the ENABLE and RESETN pins can be
tied together and used as a single enable/disable pin.
30
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xx
Shutdown Command
PWI
OFF
x
OFF
EN and
RESETN
Voltages
On
Off
Figure 27. ENABLE and RESETN operation
INDUCTOR
A 4.7uH inductor should be used with the LP5551. The inductor should be rated to handle the peak load current
plus the ripple current:
IL(MAX) = ILOAD(MAX) + 'iL(MAX)
= ILOAD(MAX) +
= ILOAD(MAX) +
D x (VIN(MAX) - VOUT)
2 x L x fS
D x (VIN(MAX) - VOUT)
9.4
(A) ,
fS = 1 MHz,
L = 4.7 PH
(3)
CURRENT LIMIT
The switching converter in the LP5551 detects the peak inductor current and limits it for protection (see General
Electrical Characteristics table and/or Typical Performance Characteristics section). To determine the average
current limit from the peak current limit, the inductor size, input and output voltage, and switching frequency must
be known. The LP5551 is designed to work with a 4.7uH inductor, so:
ICL_AVG = ICL_PK - 'iL
= ICL_PK -
| 0.4 -
D x (VIN - VOUT)
2 x L x fS
D x (VIN - VOUT)
fS = 1 MHz,
L = 4.7 PH
,
9.4
(4)
INPUT CAPACITOR
The input capacitor to the switching converter supplies the AC switching current drawn from the switching action
of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied
by the input capacitor is large. The input capacitor must be rated to handle this current:
IRMS_CIN = IOUT
VOUT x (VIN - VOUT)
(A)
VIN
(5)
The power dissipated in the input capacitor is given by:
PD_CIN = I2RMS_CIN x RESR_CIN (W)
(6)
The input capacitor must be rated to handle both the RMS current and the dissipated power. A 22 µF ceramic
capacitor is recommended for the LP5551.
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OUTPUT CAPACITOR
The switching converters in the LP5551 are designed to be used with a 22uF ceramic output capacitor. The
dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. The output capacitor of the
switching converter absorbs the AC ripple current from the inductor and provides the initial response to a load
transient. The ripple voltage at the output of the converter is the product of the ripple current flowing through the
output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by
capacitive, resistive, or inductive elements within the capacitor, depending on the frequency of the ripple current.
Ceramic capacitors are predominately used in portable systems and have very low ESR and remain capacitive
up to high frequencies.
The switcher peak - to - peak output voltage ripple in steady state can be calculated as:
1
VPP = ILPP (RESR +
)
FS x 8 x COUT
(7)
LDO INFORMATION
The LDOs included in the LP5551 provide static supply voltages for various functions in the processor. Use the
following sections to determine loading and external components.
LDO LOADING CAPABILITY
The LDOs in the LP5551 can regulate to a variety of output voltages, depending on the need of the processor.
These voltages can be programmed through the PWI. Table 1 summarizes the parameters of the LP5551 LDOs.
Table 2. LDO Parameters
(1)
(2)
PWI Register
Output voltage
range
Recommended
Maximum Output
Current
Dropout Voltage
(typical)
Typical Load
LDO1
R8
0.6 V – 2.2 V
100 mA
200 mV
PLL
LDO2
R7
1.5 V – 3.3 V
250 mA
150 mV
I/O
LDO3
R2
50 mA
200 mV
Memory/Memory
retention
LDO4
R12
250 mA
150 mV
User defined
VOSW + 0.05 V (1)
0.7 V – 1.35 V (2)
1.5 V – 3.3 V
LDO3 tracks the switching converter output voltage (VOSW) plus a 50 mV offset when the LP5551 is in active state.
LDO3 regulates at the set memory retention voltage when the LP5551 is in shutdown state.
LDO OUTPUT CAPACITOR
The output capacitor sets a low frequency pole and a high frequency zero in the control loop of an LDO. The
capacitance and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet
stability requirements. The LDOs in the LP5551 are designed to be used with ceramic output capacitors. The
dielectric should be X5R, X7R, or comparable material to maintain proper tolerances. Use the following table to
choose a suitable output capacitor:
Table 3. Output Capacitor Selection Guide
32
Output Capacitance Range
(Recommended Typical Value)
ESR range
LDO1
1 µF – 20 µF (2.2 µF)
5 mohm – 500 mohm
LDO2
2 µF – 20 µF (4.7 µF)
5 mohm – 500 mohm
LDO3
0.7 µF – 2.2 µF (1.0 µF)
5 mohm– 500 mohm
LDO4
2 µF – 20 µF (4.7 µF)
5 mohm – 500 mohm
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BOARD LAYOUT CONSIDERATIONS
Shading represents different
layers. (lightest is top layer,
darkest is bottom layer)
GP3
GP2
GND
(can be a mid layer)
GP1
GP0
PWROK
RESETN
EN
GND
SPWI
SCLK
Digital Signals
NC
VO2
VO4
VNWELL
GND
VO1
NC
GND
VPWELL
VO3
NC
NC
NC
FB1
FB2
PGND1
PGND2
PGND1
PGND2
GND
GND
PGND2
SW_DVS
PVDD2
NC
VDD_D
VDD_A
PVDD1
PGND1
SW_AVS
GND
GND
Figure 28. Board Layout Design Recommendations for the LP5551
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
34
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 33
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PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP5551SQ/NOPB
OBSOLETE
WQFN
NJK
36
TBD
Call TI
Call TI
-40 to 125
LP5551SQX/NOPB
OBSOLETE
WQFN
NJK
36
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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17-May-2014
Addendum-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
www.ti.com
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