MC9S08MM32AVLH

Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08MM128 Rev. 3, 10/2010 An Energy-Efficient Solution from Freescale MC9S08MM128 series Covers: MC9S08MM128, and MC9S08MM64, MC9S08MM32, and MC9S08MM32A 64-LQFP 10mm x 10mm 8-Bit HCS08 Central Processor Unit (CPU) – – – Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and 20 MHz CPU above 1.8 V across temperature of -40°C to 105°C HCS08 instruction set with added BGND instruction Support for up to 33 interrupt/reset sources On-Chip Memory – – – 128 K Dual Array Flash read/program/erase over full operating voltage and temperature 12 KB Random-access memory (RAM) Security circuitry to prevent unauthorized access to RAM and Flash – – – Power-Saving Modes – – – Two ultra-low power stop modes. Peripheral clock enable register can disable clocks to unused modules to reduce currents Time of Day (TOD) — Ultra-low power 1/4 sec counter with up to 64s timeout. Ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the TOD. 6 usec typical wake up time from stop3 mode Clock Source Options – – – Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or ceramic resonator dedicated for TOD operation. Oscillator (XOSC2) — for high frequency crystal input for MCG reference to be used for system clock and USB operations. Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports CPU frequencies from 4 kHz to 48 MHz. – – – – System Protection – – – – – Watchdog computer operating properly (COP) reset Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock Low-voltage detection with reset or interrupt; selectable trip points; separate low-voltage warning with optional interrupt; selectable trip points Illegal opcode and illegal address detection with reset Flash block protection for each array to prevent accidental write/erasure Hardware CRC to support fast cyclic redundancy checks – – – – Development Support – – – Single-wire background debug interface Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1 data) Breakpoint capability to allow single breakpoint setting during in-circuit debugging On-chip in-circuit emulator (ICE) debug module containing 3 comparators and 9 trigger modes Peripherals – – CMT— Carrier Modulator timer for remote control communications. Carrier generator, modulator and driver for dedicated infrared out. Can be used as an output compare timer. IIC— Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven 80-LQFP 12mm x 12mm 81-MapBGA 10mm x10mm byte-by-byte data transfer; supports broadcast mode and 11-bit addressing PRACMP — Analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3 SCI — Two serial communications interfaces with optional 13-bit break; option to connect Rx input to PRACMP output on SCI1 and SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge SPI1— Serial peripheral interface (SPI) with 64-bit FIFO buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting SPI2— Serial peripheral interface with full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting TPM — Two 4-channel Timer/PWM Module; Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; external clock input/pulse accumulator USB — Supports USB in full-speed device configuration. On-chip transceiver and 3.3V regulator help save system cost, fully compliant with USB Specification 2.0. Allows control, bulk, interrupt and isochronous transfers. Not available on MC9S08MM32A devices. ADC16 — 16-bit Successive approximation ADC with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mV/C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel select and result registers PDB — Programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for ADC16 module provides periodic coordination of ADC sampling sequence with sequence completion interrupt; Back-to-Back mode and Timed mode DAC — 12-bit resolution; 16-word data buffers with configurable watermark. OPAMP — Two flexible operational amplifiers configurable for general operations; Low offset and temperature drift. TRIAMP — Two trans-impedance amplifiers dedicated for converting current inputs into voltages. Input/Output – – – – Up to 47 GPIOs and 2 output-only pin and 1 input-only pin. Voltage Reference output (VREFO). Dedicated infrared output pin (IRO) with high current sink capability. Up to 16 KBI pins with selectable polarity. Package Options – – – 81-MBGA 10x10 mm 80-LQFP 12x12 mm 64-LQFP 10x10 mm Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Contents 1 Devices in the MC9S08MM128 series. . . . . . . . . . . . . . . . . . . . . 3 1.1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.2 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Pin Assignments by Packages . . . . . . . . . . . . . . . . . . . 10 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . 14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 ESD Protection Characteristics . . . . . . . . . . . . . . . . . . 16 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . 20 2.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.8 12-Bit DAC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.10 MCG and External Oscillator (XOSC) Characteristics .33 2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.11.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.12 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.14 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.15 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .44 2.16 TRIAMP Electrical Parameters . . . . . . . . . . . . . . . . . . .46 2.17 OPAMP Electrical Parameters. . . . . . . . . . . . . . . . . . . .47 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .48 3.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .49 4 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Related Documentation Find the most current versions of all documents at: http://www.freescale.com. Reference Manual —MC9S08MM128RM Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. – 2 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Devices in the MC9S08MM128 series 1 Devices in the MC9S08MM128 series The following table summarizes the feature set available in the MC9S08MM128 series of MCUs. Table 1. MC9S08MM128 series Features by MCU and Package Feature Pin quantity MC9S08MM128 81 64 64 64 131072 65535 32768 32768 RAM size (bytes) 12K 12K 4K 2K FLASH size (bytes) 80 64 MC9S08MM64 MC9S08MM32 MC9S08MM32A Programmable Analog Comparator (PRACMP) yes yes yes yes Debug Module (DBG) yes yes yes yes Multipurpose Clock Generator (MCG) yes yes yes yes Inter-Integrated Communication (IIC) yes yes yes yes Interrupt Request Pin (IRQ) Keyboard Interrupt (KBI) Port I/O 1 yes yes yes 16 yes 16 6 6 6 6 47 46 33 33 33 33 12 12 12 Dedicated Analog Input Pins 12 Power and Ground Pins 8 8 8 8 Time Of Day (TOD) yes yes yes yes Serial Communications (SCI1) yes yes yes yes Serial Communications (SCI2) yes yes yes yes Serial Peripheral Interface 1 (SPI1 (FIFO)) yes yes yes yes Serial Peripheral Interface 2 (SPI2) yes yes yes yes Carrier Modulator Timer pin (IRO) yes yes yes yes TPM input clock pin (TPMCLK) yes yes yes yes TPM1 channels TPM2 channels 4 4 4 2 4 4 4 2 2 2 XOSC1 yes yes yes yes XOSC2 yes yes yes yes USB yes yes yes no Programmable Delay Block (PDB) yes yes yes yes SAR ADC differential channels2 4 4 3 3 3 3 SAR ADC single-ended channels 8 8 6 6 6 6 DAC ouput pin (DACO) yes yes yes yes Voltage reference output pin (VREFO) yes yes yes yes General Purpose OPAMP (OPAMP) yes yes yes yes Trans-Impedance Amplifier (TRIAMP) yes yes yes yes 1 2 Port I/O count does not include two (2) output-only and one (1) input-only pins. Each differential channel is comprised of 2 pin inputs. Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 3 Devices in the MC9S08MM128 series A complete description of the modules included on each device is provided in the following table. Table 2. Versions of On-Chip Modules Module Analog-to-Digital Converter (ADC16) 1 General Purpose Operational Amplifier (OPAMP) 1 Trans-Impedance Operational Amplifier (TRIAMP) 1 Digital to Analog Converter (DAC) 1 Programmable Delay Block 1 Inter-Integrated Circuit (IIC) 3 Central Processing Unit (CPU) 5 On-Chip In-Circuit Debug/Emulator (DBG) 3 Multi-Purpose Clock Generator (MCG) 3 Low Power Oscillator (XOSCVLP) 1 Carrier Modulator Timer (CMT) 1 Programable Analog Comparator (PRACMP) 1 Serial Communications Interface (SCI) 4 Serial Peripheral Interface (SPI) 5 Time of Day (TOD) 1 1 Universal Serial Bus (USB) 1 Version 1 Timer Pulse-Width Modulator (TPM) 3 System Integration Module (SIM) 1 Cyclic Redundancy Check (CRC) 3 Keyboard Interrupt (KBI) 2 Voltage Reference (VREF) 1 Voltage Regulator (VREG) 1 Interrupt Request (IRQ) 3 Flash Wrapper 1 GPIO 2 Port Control 1 USB Module not available on MC9S08MM32A devices. The block diagram in Figure 1 shows the structure of the MC9S08MM128 series MCU. 4 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Devices in the MC9S08MM128 series Figure 1. MC9S08MM128 series Block Diagram Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 5 Devices in the MC9S08MM128 series 1.1 Pin Assignments This section shows the pin assignments for the MC9S08MM128 series devices. 1.1.1 64-Pin LQFP PTA0/SS1 IRO PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1TRIOUT1/DADP2 VINP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2 PTC0/MOSI2 Figure 2. 64-Pin LQFP for MC9S08MM128, VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 OUT2DACO TRIOUT2/DADP3 VINP2 VINN2/DADM3 DADP0 DADM0 VREFO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VINN1/DADM2 INP2- 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF2/TX2/TPM2CH0 PTF1/RX2/TPM2CH1 PTE6/RX2 PTE5/TX2 VDD3 VSS3 PTE4/CMPP3/TPMCLK/IRQ The following two figures show the 64-pin LQFP pinout configuration. The first illustrates the pinout configuration for MC9S08MM128, MC9S08MM64, and MC9S08MM32 devices. MC9S08MM64, and MC9S08MM32 devices For MC9S08MM32A devices, pins 56, 57, 58, and 59 are no connects (NC) as illustrated in the following figure. 6 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. PTA0/SS1 IRO PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1TRIOUT1/DADP2 VINP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2 PTC0/MOSI2 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 OUT2DACO TRIOUT2/DADP3 VINP2 VINN2/DADM3 DADP0 DADM0 VREFO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VINN1/DADM2 INP2- 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 NC NC NC NC PTF2/TX2/TPM2CH0 PTF1/RX2/TPM2CH1 PTE6/RX2 PTE5/TX2 VDD3 VSS3 PTE4/CMPP3/TPMCLK/IRQ Devices in the MC9S08MM128 series Figure 3. 64-Pin LQFP for MC9S08MM32A devices Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 7 Devices in the MC9S08MM128 series 1.1.2 80-Pin LQFP PTA0/SS1 IRO PTA1/KBI1P0/TX1 PTA2/KBI1P1/RX1/ADP4 PTA3/KBI1P2/ADP5 PTA4/INP1+ PTA5 PTA6 PTA7/INP2+ PTB0 PTB1/BLMS VSSA VREFL INP1OUT1- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6 PTE2/KBI2P5 PTE1/KBI2P4 PTE0/KBI2P3 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS PTC7/KBI2P2/CLKOUT/ADP11 PTC6/KBI2P1/PRACMPO/ADP10 PTC5/KBI2P0/CMPP1/ADP9 PTC4/KBI1P7/CMPP0/ADP8 PTC3/KBI1P6/SS2/ADP7 PTC2/KBI1P5/SPSCK2/ADP6 PTC1/MISO2 DADM0 VREFO DADP1 DADM1 VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3 PTB7/KBI1P4 PTC0/MOSI2 DACO TRIOUT2/DADP3 VINP2 VINN2/DADM3 DADP0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 TRIOUT1/DADP2 VINP1 VINN1/DADM2 INP2OUT2- 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTG0/SPSCK1 PTF7/MISO1 PTF6/MOSI1 VDD1 VSS1 VBUS USB_DP USB_DM VUSB33 PTF5/KBI2P7 PTF4/SDA PTF3/SCL PTF2/TX2/TPM2CH0 PTF1/RX2/TPM2CH1 PTF0/TPM2CH2 PTE7/TPM2CH3 PTE6/RX2 PTE5/TX2 VDD3 VSS3 The following figure shows the 80-pin LQFP pinout configuration. Figure 4. 80-Pin LQFP 8 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Devices in the MC9S08MM128 series 1.1.3 81-Pin MAPBGA The following figure shows the 81-pin MAPBGA pinout configuration. 1 2 3 4 5 6 7 8 9 A IRO PTG0 PTF6 USB_DP VBUS VUSB33 PTF4 PTF3 PTE4 B PTF7 PTA0 PTG1 USB_DM PTF5 PTE7 PTF1 PTF0 PTE3 C PTA4 PTA5 PTA6 PTA1 PTF2 PTE6 PTE5 PTE2 PTE1 D INP1- PTA7 PTB0 PTB1 PTA2 PTA3 PTD5 PTD7 PTE0 E OUT1 VINN1 OUT2 VDD2 VDD3 VDD1 PTD2 PTD3 PTD6 F VINP1 TRIOUT1 INP2- VSS2 VSS3 VSS1 PTB7 PTC7 PTD4 G DADP0 DACO TRIOUT2 VINN2 VREFO PTB6 PTC0 PTC1 PTC2 H DADM0 DADM1 DADP1 VINP2 PTC3 PTC4 PTD0 PTC5 PTC6 J VSSA VREFL VREFH VDDA PTB2 PTB3 PTD1 PTB4 PTB5 Figure 5. 81-Pin MAPBGA Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 9 Devices in the MC9S08MM128 series 1.2 Pin Assignments by Packages Table 3. Package Pin Assignments 10 81 MAPBGA 80 LQFP 64 LQFP Package Default Function B2 1 1 PTA0 SS1 — — PTA0/SS1 A1 2 2 IRO — — — IRO C4 3 — PTA1 KBI1P0 TX1 — PTA1/KBI1P0/TX1 D5 4 — PTA2 KBI1P1 RX1 ADP4 PTA2/KBI1P1/RX1/ADP4 D6 5 — PTA3 KBI1P2 ADP5 — PTA3/KBI1P2/ADP5 C1 6 3 PTA4 INP1+ — — PTA4/INP1+ C2 7 4 PTA5 — — — PTA5 C3 8 5 PTA6 — — — PTA6 D2 9 6 PTA7 INP2+ — — PTA7/INP2+ D3 10 7 PTB0 — — — PTB0 D4 11 8 PTB1 BLMS — — PTB1/BLMS J1 12 9 VSSA — — — VSSA J2 13 10 VREFL — — — VREFL D1 14 11 INP1- — — — INP1- E1 15 12 OUT1 — — — OUT1 F2 16 13 DADP2 TRIOUT1 — — DADP2/TRIOUT1 F1 17 14 VINP1 — — — VINP1 E2 18 15 DADM2 VINN1 — — DADM2/VINN1 F3 19 16 INP2- — — — INP2- E3 20 17 OUT2 — — — OUT2 G2 21 18 DACO — — — DACO G3 22 19 DADP3 TRIOUT2 — — DADP3/TRIOUT2 H4 23 20 VINP2 — — — VINP2 G4 24 21 DADM3 VINN2 — — DADM3/VINN2 G1 25 22 DADP0 — — — DADP0 H1 26 23 DADM0 — — — DADM0 G5 27 24 VREFO — — — VREFO H3 28 — DADP1 — — — DADP1 H2 29 — DADM1 — — — DADM1 ALT1 ALT2 ALT3 Composite Pin Name Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Devices in the MC9S08MM128 series Table 3. Package Pin Assignments (Continued) 81 MAPBGA 80 LQFP 64 LQFP Package Default Function J3 30 25 VREFH — — — VREFH J4 31 26 VDDA — — — VDDA F4 32 27 VSS2 — — — VSS2 J5 33 28 PTB2 EXTAL1 — — PTB2/EXTAL1 J6 34 29 PTB3 XTAL1 — — PTB3/XTAL1 E4 35 30 VDD2 — — — VDD2 J8 36 31 PTB4 EXTAL2 — — PTB4/EXTAL2 J9 37 32 PTB5 XTAL2 — — PTB5/XTAL2 G6 38 — PTB6 KBI1P3 — — PTB6/KBI1P3 F7 39 — PTB7 KBI1P4 — — PTB7/KBI1P4 G7 40 33 PTC0 MOSI2 — — PTC0/MOSI2 G8 41 34 PTC1 MISO2 — — PTC1/MISO2 G9 42 35 PTC2 KBI1P5 SPSCK2 ADP6 PTC2/KBI1P5/SPSCK2/ADP6 H5 43 36 PTC3 KBI1P6 SS2 ADP7 PTC3/KBI1P6/SS2/ADP7 H6 44 37 PTC4 KBI1P7 CMPP0 ADP8 PTC4/KBI1P7/CMPP0/ADP8 H8 45 38 PTC5 KBI2P0 CMPP1 ADP9 PTC5/KBI2P0/CMPP1/ADP9 H9 46 39 PTC6 KBI2P1 PRACMPO ADP10 PTC6/KBI2P1/PRACMPO/ADP10 F8 47 40 PTC7 KBI2P2 CLKOUT ADP11 PTC7/KBI2P2/CLKOUT/ADP11 H7 48 41 PTD0 BKGD MS — PTD0/BKGD/MS J7 49 42 PTD1 CMPP2 RESET — PTD1/CMPP2/RESET E7 50 43 PTD2 TPM1CH0 — — PTD2TPM1CH0 E8 51 44 PTD3 TPM1CH1 — — PTD3/TPM1CH1 F9 52 45 PTD4 SDA TPM1CH2 — PTD4/SDA/TPM1CH2 D7 53 46 PTD5 SCL TPM1CH3 — PTD5/SCL/TPM1CH3 E9 54 47 PTD6 TX1 — — PTD6/TX1 D8 55 48 PTD7 RX1 — — PTD7/RX1 D9 56 — PTE0 KBI2P3 — — PTE0/KBI2P3 C9 57 — PTE1 KBI2P4 — — PTE1/KBI2P4 C8 58 — PTE2 KBI2P5 — — PTE2/KBI2P5 B9 59 — PTE3 KBI2P6 — — PTE3/KBI2P6 A9 60 49 PTE4 CMPP3 TPMCLK IRQ PTE4/CMPP3/TPMCLK/IRQ ALT1 ALT2 ALT3 Composite Pin Name Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 11 Devices in the MC9S08MM128 series Table 3. Package Pin Assignments (Continued) 81 MAPBGA 80 LQFP 64 LQFP Package Default Function F5 61 50 VSS3 — — — VSS3 E5 62 51 VDD3 — — — VDD3 C7 63 52 PTE5 TX2 — — PTE5/TX2 C6 64 53 PTE6 RX2 — — PTE6/RX2 B6 65 — PTE7 TPM2CH3 — — PTE7/TPM2CH3 B8 66 — PTF0 TPM2CH2 — — PTF0/TPM2CH2 B7 67 54 PTF1 RX2 TPM2CH1 — PTF1/RX2/TPM2CH1 C5 68 55 PTF2 TX2 TPM2CH0 — PTF2/TX2/TPM2CH0 A8 69 — PTF3 SCL — — PTF3/SCL A7 70 — PTF4 SDA — — PTF4/SDA B5 71 — PTF5 A6 72 56 ALT1 ALT2 ALT3 Composite Pin Name KBI2P7 — — PTF5/KBI2P7 1 — — — VUSB33 2 VUSB33 B4 73 57 USB_DM — — — USB_DM A4 74 58 USB_DP3 — — — USB_DP A5 75 59 VBUS4 — — — VBUS F6 76 60 VSS1 — — — VSS1 E6 77 61 VDD1 — — — VDD1 A3 78 62 PTF6 MOSI1 — — PTF6/MOSI1 B1 79 63 PTF7 MISO1 — — PTF7/MISO1 A2 80 64 PTG0 SPSCK1 — — PTG0/SPSCK1 B3 — — PTG1 — — — PTG1 1 NC on MC9S08MM32A devices. NC on MC9S08MM32A devices. 3 NC on MC9S08MM32A devices. 4 NC on MC9S08MM32A devices. 2 12 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2 Electrical Characteristics This section contains electrical specification tables and reference timing diagrams for the MC9S08MM128/64/32/32A microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for production silicon. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this data sheet supersede any values found in the module specifications. 2.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 4. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 13 Electrical Characteristics 2.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. Table 5. Absolute Maximum Ratings # Rating Symbol Value Unit 1 Supply voltage VDD –0.3 to +3.8 V 2 Maximum current into VDD IDD 120 mA 3 Digital input voltage VIn –0.3 to VDD + 0.3 V 4 Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID  25 mA 5 Storage temperature range Tstg –55 to 150 C 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD). 14 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 6. Thermal Characteristics # Symbol 1 TA 2 TJMAX 3 JA 4 JA Rating Value C Operating temperature range (packaged): MC9S08MM128 –40 to 105 MC9S08MM64 –40 to 105 MC9S08MM32 –40 to 105 MC9S08MM32A –40 to 105 Maximum junction temperature Thermal Thermal resistance1,2,3,4 135 C C/W Single-layer board — 1s 81-pin MBGA 77 80-pin LQFP 55 64-pin LQFP 68 resistance1, 2, 3, 4 Unit C/W Four-layer board — 2s2p 81-pin MBGA 47 80-pin LQFP 40 64-pin LQFP 49 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection 3 1s — Single layer board, one signal layer 4 2s2p — Four layer board, 2 signal and 2 power layers The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD  JA) Eqn. 1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD  VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 15 Electrical Characteristics For most applications, PI/O  Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K  (TJ + 273C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD  (TA + 273C) + JA  (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 2.4 ESD Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E. A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 7. ESD and Latch-up Test Conditions Model Human Body Machine Latch-up Description Symbol Value Unit Series Resistance R1 1500  Storage Capacitance C 100 pF Number of Pulse per pin — 3 — Series Resistance R1 0  Storage Capacitance C 200 pF Number of Pulse per pin — 3 — Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Table 8. ESD and Latch-Up Protection Characteristics # 16 Rating Symbol Min Max Unit C 1 Human Body Model (HBM) VHBM 2000 — V T 2 Machine Model (MM) VMM 200 — V T 3 Charge Device Model (CDM) VCDM 500 — V T 4 Latch-up Current at TA = 125C ILAT 00 — mA T Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2.5 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table 9. DC Characteristics Num Symbol Characteristic 1 VDD Operating Voltage 2 VOH Output high voltage Condition Min Typ1 Max Unit — 1.82 — 3.6 V VDD – 0.5 — — V VDD  2.7 V, ILoad = –10 mA VDD – 0.5 — — V VDD  1.8V, ILoad = –3 mA VDD – 0.5 — — V — — 100 mA — — 0.5 V VDD  2.7 V, ILoad = 10 mA — — 0.5 V VDD  1.8 V, ILoad = 3 mA — — 0.5 V — — — 100 mA all digital inputs, VDD  2.7 V 0.70 x VDD — — V all digital inputs, 2.7 V > VDD  1.8 V 0.85 x VDD — — V C — All I/O pins, low-drive strength VDD  1.8 V, ILoad = –600 A C All I/O pins, high-drive strength 3 IOHT Output high current VOL Output low voltage C Max total IOH for all ports — 4 P D All I/O pins, low-drive strength VDD  1.8 V, ILoad = 600 A C All I/O pins, high-drive strength 5 IOLT Output low current 6 VIH Input high voltage all digital inputs Max total IOL for all ports P C D P P Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 17 Electrical Characteristics Table 9. DC Characteristics (Continued) Num Symbol 7 8 VIL Vhys Input hysteresis |IIn| Input leakage current |IOZ| Typ1 Max Unit all digital inputs, VDD  2.7 V — — 0.35 x VDD V all digital inputs, 2.7  VDD  1.8 V — — 0.30 x VDD V — 0.06 x VDD — — mV all input only VIn = VDD or VSS pins (Per pin) — — 0.5 A all digital VIn = VDD or VSS input/output (per pin) — all digital inputs Hi-Z (off-state) leakage current3 10 RPU Pull-up resistors — RPD Internal pull-down resistors4 — 12 13 Min C Input low voltage all digital inputs 9 11 Condition Characteristic DC injection current 5, 6, 7 IIC P P C P 0.003 0.5 A P 17.5 — 52.5 k 17.5 — 52.5 k P P Single pin limit VSS > VIN > VDD –0.2 — 0.2 mA D Total MCU limit, includes sum of all stressed pins 14 CIn 15 VRAM VSS > VIN > VDD –5 — 5 mA D Input Capacitance, all pins — — — 8 pF C RAM retention voltage — — 0.6 1.0 V C — 0.9 1.4 1.79 V C — 10 — — s D — 2.11 2.16 2.22 V P — 2.16 2.23 2.27 V P — 1.80 1.84 1.88 V P — 1.88 1.93 1.96 V P voltage8 16 VPOR POR re-arm 17 tPOR POR re-arm time VLVDH 9 18 Low-voltage detection threshold — high range VDD falling VDD rising VLVDL 19 Low-voltage detection threshold — low range9 VDD falling VDD rising 18 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 9. DC Characteristics (Continued) Num Symbol 20 Characteristic VLVWH Low-voltage warning threshold — high range9 Condition Min Typ1 Max Unit C — 2.36 2.46 2.56 V P — 2.36 2.46 2.56 V P — 2.11 2.16 2.22 V P — 2.16 2.23 2.27 V P VDD falling VDD rising 21 VLVWL Low-voltage warning threshold — low range9 VDD falling VDD rising 22 Vhys Low-voltage inhibit reset/recover hysteresis10 — — 50 — mV C 23 VBG Bandgap Voltage Reference11 — 1.15 1.17 1.18 V P 1 Typical values are measured at 25C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. 3 Does not include analog module pins. Dedicated analog pins should not be pulled to V DD or VSS and should be left floating when not used to reduce current leakage. 4 Measured with V = V . In DD 5 All functional non-supply pins are internally clamped to V SS and VDD except PTD1. 6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 7 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 8 Maximum is highest voltage that POR is guaranteed. 9 Run at 1 MHz bus frequency 10 Low voltage detection and warning limits measured at 1 MHz bus frequency. 11 Factory trimmed at V DD = 3.0 V, Temp = 25C 2 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 19 Electrical Characteristics 2.6 Supply Current Characteristics Table 10. Supply Current Characteristics # Symbol RIDD 1 Parameter Run supply current Bus Freq VDD (V) 24 MHz 20 MHz 8 MHz 1 MHz RIDD Run supply current 4 20 RIDD Run supply current Run supply current Temp (C) C 3 20 24 mA –40 to 25 P 3 20 24 mA 105 P 3 18 — mA –40 to 105 T 3 8 — mA –40 to 105 T 3 1.8 — mA –40 to 105 T 24 MHz 3 12.3 14.1 mA –40 to 105 C 20 MHz 3 10.5 — mA –40 to 105 T 4.8 — mA –40 to 105 T 1.3 — mA –40 to 105 T 153 222 A –40 to 105 T 143 200 A –40 to 105 T 20 26 A 0 to 70 T 20 70 A –40 to 105 T 1 MHz RIDD Unit FEI mode; all modules OFF3 8 MHz 3 Max FEI mode; all modules ON2 24 MHz 2 Typ1 3 3 LPS=0; all modules OFF3 16 kHz FBILP 3 16 kHz FBELP 3 LPS=1, all modules OFF3 16 kHz FBELP 3 16 kHz FBELP 3 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 10. Supply Current Characteristics (Continued) # Symbol 5 WIDD Parameter Bus Freq 20 MHz 8 MHz 1 MHz LPWIDD S2IDD Max Unit Temp (C) C 3 6.7 — mA –40 to 105 C 3 5.6 — mA –40 to 105 T 3 2.4 — mA –40 to 105 T 3 1 — mA –40 to 105 T 10 40 µA –40 to 105 T 0.39 0.8 µA –40 to 25 P Low-Power Wait mode supply current 16 KHz 7 Typ1 FEI mode, all modules OFF3 Wait mode supply current 24 MHz 6 VDD (V) 3 Stop2 mode supply current4 N/A 3 N/A 3 2.4 4.5 µA 70 C N/A 3 7 11 µA 85 C N/A 3 16 22 µA 105 P 0.2 0.45 µA –40 to 25 C N/A 2 N/A 2 2 3.8 µA 70 C N/A 2 8 12 µA 85 C N/A 2 10 20 µA 105 C Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 21 Electrical Characteristics Table 10. Supply Current Characteristics (Continued) # Symbol S3IDD Bus Freq Parameter Stop3 mode supply current4 VDD (V) Typ1 Max Unit Temp (C) C 0.55 0.9 µA –40 to 25 P No clocks active N/A 8 3 N/A 3 5.5 8.9 µA 70 C N/A 3 14 18 µA 85 C N/A 3 37 42 µA 105 P 2 0.35 0.5 µA –40 to 25 C N/A 2 3.8 6.8 µA 70 C N/A 2 14 20 µA 85 C N/A 2 25 46 µA 105 C N/A 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. ON = System Clock Gating Control registers turn on system clock to the corresponding modules. 3 OFF = System Clock Gating Control registers turn off system clock to the corresponding modules. 4 All digital pins must be configured to a known state to prevent floating pins from adding current. Smaller packages may have some pins that are not bonded out; however, software must still be configured to the largest pin package available so that all pins are in a known state. Otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. NOTE: I/O pins are configured to output low, input-only pins are configured to pullup enabled. IRO pin connects to ground. TRIAMPx, OPAMPx, DACO, and VREFO pins are at reset state and unconnected. 2 Table 11. Typical Stop Mode Adders Temperature (°C) # 1 LPO 2 EREFSTEN 3 IREFSTEN1 4 5 6 22 Parameter Condition — RANGE = HGO = 0 — Units C 250 nA D 850 1000 nA D 80 92 125 µA T –40 25 70 85 105 50 75 100 150 600 650 750 — 73 TOD Does not include clock source current 50 75 100 150 250 nA D PRACMP1 Not using the bandgap (BGBE = 0) 30 35 40 55 75 µA T ADC1 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 190 195 210 220 260 µA T Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 11. Typical Stop Mode Adders (Continued) Temperature (°C) # Parameter DAC1 7 OPAMP1 Condition Units C 410 µA T 52 60 µA T 538 540 540 µA T 67 67 68 70 µA T 430 432 433 438 478 µA T 52 52 52 55 60 µA T –40 25 70 85 105 High-Power mode; no load on DACO 369 377 377 390 Low-Power mode 50 51 51 High-Power mode 453 538 Low-Power mode 56 High-Power mode Low-Power mode 8 TRIAMP1 9 1 Not available in stop2 mode. 2.7 PRACMP Electricals Table 12. PRACMP Electrical Specifications # Characteristic Symbol Min Typical Max Unit C VPWR 1.8 — 3.6 V P 1 Supply voltage 2 Supply current (active) (PRG enabled) IDDACT1 — — 80 A D 3 Supply current (active) (PRG disabled) IDDACT2 — — 40 A D 4 Supply current (ACMP and PRG all disabled) IDDDIS — — 2 nA D 5 Analog input voltage VAIN VSS – 0.3 — VDD V D 6 Analog input offset voltage VAIO — 5 40 mV D 7 Analog comparator hysteresis VH 3.0 — 20.0 mV D 8 Analog input leakage current IALKG — — 1 nA D 9 Analog comparator initialization delay tAINIT — — 1.0 s D 10 Programmable reference generator inputs VIn2 (VDD25) 1.8 — 2.75 V D 11 Programmable reference generator setup delay tPRGST — 1 — µs D 12 Programmable reference generator step size Vstep 0.75 1 1.25 LSB D 13 Programmable reference generator voltage range Vprgout VIn/32 — Vin V P Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 23 Electrical Characteristics 2.8 12-Bit DAC Electricals Table 13. DAC 12LV Operating Requirements # Characteristic Symbol Min Max Unit C 1 Supply voltage VDDA 1.8 3.6 V P 2 Reference voltage VDACR 1.15 3.6 V C 3 Temperature TA –40 105 °C C Output load capacitance CL — 100 pF C — 1 mA C 4 5 Output load current IL Notes A small load capacitance (47 pF) can improve the bandwidth performance of the DAC. Table 14. DAC 12-Bit Operating Behaviors # 24 Characteristic Symbol N Min Typ Max 1 Resolution 2 Supply current low-power mode IDDA_DACLP — 50 100 3 Supply current high-power mode IDDA_DACHP — 345 500 TsFSLP 4 Full-scale Settling time (±1 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) low-power mode TsFSHP 5 Full-scale Settling time (±1 LSB) (0x080 to 0xF7F or 0xF7F to 0x080) high-power mode TsC-CLP 6 Code-to-code Settling time (±1 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) low-power mode TsC-CHP 7 Code-to-code Settling time (±1 LSB) (0xBF8 to 0xC08 or 0xC08 to 0xBF8) high-power mode (3 V at Room Temperature) Vdacoutl 8 DAC output voltage range low (high-power mode, no load, DAC set to 0) (3 V at Room Temperature) 12 — — — — — — — 12 200 30 5 Unit bit µA µA µs µs µs C Notes T T T T T T — 1 — µs T — — 100 mV T • VDDA = 3 V or 2.2 V • VREFSEL = 1 • Temperature = 25°C • VDDA = 3 V or 2.2 V • VREFSEL = 1 • Temperature = 25°C • VDDA = 3 V or 2.2 V • VREFSEL = 1 • Temperature = 25°C • VDDA = 3 V or 2.2 V • VREFSEL = 1 • Temperature = 25°C Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 14. DAC 12-Bit Operating Behaviors (Continued) # Characteristic Symbol DAC output voltage range high (high-power mode, no load, DAC set to 0x0FFF) Vdacouth 9 10 Integral non-linearity error INL 11 Differential non-linearity error VDACR is > 2.4 V DNL Offset error Min Typ Max Unit C VDACR100 — — mV T — — ±8 LSB T — — ±1 LSB T EO 12 — Gain error, VREFH = Vext = VDD ±0.4 ±3 %FSR T Calculated by a best fit curve from VSS + 100mV to VREFH –100mV Calculated by a best fit curve from VSS + 100mV to VREFH –100mV EG 13 14 Power supply rejection ratio VDD  2.4 V 15 Temperature drift of offset voltage (DAC set to 0x0800) Tco 16 Offset aging coefficient Ac PSRR Notes — ±0.1 ± 0.5 %FSR T 60 — — dB T — — 2 mV T — — 8 µV/yr T See Typical Drift figure that follows. Figure 6. Offset at Half Scale vs Temperature Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 25 Electrical Characteristics 2.9 ADC Characteristics Table 15. 16-Bit ADC Operating Conditions Min Typ1 Max Unit C 1.8 — 3.6 V D –100 0 +100 mV D –100 0 +100 mV D VREFH Ref Voltage High 1.15 VDDA VDDA V D 5 VREFL Ref Voltage Low VSSA VSSA VSSA V D 6 VADIN VREFL — VREFH V D 7 CADIN Input Capacitance — 8 4 10 5 pF T 8 RADIN Input Resistance — 2 5 k T # Symb 1 VDDA 2 VDDA 3 VSSA Ground voltage 4 RAS 9 Characteristic Supply voltage Conditions Absolute Delta to VDD (VDD–VDDA)2 Delta to VSS (VSS–VSSA)2 Input Voltage 16-bit modes 8/10/12-bit modes Analog Source Resistance External to MCU Assumes ADLSMP=0 — — 0.5 4 MHz < fADCK < 8 MHz — — 1 fADCK < 4 MHz — — 2 — — 1 4 MHz < fADCK < 8 MHz — — 2 fADCK < 4 MHz — — 5 — — 2 4 MHz < fADCK < 8 MHz — — 5 fADCK < 4 MHz — — 10 — — 5 — — 10 16-bit mode fADCK > 8 MHz 13/12-bit mode fADCK > 8 MHz 11/10-bit mode fADCK > 8 MHz 9/8-bit mode fADCK > 8 MHz fADCK < 8 MHz 26 Comment k T k T k T k T k T k T k T k T k T k T k T Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 15. 16-Bit ADC Operating Conditions (Continued) # Symb 10 fADCK Min Typ1 Max ADLPC=0, ADHSC=1 1.0 — 8.0 ADLPC=0, ADHSC=0 1.0 — 5.0 Characteristic Conditions Unit C MHz D MHz D MHz D Comment ADC Conversion Clock Frequency ADLPC=1, ADHSC=0 1.0 — 2.5 Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 7. ADC Input Impedance Equivalency Diagram Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 27 Electrical Characteristics Table 16. 16-Bit SAR ADC Characteristics full operating range (VREFH = VDDA, > 1.8, VREFL = VSSA  8 MHz, –40 to 85 °C) # Characteristic Supply Current 1 Conditions1 Min Typ2 Max — 215 — — 470 — — 610 — — 0.01 — — 2.4 — — 5.2 — — 6.2 — — — 16 20 48/ –40 56/ –28 13-bit differential mode 12-bit single-ended mode — — 1.5 1.75 3.0 3.5 T 11-bit differential mode 10-bit single-ended mode — — 0.7 0.8 1.5 1.5 T 9-bit differential mode 8-bit single-ended mode — — 0.5 0.5 1.0 1.0 T — — 2.5 2.5 5/–3 +5/–3 13-bit differential mode 12-bit single-ended mode — — 0.7 0.7 1 1 T 11-bit differential mode 10-bit single-ended mode — — 0.5 0.5 0.75 0.75 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T Symb ADLPC=1, ADHSC=0 ADLPC=0, ADHSC=0 IDDAD ADLPC=0, ADHSC=1 2 Supply Current Stop, Reset, Module Off ADLPC=1, ADHSC=0 3 ADC Asynchronous Clock Source ADLPC=0, ADHSC=0 IDDAD fADACK ADLPC=0, ADHSC=1 4 Sample Time See Reference Manual for sample times 5 Conversion Time See Reference Manual for conversion times Total Unadjusted Error 16-bit differential mode 16-bit single-ended mode TUE Unit C Comment A T ADLSMP =0 ADCO=1 A T C MHz LSB3 tADACK = 1/fADACK T 6 7 28 Differential Non-Linearity 16-bit differential mode 16-bit single-ended mode DNL LSB2 32x Hardware Averaging (AVGE = %1 AVGS = %11) T Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 16. 16-Bit SAR ADC Characteristics full operating range (VREFH = VDDA, > 1.8, VREFL = VSSA  8 MHz, –40 to 85 °C) (Continued) # Characteristic 8 Integral Non-Linearity 9 10 11 Zero-Scale Error Full-Scale Error Quantization Error Conditions1 Symb Min Typ2 Max Unit C 16-bit differential mode 16-bit single-ended mode INL — — 6.0 10.0 16.0 20.0 LSB2 T 13-bit differential mode 12-bit single-ended mode — — 1.0 1.0 2.5 2.5 T 11-bit differential mode 10-bit single-ended mode — — 0.5 0.5 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode — — 0.3 0.3 0.5 0.5 T — — 4.0 4.0 +32/ –24 +24/ –16 13-bit differential mode 12-bit single-ended mode — — 0.7 0.7 2.5 2.0 T 11-bit differential mode 10-bit single-ended mode — — 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T — — +10/0 +14/0 +42/–2 +46/–2 13-bit differential mode 12-bit single-ended mode — — 1.0 1.0 3.5 3.5 T 11-bit differential mode 10-bit single-ended mode — — 0.4 0.4 1.5 1.5 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T — –1 to 0 — — — 0.5 12.8 12.7 12.6 12.5 11.9 14.2 13.8 13.6 13.3 12.5 — — — — — 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode 16-bit modes EZS EFS EQ 1.8, VREFL = VSSA  8 MHz, –40 to 85 °C) (Continued) # Characteristic 14 Total Harmonic Distortion Conditions1 16-bit differential mode Avg=32 Symb Spurious Free Dynamic Range Input Leakage Error 16-bit differential mode Avg=32 Max Unit — –91.5 –74.3 dB — –85.5 — 75.0 92.2 — — 86.2 — C Comment C Fin = Fsample/10 0 D SFDR 16-bit single-ended mode Avg=32 all modes Typ2 THD 16-bit single-ended mode Avg=32 15 Min dB C D IIn * RAS EIL mV D mV/× C C mV C 16 17 Temp Sensor Slope m 25C – 125C 18 Temp Sensor Voltage — 1.646 — — 1.769 — — 718.2 — –40C – 25C 25C VTEMP2 Fin = Fsample/10 0 IIn = leakage current (refer to DC characteri stics) 5 1 All accuracy numbers assume the ADC is calibrated with VREFH=VDDA Typical values assume VDDA = 3.0V, Temp = 25C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3 1 LSB = (V N REFH – VREFL)/2 2 30 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 17. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDA,  2.7 V, VREFL = VSSA, fADACK  4 MHz, ADHSC = 1) # Characteristic Total Unadjusted Error Conditions1 Symb Min Typ2 Max Unit C Comment 16-bit differential mode 16-bit single-ended mode TUE — — 16 20 24/ –24 32/–20 LSB3 T 32x Hardware Averaging (AVGE = %1 AVGS = %11) 13-bit differential mode 12-bit single-ended mode — — 1.5 1.75 2.0 2.5 T 11-bit differential mode 10-bit single-ended mode — — 0.7 0.8 1.0 1.25 T 9-bit differential mode 8-bit single-ended mode — — 0.5 0.5 1.0 1.0 T — — 2.5 2.5 3 3 13-bit differential mode 12-bit single-ended mode — — 0.7 0.7 1 1 T 11-bit differential mode 10-bit single-ended mode — — 0.5 0.5 0.75 0.75 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T — — 6.0 10.0 12.0 16.0 13-bit differential mode 12-bit single-ended mode — — 1.0 1.0 2.0 2.0 T 11-bit differential mode 10-bit single-ended mode — — 0.5 0.5 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode — — 0.3 0.3 0.5 0.5 T — — 4.0 4.0 +16/0 +16/-8 13-bit differential mode 12-bit single-ended mode — — 0.7 0.7 2.0 2.0 T 11-bit differential mode 10-bit single-ended mode — — 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T 1 2 3 4 Differential Non-Linearity Integral Non-Linearity Zero-Scale Error 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode 16-bit differential mode 16-bit single-ended mode DNL INL EZS LSB2 LSB2 LSB2 T T T VADIN = VSSA Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 31 Electrical Characteristics Table 17. 16-bit SAR ADC Characteristics full operating range (VREFH = VDDA,  2.7 V, VREFL = VSSA, fADACK  4 MHz, ADHSC = 1) (Continued) # 5 6 Characteristic Conditions1 Symb Min Typ2 Max Unit C Comment Full-Scale Error 16-bit differential mode 16-bit single-ended mode EFS — — +8/0 +12/0 +24/0 +24/0 LSB2 T VADIN = VDDA 13-bit differential mode 12-bit single-ended mode — — 0.7 0.7 2.0 2.5 T 11-bit differential mode 10-bit single-ended mode — — 0.4 0.4 1.0 1.0 T 9-bit differential mode 8-bit single-ended mode — — 0.2 0.2 0.5 0.5 T — –1 to 0 — — — 0.5 14.3 13.8 13.4 13.1 12.4 14.5 14.0 13.7 13.4 12.6 — — — — — Quantization Error 16-bit modes EQ 2.1 V dc — 20 D VDD > 2.4 V dc — D 24 36 2 tLPO Internal low-power oscillator period 700 1000 1300 P s 3 textrst External reset pulse width2 (tcyc = 1/fSelf_reset) 100 — — D ns 4 trstdrv Reset low drive 66 x tcyc — — D ns 5 tMSSU Active background debug mode latch setup time 500 — — D ns 6 tMSH Active background debug mode latch hold time 100 — — D ns 7 tILIH, tIHIL IRQ pulse width • Asynchronous path2 • Synchronous path3 100 1.5 x tcyc — — 8 tILIH, tIHIL KBIPx pulse width • Asynchronous path2 • Synchronous path3 100 1.5 x tcyc — — D ns D ns Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Table 20. Control Timing # Symbol 9 tRise, tFall Parameter Min Typical1 Max C Port rise and fall time (load = 50 pF)4, Low Drive Unit ns Slew rate control disabled (PTxSE = 0) — 11 — D Slew rate control enabled (PTxSE = 1) — 35 — D Slew rate control disabled (PTxSE = 0) — 40 — D Slew rate control enabled (PTxSE = 1) — 75 — D Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40 C to 105 C. 1 2 textrst RESET PIN Figure 8. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 9. IRQ/KBIPx Timing Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 37 Electrical Characteristics 2.11.2 TPM Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 21. TPM Input Timing # C Function Symbol Min Max Unit 1 — External clock frequency fTPMext dc fBus/4 MHz 2 — External clock period tTPMext 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTPMext tclkh TPMxCLK tclkl Figure 10. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure 11. Timer Input Capture Pulse 38 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2.12 SPI Characteristics Table 22 and Figure 12 through Figure 15 describe the timing requirements for the SPI system. Table 22. SPI Timing No.1 Characteristic2 Symbol Operating frequency Unit C fBus/2048 0 fBus/2 fBus/4 Hz Hz D 2 4 2048 — tcyc tcyc D 12 1 — — tSPSCK tcyc D 12 1 — — tSPSCK tcyc D tcyc –30 tcyc – 30 1024 tcyc — ns ns D 15 15 — — ns ns D 0 25 — — ns ns D ta — 1 tcyc D tdis — 1 tcyc D — — 25 25 ns ns D 0 0 — — ns ns D Master Slave SPSCK period tSPSCK 2 Master Slave Enable lead time tLead 3 Master Slave Enable lag time tLag 4 Master Slave Clock (SPSCK) high or low time 5 tWSPSCK Master Slave Data setup time (inputs) 6 Master Slave Data hold time (inputs) 7 9 Max fop 1 8 Min Master Slave Slave access time3 Slave MISO disable time 4 Data valid (after SPSCK edge) 10 tSU tSU tHI tHI tv Master Slave Data hold time (outputs) 11 tHO Master Slave Rise time 12 Input Output tRI tRO — — tcyc – 25 25 ns ns D Input Output tFI tFO — — tcyc – 25 25 ns ns D Fall time 13 1 Numbers in this column identify elements in Figure 12 through Figure 15. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. 2 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 39 Electrical Characteristics SS1 (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 11 MOSI (OUTPUT) LSB IN 11 MSB OUT2 12 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 12. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 2 2 SCK (CPOL = 0) (OUTPUT) 3 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN(2) 11 MOSI (OUTPUT) BIT 6 . . . 1 LSB IN 12 MSB OUT(2) BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 13. SPI Master Timing (CPHA = 1) 40 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics SS (INPUT) 3 2 SCK (CPOL = 0) (INPUT) 5 4 2 SCK (CPOL = 1) (INPUT) 5 4 8 MISO (OUTPUT) 12 11 BIT 6 . . . 1 MSB OUT SLAVE SLAVE LSB OUT SEE NOTE 7 6 MOSI (INPUT) 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined, but normally MSB of character just received Figure 14. SPI Slave Timing (CPHA = 0) SS (INPUT) 2 3 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 11 MISO (OUTPUT) SEE NOTE 8 MOSI (INPUT) SLAVE 12 MSB OUT 6 BIT 6 . . . 1 9 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined, but normally LSB of character just received Figure 15. SPI Slave Timing (CPHA = 1) Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 41 Electrical Characteristics 2.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the Flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory chapter in the Reference Manual for this device (MC9S08MM128RM). Table 23. Flash Characteristics # Characteristic Symbol Min Typical Max Unit 3.6 V C 1 Supply voltage for program/erase –40C to 105C Vprog/erase 1.8 2 Supply voltage for read operation VRead 1.8 — 3.6 V D 3 Internal FCLK frequency1 fFCLK 150 — 200 kHz D 4 Internal FCLK period (1/FCLK) tFcyc 5 — 6.67 s D 5 Byte program time (random location) 2 2 — D tprog 9 tFcyc P tBurst 4 tFcyc P 6 Byte program time (burst mode) 7 Page erase time2 tPage 4000 tFcyc P 8 2 tMass 20,000 tFcyc P Mass erase time endurance3 9 Program/erase TL to TH = –40C to + 105C T = 25C 10 Data retention4 tD_ret 10,000 — — 100,000 — — cycles C 15 100 — years C 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 42 Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2.14 USB Electricals The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require additional information, this space would be used to communicate that information. Table 24. Internal USB 3.3 V Voltage Regulator Characteristics # Characteristic Symbol Min Typ Max Unit C 1 Regulator operating voltage Vregin 3.9 — 5.5 V C 2 VREG output Vregout 3 3.3 3.75 V P 3 VUSB33 input with internal VREG disabled Vusb33in 3 3.3 3.6 V C 4 VREG Quiescent Current IVRQ — 0.5 — mA C Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 43 Electrical Characteristics 2.15 VREF Electrical Specifications Table 25. VREF Electrical Specifications # 1 2 Characteristic Symbol Min Max Unit C VDDA 1.80 3.6 V C 1 Supply voltage 2 Temperature TA –40 105 °C C 3 Output Load Capacitance CL — 100 nf D 4 Maximum Load — — 10 mA — 5 Voltage Reference Output with Factory Trim. VDD = 3 V at 25°C. Vout 1.140 1.160 V P 6 Temperature Drift (Vmin – Vmax across the full temperature range) Tdrift — 25 mV1 T 7 Aging Coefficient2 Ac — 60 µV/year C 8 Powered down Current (Off Mode, VREFEN=0, VRSTEN=0) I — 0.10 µA C 9 Bandgap only (MODE_LV[1:0] = 00) I — 75 µA T 10 Low-Power buffer (MODE_LV[1:0] = 01) I — 125 µA T 11 Tight-Regulation buffer (MODE_LV[1:0] = 10) I — 1.1 mA T 12 Load Regulation MODE_LV = 10 — — 100 µV/mA C DC 70 — dB C 13 Line Regulation MODE = 1:0, Tight Regulation VDD < 2.3 V, Delta VDDA = 100 mV, VREFH = 1.2 V driven externally with VREFO disabled. (Power Supply Rejection) See typical chart that follows (Figure 16). Linear reliability model (1008 hours stress at 125°C = 10 years operating life) used to calculate Aging µV/year. Vrefo data recorded per month. Table 26. VREF Limited Range Operating Behaviors 1 44 # Characteristic Symbol Min Max Unit C Voltage Reference Output with Factory Trim (Temperature range from 0° C to 50° C) Vout 1.149 1.152 mV T 1 Temperature Drift (Vmin – Vmax Temperature range from 0° C to 50° C) Tdrift — 3 mV1 T 2 Notes See typical chart that follows (Figure 16). Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics Figure 16. Typical VREF Output vs. Temperature Figure 17. Typical VREF Output vs. VDD Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 45 Electrical Characteristics 2.16 TRIAMP Electrical Parameters Table 27. TRIAMP Characteristics 1.8–3.6 V, –40°C~105°C Characteristic1 # 1 2 46 Symbol Min Typ2 Max Unit C VDD 1.8 — 3.6 V C 1 Operating Voltage 2 Supply Current (IOUT=0mA, CL=0) Low-power mode ISUPPLY — 52 60 A T 3 Supply Current (IOUT=0mA, CL=0) High-speed mode ISUPPLY — 432 480 A T 4 Input Offset Voltage VOS — ±1 ±5 mV T 5 Input Offset Voltage Temperature Drift VOS — 600 — V T 6 Input Offset Current IOS — ±120 500 pA T 7 Input Bias Current (0 ~ 50°C) IBIAS — < 350 < ±500 pA T 8 Input Bias Current (–40 ~ 105°C) IBIAS — 3 6.55 nA T 9 Input Common Mode Voltage Low VCML 0 — — V T 10 Input Common Mode Voltage High VCMH — — VDD–1.4 V T 11 Input Resistance RIN 500 — — M T 12 Input Capacitances CIN — — 5 pF D 13 AC Input Impedance (fIN=100kHz) |XIN| — 1 — M D 14 Input Common Mode Rejection Ratio CMRR 60 70 — dB T 15 Power Supply Rejection Ration PSRR 60 70 — dB T 16 Slew Rate (VIN=100mV) Low-power mode SR — 0.1 — V/s T 17 Slew Rate (VIN=100mV) High-speed mode SR — 1 — V/s T 18 Unity Gain Bandwidth (Low-power mode) 50pF GBW 0.15 0.25 — MHz T 19 Unity Gain Bandwidth (High-speed mode) 50pF GBW — 1.6 — MHz T 20 DC Open Loop Voltage Gain AV — 80 — dB T 21 Load Capacitance Driving Capability CL(max) — — 100 pF T 22 Output Impedance AC Open Loop (@100 kHz Low-power mode) ROUT — 1.4 — k D 23 Output Impedance AC Open Loop (@100 kHz High-speed mode) ROUT — 184 —  D 24 Output Voltage Range triout 0.15 — VDD – 0.15 V T 25 Output Drive Capability IOUT — ± 1.0 — mA T 26 Gain Margin GM 20 — — dB D 27 Phase Margin PM 45 55 — deg T 28 Input Voltage Noise Density f= 1 kHz — 160 — nV/Hz T All parameters are measured at 3.0 V, CL= 47 pF across temperature –40 to + 105 °C unless specified. Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Electrical Characteristics 2.17 OPAMP Electrical Parameters Table 28. OPAMP Characteristics 1.8–3.6 V Characteristics1 # Symbol Min Typ2 Max Unit C VDD 1.8 — 3.6 V C 1 Operating Voltage 2 Supply Current (IOUT=0mA, CL=0 Low-Power mode) ISUPPLY — 67 80 A T 3 Supply Current (IOUT=0mA, CL=0 High-Speed mode) ISUPPLY — 538 550 A T 4 Input Offset Voltage VOS — 2 6 mV T 5 Input Offset Voltage Temperature Coefficient VOS — 10 — V/C T 6 Input Offset Current (–40°C to 105°C) IOS — 2.5 250 nA T 7 Input Offset Current (–40°C to 50°C) IOS — — 45 nA T 8 Positive Input Bias Current (–40°C to 105°C) IBIAS — 0.8 3.5 nA T 9 Positive Input Bias Current (–40°C to 50°C) IBIAS — — 2 nA T 10 Negative Input Bias Current (–40°C to 105°C) IBIAS — 2.5 250 nA T 11 Negative Input Bias Current (–40°C to 50°C) IBIAS — — 45 nA T 12 Input Common Mode Voltage Low VCML 0.1 — — V T 13 Input Common Mode Voltage High VCMH — — VDD V T 14 Input Resistance RIN — 500 — M T 15 Input Capacitances CIN — — 10 pF D 16 AC Input Impedance (fIN=100kHz Negative Channel) |XIN| — 52 — 17 AC Input Impedance (fIN=100kHz Positive Channel) |XIN| — 132 — 18 Input Common Mode Rejection Ratio CMRR 55 65 — dB T 19 Power Supply Rejection Ratio PSRR 60 65 — dB T 20 Slew Rate (VIN=100mV Low-Power mode) SR 0.1 — — V/s T 21 Slew Rate (VIN=100mV High-Speed mode) SR 1 — — V/s T 22 Unity Gain Bandwidth (Low-Power mode) GBW 0.2 — — MHz T 23 Unity Gain Bandwidth (High-Speed mode) GBW 1 — — MHz T 24 DC Open Loop Voltage Gain AV 80 90 — dB T 25 Load Capacitance Driving Capability CL(max) — — 100 pF T 26 Output Impedance AC Open Loop (@100 kHz Low-Power mode) ROUT — 4k —  D 27 Output Impedance AC Open Loop (@100 kHz High-Speed mode) ROUT — 220 —  D Output Voltage Range VOUT 0.15 — VDD–0.1 5 V 29 Output Drive Capability IOUT 0.5 1.0 — mA T 30 Gain Margin GM 20 — — dB D 31 Phase Margin PM 45 55 — deg T 28 k k D D T Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 47 Ordering Information Table 28. OPAMP Characteristics 1.8–3.6 V (Continued) 1 2 # Characteristics1 Symbol Min Typ2 Max GPAMP startup time (Low-Power mode) (Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF, RL = 100k) Tstartup — 4 — 32 GPAMP startup time (Low-Power mode) (Tolerance < 1%, Vin = 0.5 Vp–p, CL = 25 pF, RL = 100k) Tstartup 33 34 Input Voltage Noise Density f=1 kHz Unit C T uS — 1 — T uS — 250 — nV/Hz T All parameters are measured at 3.3 V, CL =4 7 pF across temperature –40 to + 105°C unless specified. Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. 3 Ordering Information This appendix contains ordering information for the device numbering system. MC9S08MM128 and MC9S08MM64 devices. 3.1 Device Numbering System Example of the device numbering system: MC 9 S08 MM 128 V XX Status (MC = Fully Qualified) Package designator (see Table 30) Temperature range (V = –40C to 105C) (C = –40C to 85C) Memory (9 = Flash-based) Core Approximate Flash size in Kbytes Family Table 29. Device Numbering System Memory Device Number1 MC9S08MM128 1 2 48 Available Packages2 Flash RAM 131,072 12,288 64 LQFP 131,072 12,288 80 LQFP 131,072 12,288 81 MAPBGA MC9S08MM64 65,536 12,288 64 LQFP MC9S08MM32 32768 4096 64 LQFP MC9S08MM32A 32768 2048 64 LQFP See Table 2 for a complete description of modules included on each device. See Table 30 for package information. Freescale Semiconductor Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Revision History 3.2 Package Information Table 30. Package Descriptions Pin Count 64 Package Type Low Quad Flat Package 80 Low Quad Flat Package 81 MAPBGA Package 3.3 Abbreviation Designator Case No. Document No. LQFP LH 840F-02 98ASS23234W 98ASS23174W 98ASA10670D LQFP LK 917-01 Map PBGA MB 1662-01 Mechanical Drawings Table 30 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08MM128 series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 30, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 30) in the “Enter Keyword” search box at the top of the page. 4 Revision History Table 31. Revision History Rev Date Description of Changes 0 06/2009 Initial release of the Data Sheet. 1 07/2009 Updated MCG and XOSC Average internal reference frequency. 2 01/2010 Revised to include MC9S08MM32 and MC9S08MM32A devices.Updated electrical characteristic data. 3 10/2010 Updated with the latest characteristic data. Added several figures. Added the ADCTypical Operation table. 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