MCZ33287EGR2

Freescale Semiconductor Technical Data Document Number: MC33287 Rev. 5.0, 2/2007 Contact Monitoring and Dual Low-Side Protected Driver 33287 The 33287 interfaces between switch contacts and a microcontroller. Eight switch-to-battery (or switch-to-ground) sense monitor switch status. Additionally, two internal low-side switches are available to control inductive or capacitive loads. The 33287 has eight sense inputs (rated at 40 V) with thresholds ratiometric to VBAT. One sense input has a dedicated output for direct interfacing to the MCU and the remaining seven inputs are multiplexed interfaced to the MCU. AUTOMOTIVE CONTACT MONITORING AND DUAL LOW-SIDE PROTECTED DRIVER The two low-side switch outputs are current limited to 535 mA and internally clamped to 50 V. Outputs also have independent overtemperature shutdown and diagnostic reporting. DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42343B 20-PIN SOICW Features • • • • Eight High-Voltage Sense Inputs Direct Interfacing to Microcontroller Two Current Limited Low-Side Drivers Drivers Internally Overvoltage Clamped and Thermally Protected • 55 µA Standby Current • Pb-Free Packaging Designated by Suffix Code EG ORDERING INFORMATION Device Temperature Range (TA) Package -40 to 125°C 20 SOICW MC33287DW/R2 MCZ33287EG/R2 GND Sense 5.0 V 33287 VBAT VDD1 VDD2 VDD IN0 IN1 8 Sense to GND or VBAT Inputs IN2 AD0 IN3 AD1 IN4 AD2 IN5 OUT1 IN6 OUT7 IN7 CD1 OUTD1 CD2 OUTD2 GND VBAT Sense Figure 1. Simplified Application Design Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2007. All rights reserved. MCU INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM IN0 VDD1 AD2 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VDD2 Internal Supply Multiplexer 8 to 1 and Diagnostic Logic DIAGD1 OUT7 DIAGD2 OUT1 AD1 AD0 OUTD1 Fault Detector Fault Detector Overtemperature Overtemperature Detection Detection VDD2 Control Control Current Limitation GND OUTD2 Current Limitation CD1 CD2 Figure 2. 33287 Simplified Internal Block Diagram 33287 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VDD1 1 20 VDD2 IN3 2 19 IN4 IN2 3 18 IN5 IN1 4 17 IN6 IN0 5 16 IN7 AD0 6 15 OUT7 AD1 7 14 OUT1 AD2 8 13 CD1 OUTD1 9 12 CD2 10 11 OUTD2 GND Figure 3. 33287 Pin Connections Table 1. 33287 Pin Definitions Pin Number Pin Name Formal Name Definition These are high-voltage power supply 5.0 V pins (VBAT). 1, 20 VDD1, VDD2 Voltage Power 5, 4, 3, 2, 19, 18, 17, 16 IN0 – IN7 Input 0 – 7 6, 7, 8 AD0 – AD2 Address 9, 11 OUTD1, OUTD2 Output Drain 10 GND Ground 12, 13 CD1, CD2 Command Driver 14 OUT1 Output 1 This is the output (multiplexed Output 1 = 0 to 6.0 V for IN0 to IN6 and DIAGD1 or DIAGD2) and DIAGD2 pins. 15 OUT7 Output 7 This is the direct output from IN7 pin. These are high-voltage input pins. These pins are the addresses for mode and input selection. These two are output driver pins (drain). This pin in the ground for the logic and analog circuitry of the device. These are the two driver command pins. 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Power Supply Voltage Value VDD1 V Normal Operation (Steady-State) 24 Load Dump Conditions 40 Logic Supply Voltage (Continuous) Input Pin Voltage (1) Unit VDD2 7.0 V VIN 40 V ESD Voltage (2) V Human Body Model VESD1 Machine Model VESD2 ±200 TA -40 to 125°C °C TSTG -65 to 150 °C PD 0.7 W TPPRT Note 4. °C RθJ-A 100 °C/W Operating Ambient Temperature Storage Temperature Power Dissipation (TA = 85°C) Peak Package Reflow Temperature During Reflow Thermal Resistance Junction-to-Ambient (3) (4) , ±2000 Notes 1 With Serial Resistor ≥ 25 kΩ 2 ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 3. 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33287 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 7.0 V ≤ VDD1 ≤ 18 V, 4.75 V ≤ VDD2 ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Extended limit is 5.0 V ≤ VDD1 ≤ 7.0 V and other parameters are full specification in this mode. Inputs IN1–IN7 and lowside drivers are still functional with down-graded characteristics. Characteristic Symbol Min Typ Max Full Specification 7.0 12 18 Extend Limit 5.0 — 7.0 VDD2 4.75 — — VDD1 ≤ 14 V IVDD1-0 — 55 110 VCD1 = VDD2, VCD2 = 0 V IVDD2-0 — — 10 Unit SUPPLY VOLTAGE (VDD1 AND VDD2 PINS) Operational Supply Voltage V VDD1 Operational Supply Voltage (Full Specification) (5) Supply Current Standby Mode Supply Current in Drivers on Configuration (Full Specification) V µA (5) µA VCD1 = 0 V IVDD1-1 — 250 1500 VCD2 = VDD2 IVDD2-1 — 650 1500 Output Resistance (Full Specification and TJ ≤ 130°C) RDS(ON) — 1.40 3.20 Ω Output Resistance (Extent Limit and TJ ≤ 130°C) RDS(ON) — — 5.0 Ω ILEAK 1.0 — 13 µs OUTPUT DRIVERS CHARACTERISTICS (OUTD1 AND OUTD2 PINS) Leakage Current (Internal Current Source) PROTECTION AND LEVEL DETECTION (OUTD1 AND OUTD2 PINS) Positive Output Clamp VCLAMP 40 50 60 V ILIM 300 535 750 mA Output Fault Detector Level VFAULT 2.0 2.75 3.5 V Overtemperature Detection (at 25°C by Function Simulation) TDETEC 145 160 175 °C VIL — — 4.0 x VDD2 V Output Current Limitation (130°C ≥ TJ) INPUTS (CD1 AND CD2 PINS) Input Voltage Low Input Voltage High VIH 8.0 x VDD2 — — V Hysteresis VHST 500 800 — mV Input Current on Pin CD1 (Internal Pull-Up and CD1 Connected to Ground) ICD1 -100 -30 -10 µA Leakage Current on Pin CD1 (Internal Pull-Up Connected to VDD2) ILEAK -5.0 — 5.0 µA Input Current on Pin CD2 (Internal Pull Down CD2 Connected to VDD2) ICD2 10 30 100 µA Leakage Current on Pin CD2 (Internal Pull-Up CD1 Connected to Ground) ILEAK -5.0 — 5.0 µA Notes 5 All INn and ADn inputs are connected to ground. 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 7.0 V ≤ VDD1 ≤ 18 V, 4.75 V ≤ VDD2 ≤ 5.25 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Extended limit is 5.0 V ≤ VDD1 ≤ 7.0 V and other parameters are full specification in this mode. Inputs IN1–IN7 and lowside drivers are still functional with down-graded characteristics. Characteristic Symbol Min Typ Max Unit Input Voltage Low (Full Specification) VIL — — 4.0 x VDD1 V Input Voltage Low (Extended Limit) VIL — — 3.0 x VDD1 V Input Voltage High (Full Specification and Extended Limit) VIH 7.0 x VDD1 — — V Hysteresis (5.0 V < VDD1 < 16 V) VHYS 5.0 1.0 — V Input Current (VIN < 16 V) ILEAK 5.0 — 5.0 µA VINCLAMP 17 20 23 V Input Voltage Low VIL — — 4.0 x VDD2 V Input Voltage High VIH 8.0 x VDD2 — — V Hysteresis VHYS 500 750 — mV Input Current ILEAK -5.0 — 5.0 µA INPUTS (IN0 TO IN7 PINS) Input Voltage Clamp (I = 100 µA) INPUTS (AD0, AD1, AND AD2 PINS) OUTPUTS (OUT1 AND OUT7 PINS) Output Voltage Low (ILOAD = 2.0 mA) VOL — — 2.0 x VDD2 V Output Voltage High (ILOAD = -2.0 mA) VOH 8.0 x VDD2 — — V 33287 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit Turn ON Delay Time tON — 1.3 10 µs Turn OFF Delay Time tOFF — 2.1 10 µs Output Rising Edge tRISE — 2.8 10 µs Output Falling Edge tFALL — 1.0 10 µs Difference Between Command Duration and Bit Duration ∆BIT -5.0 — 5.0 µs OUTPUT DRIVERS CHARACTERISTICS (OUTD1 AND OUTD2 PINS) 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CD2 t tCOMMAND OUTD2 ∆Bit = tCOMMAND- tBIT 80% 80% 50% 50% tBIT 20% 20% tON tOFF tFALL tRISE t Figure 4. Timing Characteristics VBAT CD1 R1 = 500 Ω C1 = 2.0 nF R2 = 47 kΩ C2 = 250 pF OUTD1 VBAT R1 = 500 Ω CD2 f = 5.0 kHz C1 = 2.0 nF OUTD2 R2 = 47 kΩ C2 = 250 pF Figure 5. Timing Test Configuration 33287 8 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 5. Drivers Function Table CD1 (6) DIAGD1 (8) OUTD1 Status High Level for Logic Signals High Level for Drivers Outputs High Level for Logic Signals Driver 1 Normally OFF Low Level for Logic Signals Low Level for Drivers Outputs High Level for Logic Signals Driver 1 Normally ON High Level for Logic Signals Low Level for Drivers Outputs Low Level for Logic Signals Driver 1 Shorted to GND or Open Load Low Level for Logic Signals High Level for Drivers Outputs Low Level for Logic Signals Driver 1 Overloaded CD2 (7) OUTD2 DIAGD2 Status Low Level for Logic Signals High Level for Drivers Outputs High Level for Logic Signals Driver 2 Normally OFF High Level for Logic Signals Low Level for Drivers Outputs High Level for Logic Signals Driver 2 Normally ON Low Level for Logic Signals Low Level for Drivers Outputs Low Level for Logic Signals Driver 2 Shorted to GND or Open Load High Level for Logic Signals High Level for Drivers Outputs Low Level for Logic Signals Driver 2 Overloaded Notes 6 CD1 is active on low level (driver 1 is on when CD1 is low). 7 CD2 is active on high level (driver 2 is on when CD2 is high. 8 DIAGD1 output is neither latched nor filtered. Table 6. Eight-to-One Data Multiplexer Function Inputs OUT1 AD2 AD1 AD0 High Impedance High Impedance High Impedance Unknown Low Level Low Level Low Level IN0(9) Low Level Low Level High Level IN1 Low Level High Level Low Level IN2 Low Level High Level High Level IN3 High Level Low Level Low Level IN4 High Level Low Level High Level IN5 High Level High Level Low Level IN6 High Level High Level High Level DIAGD1 or DIAGD2(10) Notes 9 IN0 to IN6 are the normalized values. 10 DIAGD1 or DIAGD2 are the values of the selected internal fault detector. See Table 7. 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 7. Fault Detector Selection Inputs OUT1 AD2 AD1 AD0 Unknown Unknown Unknown Unknown Unknown Low Level High Level Unknown High Level High Level High Level DIAGD1 Unknown Unknown Unknown Unknown Unknown High Level Low Level Unknown High Level High Level High Level DIAGD2 33287 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS TYPICAL APPLICATIONS 8 contacts to Vbat or GND 5V Regulator VDD Vbat 1 VDD1 2 IN3 IN4 1 9 3 IN2 IN5 1 8 4 IN1 IN6 1 7 5 IN0 IN7 1 6 6 AD0 OUT7 1 5 7 AD1 OUTi 1 4 8 AD2 CD1 1 3 9 D1 CD2 1 2 D2 1 1 VDD2 20 I/O PORT 470nF MICROCONTROLLER Relay Relay (65Ω) Lamp (1,2W) Resistor 10 GND Lamp Figure 6. Typical Application Configuration VBAT VBAT 47 kΩ 500 Ω 500 Ω 47 kΩ 10 nF 10 nF Contact to GND Contact to VBAT Figure 7. Contact Configuration 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 VALIM AD2 OUT7 AD1 8 TO 1 LOGIC MULTIPLEXER OUTi AD0 VDD2 All the symbols represented without supply pin are connected to VDD2 NQ Q R S DIAGD1 VDD1 VDD2 DIAGD2 VALIM VALIM OUTD2 GND S CD2 Q VALIM R + - VDD2 OUTD2 Driver CD1 OUTD1 Driver OUTD1 NOTE: The only difference between the low side driver 1 and 2 is the polarity of the command. Also, there is an integral pull-up at pin CD1, and an internal pull-down at pin CD2. Figure 8. Electrical Schematic 33287 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGE PACKAGE DIMENSIONS PACKAGE PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42343B REV. J 33287 Analog Integrated Circuit Device Data Freescale Semiconductor 13 REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 4.0 11/2006 • • • • • Converted to Freescale format with the current form and style Implemented Revision History page Updated Package Drawing 98ASB42343B to Rev. J Added EG Pb-FREE suffix Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com. 5.0 2/2007 • • • • • • Corrected Internal Block Diagram on page 2 Restated Definition for OUT1 in 33287 Pin Definitions on page 3 Corrected value for Storage Temperature on page 4 Corrected unit for Output Resistance (Extent Limit and TJ ≤ 130°C) on page 5 Corrected Electrical Schematic on page 12 Restated note 4 in Maximum Ratings on page 4. 33287 14 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. 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