UJA1163A
Mini high-speed CAN system basis chip with Standby mode
Rev. 1 — 23 August 2019
Product data sheet
1. General description
The UJA1163A is a mini high-speed CAN System Basis Chip (SBC) containing an ISO
11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver and an
integrated 5 V/100 mA supply for a microcontroller. The UJA1163A can be operated in
very-low-current Standby mode with bus wake-up capability and supports ISO 11898-6
compliant autonomous CAN biasing.
This implementation enables reliable communication in the CAN FD fast phase at data
rates up to 5 Mbit/s.
2. Features and benefits
2.1 General
ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant high-speed CAN
transceiver
Hardware and software compatible with the UJA116x product family and with improved
EMC performance
Loop delay symmetry timing enables reliable communication at data rates up to
5 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC TS 62228 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
UJA1163A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
2.3 Low-drop voltage regulator for 5 V microcontroller supply (V1)
5 V nominal output; 2 % accuracy
100 mA output current capability
Current limiting above 150 mA
On-resistance of 5 (max)
Support for microcontroller RAM retention down to a battery voltage of 2 V
Undervoltage reset at 90 % of nominal value
Excellent transient response with a 4.7 F ceramic output capacitor
Short-circuit to GND/overload protection on pin V1
2.4 Power Management
Standby mode featuring very low supply current; voltage V1 remains active to maintain
the supply to the microcontroller
Remote wake-up capability via standard CAN wake-up pattern
2.5 System control and diagnostic features
Mode control via pin STBN
Overtemperature shutdown
Bidirectional reset pin
3. Ordering information
Table 1.
Ordering information
Type number
UJA1163ATK
UJA1163A
Product data sheet
Package
Name
Description
Version
HVSON14
plastic thermal enhanced very thin small outline package; no
leads; 14 terminals; body 3 4.5 0.85 mm
SOT1086-2
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Mini high-speed CAN system basis chip with Standby mode
4. Block diagram
UJA1163A
5
10
BAT
RXD
TXD
CTS
STBN
5 V MICROCONTROLLER SUPPLY (V1)
3
RSTN
V1
4
13
HS-CAN
1
12
6
CANH
CANL
CAN TRANSCEIVER STATUS
14
MODE CONTROL
2
aaa-022897
GND
Fig 1.
Block diagram of UJA1163A
5. Pinning information
5.1 Pinning
terminal 1
index area
TXD
1
14 STBN
GND
2
13 CANH
V1
3
12 CANL
RXD
4
RSTN
5
10 BAT
CTS
6
9
i.c.
i.c.
7
8
i.c.
UJA1163A
11 i.c.
aaa-022898
Transparent top view
Fig 2.
UJA1163A
Product data sheet
Pin configuration diagram
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Mini high-speed CAN system basis chip with Standby mode
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
TXD
1
transmit data input
GND
2[1]
ground
V1
3
5 V microcontroller supply voltage
RXD
4
receive data output; reads out data from the bus lines
RSTN
5
reset input/output
CTS
6
CAN transceiver status output
i.c.
7
internally connected; should be left floating or connected to GND
i.c.
8
internally connected; should be left floating or connected to GND
i.c.
9
internally connected; should be left floating or connected to GND
BAT
10
battery supply voltage
i.c.
11
internally connected; should be left floating or connected to GND
CANL
12
LOW-level CAN bus line
CANH
13
HIGH-level CAN bus line
STBN
14
standby control input (active LOW)
[1]
The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
SBC via the printed circuit board. For enhanced thermal and electrical performance, it is recommended to
solder the exposed die pad to GND.
6. Functional description
6.1 System controller
The system controller controls the internal functions of the UJA1163A.
6.1.1 Operating modes
The system controller contains a state machine that supports five operating modes:
Normal, Standby, Reset, Overtemp and Off. The state transitions are illustrated in
Figure 3.
6.1.1.1
Normal mode
Normal mode is the active operating mode. In this mode, all the hardware on the device is
available and can be activated (see Table 3). Voltage regulator V1 is enabled to supply the
microcontroller.
The CAN interface can be configured to be active and thus to support normal CAN
communication.
Normal mode can be selected from Standby mode by setting pin STBN HIGH. Pending
wake-up events (power-on, CAN bus wake-up) are cleared when the UJA1163A enters
Normal mode.
UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
6.1.1.2
Standby mode
Standby mode is the power saving mode of the UJA1163A, offering reduced current
consumption. The transceiver is unable to transmit or receive data in Standby mode. V1
remains active.
The receiver monitors bus activity for a wake-up request. The bus pins are biased to GND
(via Ri(cm)) when the bus is inactive for t > tto(silence) and at approximately 2.5 V when there
is activity on the bus (autonomous biasing).
Pin RXD is forced LOW when a wake-up event is detected on the CAN bus.
The UJA1163A switches to Standby mode via Reset mode:
• from Off mode if the battery voltage rises above the power-on detection threshold
(Vth(det)pon)
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
Standby mode can also be selected from Normal by setting pin STBN LOW.
STBN = HIGH
NORMAL
STANDBY
STBN = LOW
RSTN = HIGH
any reset event
V1 undervoltage
no overtemperature
RESET
OVERTEMP
power-on
overtemperature event
OFF
VBAT undervoltage
from any mode
015aaa295
from any mode except Off
Fig 3.
UJA1163A system controller state diagram
UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
6.1.1.3
Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. V1 and
overtemperature detection are active.
The UJA1163A switches to Reset mode from any mode in response to a reset event.
The UJA1163A exits Reset mode:
• and switches to Standby mode if pin RSTN is released HIGH
• if the SBC is forced into Off or Overtemp mode
If a V1 undervoltage event forced the transition to Reset mode, the UJA1163A will remain
in Reset mode until the voltage on pin V1 has recovered.
6.1.1.4
Off mode
The UJA1163A switches to Off mode when the battery is first connected or from any mode
when VBAT < Vth(det)poff. Only power-on detection is enabled; all other modules are
inactive. The UJA1163A starts to boot up when the battery voltage rises above the
power-on detection threshold Vth(det)pon (triggering an initialization process) and switches
to Reset mode after tstartup. Pin RXD is driven LOW when the UJA1163A switches from Off
mode to Standby mode, to indicate a power-on event has occurred.
In Off mode, the CAN pins disengage from the bus (zero load; high-ohmic).
6.1.1.5
Overtemp mode
Overtemp mode is provided to prevent the UJA1163A being damaged by excessive
temperatures. The UJA1163A switches immediately to Overtemp mode from any mode
(other than Off mode) when the global chip temperature rises above the overtemperature
protection activation threshold, Tth(act)otp.
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off and pin RSTN is driven LOW.
The UJA1163A exits Overtemp mode:
• and switches to Reset mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
• if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
6.1.1.6
Table 3.
Block
Hardware characterization for the UJA1163A operating modes
Hardware characterization by functional block
Operating mode
Off
Standby
Normal
Reset
Overtemp
V1
off[1]
on
on
on
off
RSTN
LOW
HIGH
HIGH
LOW
LOW
CAN
off
Offline
Active
Offline
off
RXD
V1 level
V1 level/LOW if
wake-up detected
CAN bit stream
V1 level/LOW if
wake-up detected
V1 level/LOW if
wake-up detected
[1]
When the SBC switches from Reset, Standby or Normal mode to Off mode, V1 behaves as a current source during power down while
VBAT is between 3 V and 2V.
6.1.2 Mode control via pin STBN
The UJA1163A can be switched between Normal and Standby modes via the STBN
control input (see Figure 3). When STBN goes LOW, the UJA1163A switches to Standby
mode. When STBN goes HIGH, the UJA1163A switches to Normal mode.
6.2 System reset
When a system reset occurs, the SBC switches to Reset mode and initiates a process
that generates a low-level pulse on pin RSTN.
6.2.1 Characteristics of pin RSTN
Pin RSTN is a bidirectional open drain low side driver with integrated pull-up resistance,
as shown in Figure 4. With this configuration, the SBC can detect the pin being pulled
down externally, e.g. by the microcontroller. The input reset pulse width must be at least
tw(rst).
V1
RSTN
015aaa276
Fig 4.
RSTN internal pin configuration
6.2.2 Output reset pulse width
The SBC distinguishes between a cold start and a warm start. A cold start is performed on
start-up if the reset event was combined with a V1 undervoltage event (power-on reset,
overtemperature reset, V1 undervoltage before entering or while in Reset mode). The cold
start output reset pulse width (tw(rst)) is between 20 ms and 25 ms.
If the reset event was triggered externally (by pulling RSTN LOW), the output reset pulse
is between 1 ms and 1.5 ms. This is called warm start of the microcontroller.
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Mini high-speed CAN system basis chip with Standby mode
6.2.3 Reset sources
The following events will cause the UJA1163A to switch to Reset mode:
•
•
•
•
VV1 drops below the 90 % undervoltage threshold
pin RSTN is pulled down externally
the SBC leaves Off mode
the SBC leaves Overtemp mode
6.3 Global temperature protection
The temperature of the UJA1163A is monitored continuously, except in Off mode. The
SBC switches to Overtemp mode if the temperature exceeds the overtemperature
protection activation threshold, Tth(act)otp. In addition, pin RSTN is driven LOW and V1 and
the CAN transceiver are switched off. When the temperature drops below the
overtemperature protection release threshold, Tth(rel)otp, the SBC switches to Standby
mode via Reset mode.
6.4 Power supplies
6.4.1 Battery supply voltage (VBAT)
The internal circuitry is supplied from the battery via pin BAT. The device needs to be
protected against negative supply voltages, e.g. by using an external series diode. If VBAT
falls below the power-off detection threshold, Vth(det)poff, the SBC switches to Off mode.
However, the microcontroller supply voltage (V1) remains active until VBAT falls below 2 V.
The SBC switches from Off mode to Reset mode tstartup after the battery voltage rises
above the power-on detection threshold, Vth(det)pon. A power-on event is indicated by a
LOW level on pin RXD. RXD remains LOW from the moment UJA1163A exits Off mode
until it switches to Normal mode.
6.4.2 Low-drop voltage supply for 5 V microcontroller (V1)
V1 is intended to supply the microcontroller and the internal CAN transceiver and delivers
up to 150 mA at 5 V. The output voltage on V1 is monitored. A system reset is generated
if the voltage on V1 drops below the 90 % undervoltage threshold (90 % of the nominal V1
output voltage).
The internal CAN transceiver consumes 50 mA (max) when the bus is continuously
dominant, leaving 100 mA available for the external load on pin V1. In practice, the typical
current consumption of the CAN transceiver is lower (25 mA), depending on the
application, leaving more current available for the load.
6.5 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2:2016 compliant. The CAN transmitter is
supplied from V1. The UJA1163A includes additional timing parameters on loop delay
symmetry to ensure reliable communication in fast phase at data rates up to 5 Mbit/s, as
used in CAN FD networks.
UJA1163A
Product data sheet
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UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
The CAN transceiver supports autonomous CAN biasing, which helps to minimize RF
emissions. CANH and CANL are always biased to 2.5 V when the UJA1163A is in Normal
mode. Autonomous biasing is active when the UJA1163A is in Standby mode and the
CAN transceiver is in CAN Offline mode - to 2.5 V if there is activity on the bus (CAN
Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence) (CAN
Offline mode).
This is useful when the node is disabled due to a malfunction in the microcontroller. The
SBC ensures that the CAN bus is correctly biased to avoid disturbing ongoing
communication between other nodes. The autonomous CAN bias voltage is derived
directly from VBAT.
6.5.1 CAN operating modes
The integrated CAN transceiver supports three operating modes: Active, Offline and
Offline Bias (see Figure 6). The CAN transceiver operating mode depends on the
UJA1163A operating mode and the output voltage on V1.
6.5.1.1
CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
The CAN transceiver is in Active mode when:
• the UJA1163A is in Normal mode (STBN = 1) AND
• the voltage on pin V1 is above the 90 % threshold
If pin TXD is LOW when the transceiver switches to CAN Active mode (UJA1163A in
Normal mode), the transmitter and receiver will remain disabled until TXD goes HIGH.
This prevents network traffic being blocked for tto(dom)TXD (i.e. while the TXD dominant
time-out timer is running; see Section 6.7.1) every time the transceiver enters Active
mode, if the TXD pin is clamped permanently LOW.
In CAN Active mode, the CAN bias voltage is derived from V1.
6.5.1.2
CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event. CANH
and CANL are biased to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN
bus is biased to 2.5 V. This mode is activated automatically when activity is detected on
the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to
CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than tto(silence).
The CAN transceiver switches to CAN Offline mode from CAN Active mode if:
• the SBC switches to Reset or Standby mode
provided the CAN-bus has been inactive for at least tto(silence). If the CAN-bus has been
inactive for less than tto(silence), the CAN transceiver switches first to CAN Offline Bias
mode and then to CAN Offline mode once the bus has been silent for tto(silence).
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Mini high-speed CAN system basis chip with Standby mode
The CAN transceiver switches to CAN Offline Bias mode from CAN Active mode if the
voltage on V1 drops below the 90 % undervoltage threshold.
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode if no activity is detected on the bus (no CAN edges) for
t > tto(silence) OR
• when the SBC switches from Off or Overtemp mode to Reset mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
• a standard wake-up pattern is detected on the CAN bus OR
• the SBC is in Normal mode with VV1 < 90 %
6.5.1.3
CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the SBC switches to Off or Overtemp mode OR
• VBAT falls below the CAN receiver undervoltage detection threshold, Vuvd(CAN)
It will be switched on again on entering CAN Offline mode when VBAT rises above the
undervoltage recovery threshold (Vuvr(CAN)) and the SBC is no longer in Off/Overtemp
mode. CAN Off mode prevents reverse currents flowing from the bus when the battery
supply to the SBC is lost.
6.5.2 CAN standard wake-up
The UJA1163A monitors the bus for a wake-up pattern when the CAN transceiver is in
Offline mode.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up
filter and trigger a wake-up event (see Figure 5; note that additional pulses may occur
between the recessive/dominant phases). The recessive and dominant phases must last
at least twake(busrec) and twake(busdom), respectively.
Pin RXD is driven LOW when a valid CAN wake-up pattern is detected on the bus.
CANH
VO(dif)
CANL
twake(busdom)
twake(busrec)
twake(busdom)
RXD
≤ tto(wake)bus
aaa-021858
Fig 5.
CAN wake-up timing
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Mini high-speed CAN system basis chip with Standby mode
CAN Active
transmitter: on
RXD: bitstream
CANH/CANL: terminated
to V1/2 (≈2.5 V)
[t < tsilence &
(Reset OR Standby)] OR
VV1 < 90 %
t > tsilence &
(Reset OR Standby)
Normal &VV1 > 90 %(1)
CAN Offline Bias
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: terminated
to 2.5 V (from VBAT)
Normal & VV1 > 90 %(1)
wake-up OR
(Normal &
VV1 < 90 %)
from all modes
t > tsilence &
(Reset OR Standby)
Off OR
Overtemp OR
VBAT < Vuvd(CAN)
CAN Offline
CAN Off
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: terminated
to GND
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: floating
leaving
Off/Overtemp
015aaa298
(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode if pin
TXD is held LOW (e.g. by a short-circuit to GND)
Fig 6.
CAN transceiver state machine
6.6 CAN transceiver status pin (CTS)
Pin CTS is driven HIGH to indicate to microcontroller that the transceiver is fully enabled
and data can be transmitted and received via the TXD/RXD pins.
Pin CTS is actively driven LOW:
• while the transceiver is starting up (e.g. during a transition from Standby to Normal) or
• if pin TXD is clamped LOW for t > tto(dom)TXD or
• if an undervoltage is detected on V1
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6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 4.4 kbit/s.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
6.7.3 Pull-down on STBN pin
Pin STBN has an internal pull-down (to GND) to ensure the UJA1163A switches to
Standby mode if STBN is left floating.
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
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7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
voltage on pin
Vx
Conditions
x[1]
V(CANH-CANL)
voltage between pin
CANH and pin CANL
Vtrt
transient voltage
Min
Max
Unit
pin V1
[2]
0.2
+6
V
pins TXD, RXD, RSTN, CTS, STBN
[3]
0.2
VV1 + 0.2 V
pin BAT
0.2
+40
V
pins CANH and CANL with respect to any other pin
58
+58
V
40
+40
V
pulse 1
100
-
V
pulse 2a
-
75
V
pulse 3a
150
-
V
-
100
V
6
+6
kV
on pins CANL, CANH, WAKE, BAT
[4]
pulse 3b
VESD
electrostatic discharge
voltage
IEC 61000-4-2 (150 pF, 330 ) discharge circuit
[5]
on pins CANH and CANL; pin BAT with capacitor
Human Body Model (HBM)
on any pin
[6]
2
+2
kV
on pin BAT
[7]
4
+4
kV
on pins CANH, CANL
[8]
8
+8
kV
100
+100
V
on corner pins
750
+750
V
on any other pin
500
+500
V
40
+150
C
55
+150
C
Machine Model (MM)
[9]
on any pin
Charged Device Model (CDM)
Tvj
virtual junction
temperature
Tstg
storage temperature
[10]
[11]
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2]
When the device is not powered up, IV1 (max) = 25 mA.
[3]
Maximum voltage should never exceed 6 V.
[4]
Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2.
[5]
Verified by an external test house according to IEC TS 62228, Section 4.3.
[6]
According to AEC-Q100-002.
[7]
Pins stressed to reference group containing all grounds, emulating the application circuit (Figure 10). HBM pulse as specified in
AEC-Q100-002 used.
[8]
Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (Figure 10). HBM pulse as
specified in AEC-Q100-002 used.
[9]
According to AEC-Q100-003.
[10] According to AEC-Q100-011.
[11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
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8. Thermal characteristics
Table 5.
Symbol
Rth(vj-a)
[1]
Thermal characteristics
Parameter
Conditions
[1]
thermal resistance from virtual junction to ambient
Typ
Unit
60
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
9. Static characteristics
Table 6.
Static characteristics
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
Vth(det)pon
power-on detection threshold
voltage
VBAT rising
4.2
-
4.55
V
Vth(det)poff
power-off detection threshold
voltage
VBAT falling
2.8
-
3
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
VBAT rising
4.5
-
5
V
Vuvd(CAN)
CAN undervoltage detection
voltage
VBAT falling
4.2
-
4.55
V
IBAT
battery supply current
Normal mode; MC = 111;
CAN Active mode
-
4
7.5
mA
CAN recessive; VTXD = VV1
-
46
67
mA
Standby mode; IV1 = 0 A;
40 C < Tvj < 85 C;
VBAT = 7 V to 18 V
CAN dominant; VTXD = 0 V
-
[2]
91
A
VBAT = 5.5 V to 28 V; VTXD = VV1;
IV1 = 120 mA to 0 mA
4.9
5
5.1
V
VBAT = 5.65 V to 28 V; VTXD = VV1;
IV1 = 150 mA to 0 mA
4.9
5
5.1
V
VBAT = 5.65 V to 28 V;
IV1 = 100 mA to 0 mA;
VTXD = 0 V; VCANH = 0 V
4.9
5
5.1
V
-
-
Voltage source: pin V1
VO
Vret(RAM)
output voltage
RAM retention voltage difference VBAT = 2 V to 3 V; IV1 = 2 mA
100
mV
10
mV
-
5
VBAT = 2 V to 3 V; IV1 = 200 A
R(BAT-V1)
resistance between pin BAT and
pin V1
VBAT = 4 V to 6 V; IV1 = 120 mA;
Tvj < 150 C
VBAT = 3 V to 4 V; IV1 = 40 mA
-
2.625
-
Vuvd
undervoltage detection voltage
Vuvd(nom) = 90 %
4.5
-
4.75
V
Vuvr
undervoltage recovery voltage
4.5
-
4.75
V
IO(sc)
short-circuit output current
300
-
150
mA
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Mini high-speed CAN system basis chip with Standby mode
Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
ICAN(int)V1
internal CAN supply current from Normal mode; CAN Active mode;
V1
CAN dominant; VTXD = 0 V;
short-circuit on bus lines;
3 V < (VCANH = VCANL) < +18 V
Min
Typ
Max
Unit
-
-
59
mA
Standby mode control input; pin STBN
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Rpd
pull-down resistance
40
80
60
k
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VV1 -
-
V
Rpu
pull-up resistance
40
60
80
k
CAN transmitter status; pin CTS
IOH
HIGH-level output current
VCTS = VV1 0.4 V; transmitter on
-
-
4
mA
IOL
LOW-level output current
VCTS = 0.4 V; transmitter off
4
-
-
mA
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VV1
0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
Rpu
pull-up resistance
CAN Offline mode
40
60
80
k
pin CANH; RL = 50 to 65
2.75
3.5
4.5
V
pin CANL; RL = 50 to 65
0.5
1.5
2.25
V
400
-
+400
mV
0.9VV1
-
1.1VV1
V
RL = 50 to 65
1.5
-
3
V
RL = 45 to 70
1.4
-
3.3
V
RL = 2240
1.5
-
5
V
CAN Active/Offline Bias mode;
VTXD = VIO
50
-
+50
mV
CAN Offline mode
0.2
-
+0.2
V
High-speed CAN bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
CAN Active mode; VTXD = 0 V;
VV1 = 4.5 V to 5.5 V; t < tto(dom)TXD
Vdom(TX)sym
transmitter dominant voltage
symmetry
Vdom(TX)sym = VV1 VCANH VCANL;
VV1 = 5 V
VTXsym
transmitter voltage symmetry
VTXsym = VCANH + VCANL;
fTXD = 250 kHz, 1 MHz or 2.5 MHz;
CSPLIT = 4.7 nF
VO(dif)
differential output voltage
[3]
[4]
CAN Active mode (dominant);
VTXD = 0 V; VBAT > 5.5 V;
t < tto(dom)TXD
recessive; RL = no load;
VBAT > 5.5 V
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Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
VO(rec)
recessive output voltage
CAN Active mode; VTXD = VV1
RL = no load
2
0.5VV1 3
V
CAN Offline mode;
RL = no load
0.1
-
+0.1
V
CAN Offline Bias mode;
RL = no load
2
2.5
3
V
pin CANH;
VCANH = 3 V to +27 V
55
-
-
mA
pin CANL;
VCANL = 15 V to +18 V
-
-
+55
mA
3
-
+3
mA
IO(sc)dom
dominant short-circuit output
current
recessive short-circuit output
current
VCANL = VCANH = 27 V to +32 V;
VTXD = VV1
Vth(RX)dif
differential receiver threshold
voltage
12 V VCANL +12 V;
12 V VCANH +12 V
Vdom(RX)
Unit
CAN Active mode;
VBAT > 5.5 V; VTXD = 0 V
IO(sc)rec
Vrec(RX)
Max
CAN Active mode
0.5
0.7
0.9
V
CAN Offline mode
0.4
0.7
1.15
V
CAN Active mode
4[3]
-
+0.5
V
CAN Offline/Offline Bias modes
4[3]
-
+0.4
V
CAN Active mode
0.9
-
9.0[3]
V
CAN Offline/Offline Bias modes
1.15
-
9.0[3]
V
12 V VCANL +12 V;
12 V VCANH +12 V
receiver recessive voltage
12 V VCANL +12 V;
12 V VCANH +12 V
receiver dominant voltage
Vhys(RX)dif
differential receiver hysteresis
voltage
CAN Active mode;
12 V VCANL +12 V;
12 V VCANH +12 V
1
30
60
mV
Ri
input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
9
15
28
k
Ri
input resistance deviation
V VCANL +5 V;
V VCANH +5 V
1
-
+1
%
Ri(dif)
differential input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
19
30
52
k
Ci(cm)
common-mode input capacitance
[3]
-
-
20
pF
Ci(dif)
differential input capacitance
[3]
-
-
10
pF
IL
leakage current
5
-
+5
A
167
177
187
C
VBAT = VV1 = 0 V or VBAT = VV1 =
shorted to ground via 47 k;
VCANH = VCANL = 5 V
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold temperature
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Mini high-speed CAN system basis chip with Standby mode
Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Tth(rel)otp
overtemperature protection
release threshold temperature
Min
Typ
Max
Unit
127
137
147
C
0
-
0.2VV1
V
60
80
k
Reset output; pin RSTN
VOL
LOW-level output voltage
Rpu
pull-up resistance
40
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VV1 -
-
[1]
VV1 = 1.0 V to 5.5 V; pull-up resistor
to VV1 900
V
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 7.
[3]
Not tested in production; guaranteed by design.
[4]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 12.
aaa-034539
100
IBAT
(μA)
80
(1)
60
40
20
0
-50
-25
0
25
50
75
Tvj (°C)
100
(1) Standby Mode: CAN Offline mode, VBAT = 12 V, IV1 = 0 A.
Fig 7.
UJA1163A typical Standby quiescent current (A)
UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ Max
Unit
from VBAT exceeding the power-on
detection threshold until VV1 exceeds
the 90 % undervoltage threshold;
CV1 = 4.7 F
-
2.8
4.7
ms
6
-
54
s
-
-
63
s
Voltage source; pin V1
tstartup
start-up time
td(uvd)
undervoltage detection delay time
td(uvd-RSTNL)
delay time from undervoltage
detection to RSTN LOW
undervoltage on V1
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXD-busdom)
delay time from TXD to bus
dominant
[2]
-
80
-
ns
td(TXD-busrec)
delay time from TXD to bus
recessive
[2]
-
80
-
ns
td(busdom-RXD)
delay time from bus dominant to
RXD
[2]
-
105 -
ns
td(busrec-RXD)
delay time from bus recessive to
RXD
[2]
-
120 -
ns
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
tbit(TXD) = 200 ns
[3]
-
-
255
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD
HIGH
tbit(TXD) = 200 ns
[3]
-
-
255
ns
tbit(bus)
transmitted recessive bit width
tbit(TXD) = 500 ns
[4]
435
-
530
ns
tbit(TXD) = 200 ns
[4]
155
-
210
ns
tbit(TXD) = 500 ns
[4]
400
-
550
ns
tbit(TXD) = 200 ns
[4]
120
-
220
ns
tbit(TXD) = 500 ns
65
-
+40
ns
tbit(TXD) = 200 ns
45
-
+15
ns
first pulse (after first recessive) for
wake-up on pins CANH and CANL;
CAN Offline mode
0.5
-
1.8
s
second pulse for wake-up on pins
CANH and CANL
0.5
-
1.8
s
first pulse for wake-up on pins CANH
and CANL;
CAN Offline mode
0.5
-
1.8
s
second pulse (after first dominant) for
wake-up on pins CANH and CANL
0.5
-
1.8
s
between first and second dominant
pulses; CAN Offline mode
0.8
-
10
ms
-
tbit(RXD)
trec
twake(busdom)
twake(busrec)
bit time on pin RXD
receiver timing symmetry
bus dominant wake-up time
bus recessive wake-up time
tto(wake)bus
bus wake-up time-out time
tto(dom)TXD
TXD dominant time-out time
CAN Active mode; VTXD = 0 V
2.7
tto(silence)
bus silence time-out time
recessive time measurement started in
all CAN modes
0.95 -
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Product data sheet
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3.3
ms
1.17
s
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Mini high-speed CAN system basis chip with Standby mode
Table 7.
Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
td(busact-bias)
delay time from bus active to bias
tstartup(CAN)
CAN start-up time
Min
Typ Max
Unit
-
-
200
s
-
-
220
s
cold start
20
-
25
ms
warm start
1
-
1.5
ms
input pulse width
18
-
-
s
delay before CAN transceiver is
activated after the UJA1163A enters
Normal mode
-
-
320
s
when switching to Active mode
(CTS = HIGH)
Pin RSTN: reset pulse width
tw(rst)
reset pulse width
output pulse width
Mode transition
td(act)norm
[1]
normal mode activation delay time
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 8 and Figure 11.
[3]
See Figure 9 and Figure 11.
[4]
See Figure 9.
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Mini high-speed CAN system basis chip with Standby mode
HIGH
70 %
TXD
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
HIGH
70 %
RXD
30 %
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
aaa-029311
Fig 8.
CAN transceiver timing diagram
70 %
TXD
30 %
30 %
td(TXDL-RXDL)
5 x tbit(TXD)
tbit(TXD)
0.9 V
VO(dif)
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Fig 9.
UJA1163A
Product data sheet
CAN FD timing definitions according to ISO 11898-2:2016
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Mini high-speed CAN system basis chip with Standby mode
11. Application information
11.1 Application diagram
BAT
22 μF
(1)
44 μF
BAT
V1
10
3
5
RSTN
RSTN
VCC
MICROCONTROLLER
6
UJA1163A
GND
14
2
4
13
12
CANH
RT (2)
1
CTS
STBN
RXD
TXD
standard
μC port
RXD
TXD
VSS
CANL
RT (2)
e.g.
4.7 nF
aaa-022899
(1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 6.8 F).
(2) For bus line end nodes, RT = 60 in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’
termination of e.g. RT = 1.3 k can be used, if required by the OEM.
Fig 10. Typical application using the UJA1163A
11.2 Application hints
Further information on the application of the UJA1163A can be found in the NXP
application hints document AH1902 Application Hints - Mini high speed CAN system basis
chips UJA116xA.
UJA1163A
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Mini high-speed CAN system basis chip with Standby mode
12. Test information
TXD
CANH
RL
60 Ω
RXD
CL
100 pF
CANL
15 pF
aaa-030850
Fig 11. Timing test circuit for CAN transceiver
TXD
CANH
30 Ω
fTXD
CSPLIT
4.7 nF
RXD
30 Ω
CANL
aaa-030851
Fig 12. Test circuit for measuring transceiver driver symmetry
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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Mini high-speed CAN system basis chip with Standby mode
13. Package outline
HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
B
D
A
A
E
A1
c
terminal 1
index area
detail X
e1
terminal 1
index area
e
v
w
b
1
7
C
C A B
C
y1 C
y
L
k
Eh
14
8
Dh
0
2.5
Dimensions
Unit
mm
5 mm
scale
A
A1
b
max 1.00 0.05 0.35
nom 0.85 0.03 0.32
min 0.80 0.00 0.29
c
D
Dh
E
Eh
0.2
4.6
4.5
4.4
4.25
4.20
4.15
3.1
3.0
2.9
e
e1
1.65
1.60 0.65
1.55
3.9
k
L
0.35 0.45
0.30 0.40
0.25 0.35
v
0.1
w
y
0.05 0.05
y1
0.1
sot1086-2
References
Outline
version
IEC
JEDEC
JEITA
SOT1086-2
---
MO-229
---
European
projection
Issue date
10-07-14
10-07-15
Fig 13. Package outline SOT1086-2 (HVSON14)
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14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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Mini high-speed CAN system basis chip with Standby mode
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 14) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 9.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 14.
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Mini high-speed CAN system basis chip with Standby mode
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 14. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Soldering of HVSON packages
Section 15 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
UJA1163A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
26 of 32
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
17. Appendix: ISO 11898-2:201x parameter cross-reference list
Table 10.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
VO(rec)
recessive output voltage
Differential output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
Dominant state differential input voltage range
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
Ri
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
tRec
trec
receiver timing symmetry
UJA1163A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
27 of 32
UJA1163A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
Table 10.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
tFilter
twake(busdom)[1] bus dominant wake-up time
HS-PMA bus biasing control timings
CAN activity filter time, long
twake(busrec)[1]
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Timeout for bus inactivity
tSilence
tto(silence)
bus silence time-out time
Bus Bias reaction time
tBias
td(busact-bias)
delay time from bus active to bias
CAN activity filter time, short
Wake-up timeout, short
Wake-up timeout, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
UJA1163A
Product data sheet
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Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
18. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UJA1163A v.1
20190823
Product data sheet
-
-
UJA1163A
Product data sheet
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Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
UJA1163A
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
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UJA1163A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
UJA1163A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
31 of 32
UJA1163A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode
21. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
6.1.2
6.2
6.2.1
6.2.2
6.2.3
6.3
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.1.1
6.5.1.2
6.5.1.3
6.5.2
6.6
6.7
6.7.1
6.7.2
6.7.3
6.7.4
7
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Designed for automotive applications. . . . . . . . 1
Low-drop voltage regulator for 5 V microcontroller
supply (V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Power Management . . . . . . . . . . . . . . . . . . . . . 2
System control and diagnostic features . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
System controller . . . . . . . . . . . . . . . . . . . . . . . 4
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 4
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware characterization for the UJA1163A
operating modes . . . . . . . . . . . . . . . . . . . . . . . . 7
Mode control via pin STBN . . . . . . . . . . . . . . . . 7
System reset. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Characteristics of pin RSTN . . . . . . . . . . . . . . . 7
Output reset pulse width . . . . . . . . . . . . . . . . . . 7
Reset sources. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Global temperature protection . . . . . . . . . . . . . 8
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8
Battery supply voltage (VBAT) . . . . . . . . . . . . . . 8
Low-drop voltage supply for 5 V microcontroller
(V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
High-speed CAN transceiver . . . . . . . . . . . . . . 8
CAN operating modes . . . . . . . . . . . . . . . . . . . 9
CAN Active mode . . . . . . . . . . . . . . . . . . . . . . . 9
CAN Offline and Offline Bias modes. . . . . . . . . 9
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 10
CAN standard wake-up . . . . . . . . . . . . . . . . . 10
CAN transceiver status pin (CTS). . . . . . . . . . 11
CAN fail-safe features . . . . . . . . . . . . . . . . . . 12
TXD dominant timeout . . . . . . . . . . . . . . . . . . 12
Pull-up on TXD pin . . . . . . . . . . . . . . . . . . . . . 12
Pull-down on STBN pin . . . . . . . . . . . . . . . . . 12
Loss of power at pin BAT . . . . . . . . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
8
9
10
11
11.1
11.2
12
12.1
13
14
15
15.1
15.2
15.3
15.4
16
17
18
19
19.1
19.2
19.3
19.4
20
21
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . .
Application hints. . . . . . . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages. . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering of HVSON packages . . . . . . . . . . .
Appendix: ISO 11898-2:201x parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
18
21
21
21
22
22
23
24
24
24
24
24
25
26
27
29
30
30
30
30
31
31
32
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2019
Document identifier: UJA1163A
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