UJA1164A
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Rev. 1 — 23 August 2019
Product data sheet
1. General description
The UJA1164A is a mini high-speed CAN System Basis Chip (SBC) containing an ISO
11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant HS-CAN transceiver and an
integrated 5 V/100 mA supply for a microcontroller. It also features a watchdog and a
Serial Peripheral Interface (SPI). The UJA1164A can be operated in very-low-current
Standby mode with bus wake-up capability and supports 11898-2:2016 compliant
autonomous CAN biasing.
This implementation enables reliable communication in the CAN FD fast phase at data
rates up to 5 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC to
be adapted for use in a specific application. This makes it possible to configure the
power-on behavior of the UJA1164A to meet the requirements of different applications.
2. Features and benefits
2.1 General
ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant high-speed CAN
transceiver
Hardware and software compatible with the UJA116x product family and with improved
EMC performance
Loop delay symmetry timing enables reliable communication at data rates up to
5 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC TS 62228 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability
UJA1164A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Low-drop voltage regulator for 5 V microcontroller supply (V1)
5 V nominal output; 2 % accuracy
100 mA output current capability
Current limiting above 150 mA
On-resistance of 5 (max)
Support for microcontroller RAM retention down to a battery voltage of 2 V
Undervoltage reset with selectable detection thresholds: 60 %, 70 %, 80 % or 90 % of
output voltage
Excellent transient response with a 4.7 F ceramic output capacitor
Short-circuit to GND/overload protection on pin V1
2.4 Power Management
Standby mode featuring very low supply current; voltage V1 remains active to maintain
the supply to the microcontroller
Remote wake-up capability via standard CAN wake-up pattern
Wake-up source recognition
Remote wake-up can be disabled to reduce current consumption
2.5 System control and diagnostic features
Mode control via the Serial Peripheral Interface (SPI)
Overtemperature warning and shutdown
Watchdog with independent clock source
Watchdog can be operated in Window, Timeout and Autonomous modes
Optional cyclic wake-up in watchdog Timeout mode
Watchdog automatically re-enabled when wake-up event captured
Watchdog period selectable between 8 ms and 4 s
Supports remote flash programming via the CAN bus
16-, 24- and 32-bit SPI for configuration, control and diagnosis
Bidirectional reset pin with variable power-on reset length to support a variety of
microcontrollers
Configuration of selected functions via non-volatile memory
3. Ordering information
Table 1.
Ordering information
Type number
UJA1164ATK
UJA1164A
Product data sheet
Package
Name
Description
Version
HVSON14
plastic thermal enhanced very thin small outline package; no
leads; 14 terminals; body 3 ´ 4.5 ´ 0.85 mm
SOT1086-2
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
4. Block diagram
UJA1164A
5
BAT
10
5 V MICROCONTROLLER SUPPLY (V1)
3
RSTN
V1
WATCHDOG
RXD
TXD
SCK
SDI
SDO
SCSN
4
HS-CAN
1
13
12
CANH
CANL
8
11
SPI
6
14
2
GND
Fig 1.
UJA1164A
Product data sheet
aaa-023211
Block diagram of UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
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5. Pinning information
5.1 Pinning
terminal 1
index area
TXD
1
14 SCSN
GND
2
13 CANH
V1
3
12 CANL
RXD
4
RSTN
5
10 BAT
SDO
6
9
i.c.
i.c.
7
8
SCK
UJA1164A
11 SDI
aaa-023212
Transparent top view
Fig 2.
Pin configuration diagram
5.2 Pin description
Table 2.
Symbol
Pin
Description
TXD
1
transmit data input
GND
2[1]
ground
V1
3
5 V microcontroller supply voltage
RXD
4
receive data output; reads out data from the bus lines
RSTN
5
reset input/output
SDO
6
SPI data output
i.c.
7
internally connected; should be left floating or connected to GND
SCK
8
SPI clock input
i.c.
9
internally connected; should be left floating or connected to GND
BAT
10
battery supply voltage
SDI
11
SPI data input
CANL
12
LOW-level CAN bus line
CANH
13
HIGH-level CAN bus line
SCSN
14
SPI chip select input
[1]
UJA1164A
Product data sheet
Pin description
The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
SBC via the printed circuit board. For enhanced thermal and electrical performance, it is recommended to
solder the exposed die pad to GND.
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
6. Functional description
6.1 System controller
The system controller manages register configuration and controls the internal functions
of the UJA1164A. Detailed device status information is collected and made available to
the microcontroller.
6.1.1 Operating modes
The system controller contains a state machine that supports six operating modes:
Normal, Standby, Reset, Forced Normal, Overtemp and Off. The state transitions are
illustrated in Figure 3.
6.1.1.1
Normal mode
Normal mode is the active operating mode. In this mode, all the hardware on the device is
available and can be activated (see Table 3). Voltage regulator V1 is enabled to supply the
microcontroller.
The CAN interface can be configured to be active and thus to support normal CAN
communication. Depending on the SPI register settings, the watchdog may be running in
Window or Timeout mode.
Normal mode can be selected from Standby mode via an SPI command (MC = 111).
6.1.1.2
Standby mode
Standby mode is the UJA1164A’s power saving mode, offering reduced current
consumption. The transceiver is unable to transmit or receive data in Standby mode. The
SPI remains enabled and V1 is still active; the watchdog is active (in Timeout mode) if
enabled.
If remote CAN wake-up is enabled (CWE = 1; see Table 24), the receiver monitors bus
activity for a wake-up request. The bus pins are biased to GND (via Ri(cm)) when the bus is
inactive for t > tto(silence) and at approximately 2.5 V when there is activity on the bus
(autonomous biasing).
Pin RXD is forced LOW when any enabled wake-up event is detected. This can be either
a regular wake-up (via the CAN bus) or a diagnostic wake-up such as an overtemperature
event (see Section 6.8).
The UJA1164A switches to Standby mode via Reset mode:
• from Off mode if the battery voltage rises above the power-on detection threshold
(Vth(det)pon)
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
Standby mode can also be selected from Normal mode via an SPI command (MC = 100).
UJA1164A
Product data sheet
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
MC = Standby
NORMAL
STANDBY
MC = Normal
any reset event
RSTN = HIGH &
FNMC = 0
V1 undervoltage
no overtemperature
RESET
RSTN = HIGH &
FNMC = 1
OVERTEMP
power-on
any reset event
FORCED
NORMAL
OFF
overtemperature event
VBAT undervoltage
from any mode
from any mode except Off
MTP programming completed or
MTP factory presets restored
Fig 3.
015aaa271
UJA1164A system controller state diagram
6.1.1.3
Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. The SPI is inactive;
the watchdog is disabled; V1 and overtemperature detection are active.
The UJA1164A switches to Reset mode from any mode in response to a reset event (see
Table 5 for a list of reset sources).
The UJA1164A exits Reset mode:
• and switches to Standby mode if pin RSTN is released HIGH
• and switches to Forced Normal mode if bit FNMC = 1
• if the SBC is forced into Off or Overtemp mode
If a V1 undervoltage event forced the transition to Reset mode, the UJA1164A will remain
in Reset mode until the voltage on pin V1 has recovered.
UJA1164A
Product data sheet
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
6.1.1.4
Off mode
The UJA1164A switches to Off mode when the battery is first connected or from any mode
when VBAT < Vth(det)poff. Only power-on detection is enabled; all other modules are
inactive. The UJA1164A starts to boot up when the battery voltage rises above the
power-on detection threshold Vth(det)pon (triggering an initialization process) and switches
to Reset mode after tstartup. In Off mode, the CAN pins disengage from the bus (zero load;
high-ohmic).
6.1.1.5
Overtemp mode
Overtemp mode is provided to prevent the UJA1164A being damaged by excessive
temperatures. The UJA1164A switches immediately to Overtemp mode from any mode
(other than Off mode) when the global chip temperature rises above the overtemperature
protection activation threshold, Tth(act)otp.
To help prevent the loss of data due to overheating, the UJA1164A issues a warning when
the IC temperature rises above the overtemperature warning threshold (Tth(warn)otp). When
this happens, status bit OTWS is set and an overtemperature warning event is captured
(OTW = 1), if enabled (OTWE = 1).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off and pin RSTN is driven LOW.
The UJA1164A exits Overtemp mode:
• and switches to Reset mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
• if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
6.1.1.6
Forced Normal mode
Forced Normal mode simplifies SBC testing and is useful for initial prototyping and failure
detection, as well as first flashing of the microcontroller. The watchdog is disabled in
Forced Normal mode. The low-drop voltage regulator (V1) and the CAN transceiver are
active.
Bit FNMC is factory preset to 1, so the UJA1164A initially boots up in Forced Normal
mode (see Table 8). This allows a newly installed device to be run in Normal mode without
a watchdog. So the microcontroller can be flashed via the CAN bus in the knowledge that
a watchdog timer overflow will not trigger a system reset.
The register containing bit FNMC (address 74h) is stored in non-volatile memory (see
Section 6.9). So once bit FNMC is programmed to 0, the SBC will no longer boot up in
Forced Normal mode, allowing the watchdog to be enabled.
Even in Forced Normal mode, a reset event (e.g. an external reset or a V1 undervoltage)
will trigger a transition to Reset mode with normal Reset mode behavior (except that the
transmitter remains active if there is no V1 undervoltage). However, the UJA1164A will
return to Forced Normal mode instead of switching to Standby mode when it exits Reset
mode.
UJA1164A
Product data sheet
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
In Forced Normal mode, only the Main status register, the Watchdog status register, the
Identification register and registers stored in non-volatile memory can be read. The
non-volatile memory area is fully accessible for writing as long as the UJA1164A is in the
factory preset state (for details see Section 6.9).
The UJA1164A switches from Reset mode to Forced Normal mode if bit FNMC = 1.
6.1.1.7
Table 3.
Hardware characterization for the UJA1164A operating modes
Hardware characterization by functional block
Block
Operating mode
Off
Forced Normal Standby
Normal
Reset
Overtemp
V1
off[1]
on
on
on
on
off
RSTN
LOW
HIGH
HIGH
HIGH
LOW
LOW
SPI
disabled active
active
active
disabled
disabled
off
off
off
WMC[2]
Watchdog
off
off
determined by bits
WMC (see Table 7)[2]
determined by bits
CAN
off
Active
Offline
Active/ Offline/ Listen-only
(determined by bits CMC;
see Table 14)
Offline
RXD
V1 level CAN bit stream
V1 level/LOW if
wake-up detected
CAN bit stream if
CMC = 01/10/11;
otherwise same as
Standby
V1 level/LOW V1 level/LOW
if wake-up
if wake-up
detected
detected
[1]
When the SBC switches from Reset, Standby or Normal mode to Off mode, V1 behaves as a current source during power down while
VBAT is between 3 V and 2 V.
[2]
Window mode is only active in Normal mode.
6.1.2 System control registers
The operating mode is selected via bits MC in the Mode control register. The Mode control
register is accessed via SPI address 0x01 (see Section 6.13).
Table 4.
Mode control register (address 01h)
Bit
Symbol
Access Value
7:3
reserved
R
2:0
MC
R/W
Description
mode control:
100
Standby mode
111
Normal mode
The Main status register can be accessed to monitor the status of the overtemperature
warning flag and to determine whether the UJA1164A has entered Normal mode after
initial power-up. It also indicates the source of the most recent reset event.
Table 5.
UJA1164A
Product data sheet
Main status register (address 03h)
Bit
Symbol
Access Value
7
reserved
R
6
OTWS
R
Description
overtemperature warning status:
0
IC temperature below overtemperature warning threshold
1
IC temperature above overtemperature warning threshold
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
Table 5.
Main status register (address 03h) …continued
Bit
Symbol
Access Value
Description
5
NMS
R
Normal mode status:
4:0
RSS
0
UJA1164A has entered Normal mode (after power-up)
1
UJA1164A has powered up but has not yet switched to
Normal mode
R
reset source status:
00000
exited Off mode (power-on)
01110
watchdog triggered too early (Window mode)
01111
watchdog overflow (Window mode or Timeout mode with
WDF = 1)
10000
illegal watchdog mode control access
10001
RSTN pulled down externally
10010
exited Overtemp mode
10011
V1 undervoltage
6.2 Watchdog
The UJA1164A contains a watchdog that supports three operating modes: Window,
Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a
watchdog trigger event within a closed watchdog window resets the watchdog timer. In
Timeout mode, the watchdog runs continuously and can be reset at any time within the
timeout time by a watchdog trigger. Watchdog timeout mode can also be used for cyclic
wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or in
Timeout mode (see Section 6.2.4).
The watchdog mode is selected via bits WMC in the Watchdog control register (Table 7).
The SBC must be in Standby mode when the watchdog mode and/or period is changed. If
Window mode is selected (WMC = 100), the watchdog will remain in (or switch to)
Timeout mode until the SBC enters Normal mode. Any attempt to change the watchdog
operating mode (via WMC) or period (via NWP) while the SBC is in Normal mode will
cause the UJA1164A to switch to Reset mode. The reset source status bits (RSS) will be
set to 10000 (‘illegal watchdog mode control access’; see Table 5) and an SPI failure
(SPIF) event triggered, if enabled.
Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is
programmed via bits NWP. The selected period is valid for both Window and Timeout
modes. The default watchdog period is 128 ms.
A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid
write access to the Watchdog control register. If the watchdog mode or the watchdog
period have changed as a result of the write access, the new values are immediately
valid.
Table 6.
Watchdog configuration
Operating/watchdog mode
FNMC (Forced Normal mode control)
0
0
0
0
1
SDMC (Software Development mode
control)
x
x
0
1
x
WMC (watchdog mode control)
100 (Window)
010 (Timeout)
001 (Autonomous) 001 (Autonomous)
UJA1164A
Product data sheet
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
Table 6.
Watchdog configuration
Operating/watchdog mode
SBC Operating
Mode
Normal mode
[1]
Window
Timeout
Timeout
off
off
Standby mode (RXD
HIGH)[1]
Timeout
Timeout
off
off
off
Standby mode (RXD
LOW)[1]
Timeout
Timeout
Timeout
off
off
Sleep mode
Timeout
Timeout
off
off
off
Other modes
off
off
off
off
off
RXD LOW signals a pending wake-up.
Table 7.
Watchdog control register (address 00h)
Bit
Symbol
Access Value
Description
7:5
WMC
R/W
watchdog mode control:
4
reserved
R
3:0
NWP
R/W
[1]
001[1]
Autonomous mode
010[2]
Timeout mode
100[3]
Window mode
nominal watchdog period
1000
8 ms
0001
16 ms
0010
32 ms
1011
64 ms
0100[2]
128 ms
1101
256 ms
1110
1024 ms
0111
4096 ms
Default value if SDMC = 1 (see Section 6.2.1)
[2]
Default value.
[3]
Selected in Standby mode but only activated when the SBC switches to Normal mode.
The watchdog is a valuable safety mechanism, so it is critical that it is configured correctly.
Two features are provided to prevent watchdog parameters being changed by mistake:
• redundant states of configuration bits WMC and NWP
• reconfiguration protection in Normal mode
Redundant states associated with control bits WMC and NWP ensure that a single bit
error cannot cause the watchdog to be configured incorrectly (at least two bits must be
changed to reconfigure WMC or NWP). If an attempt is made to write an invalid code to
WMC or NWP (e.g. 011 or 1001 respectively), the SPI operation is abandoned and an SPI
failure event is captured, if enabled (see Section 6.8).
Two operating modes have a major impact on the operation of the watchdog: Forced
Normal mode and Software Development mode (Software Development mode is provided
for test purposes and is not an SBC operating mode; the UJA1164A can be in any mode
with Software Development mode enabled; see Section 6.2.1). These modes are enabled
and disabled via bits FNMC and SDMC respectively in the SBC configuration control
UJA1164A
Product data sheet
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UJA1164A
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Mini high-speed CAN system basis chip with Standby mode &
watchdog
register (see Table 8). Note that this register is located in the non-volatile memory area
(see Section 6.8). In Forced Normal mode (FNM), the watchdog is completely disabled. In
Software Development mode (SDM), the watchdog can be disabled or activated for test
purposes.
Information on the status of the watchdog is available from the Watchdog status register
(Table 9). This register also indicates whether Forced Normal and Software Development
modes are active.
Table 8.
SBC configuration control register (address 74h)
Bit
Symbol
Access Value
7:6
reserved
R
5:4
V1RTSUC
R/W
3
FNMC
V1 reset threshold (defined by bit V1RTC) at start-up:
00[1]
V1 undervoltage detection at 90 % of nominal value at
start-up (V1RTC = 00)
01
V1 undervoltage detection at 80 % of nominal value at
start-up (V1RTC = 01)
10
V1 undervoltage detection at 70 % of nominal value at
start-up (V1RTC = 10)
11
V1 undervoltage detection at 60 % of nominal value at
start-up (V1RTC = 11)
R/W
Forced Normal mode control:
0
1[1]
2
1:0
[1]
SDMC
reserved
Forced Normal mode enabled
Software Development mode control:
0[1]
Software Development mode disabled
1
Software Development mode enabled
-
Watchdog status register (address 05h)
Bit
Symbol
Access Value
7:4
reserved
R
-
3
FNMS
R
0
SBC is not in Forced Normal mode
1
SBC is in Forced Normal mode
0
SBC is not in Software Development mode
1
SBC is in Software Development mode
2
1:0
Product data sheet
Forced Normal mode disabled
Factory preset value.
Table 9.
UJA1164A
R/W
R
Description
-
SDMS
WDS
R
R
Description
watchdog status:
00
watchdog is off
01
watchdog is in first half of window
10
watchdog is in second half of window
11
reserved
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Mini high-speed CAN system basis chip with Standby mode &
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6.2.1 Software Development mode
Software Development mode is provided to simplify the software design process. When
Software Development mode is enabled, the watchdog starts up in Autonomous mode
(WMC = 001) and is inactive after a system reset, overriding the default value (see
Table 7). The watchdog is always off in Autonomous mode if Software Development mode
is enabled (SDMC = 1; see Table 10).
Software can be run without a watchdog in Software Development mode. However, it is
possible to activate and deactivate the watchdog for test purposes by selecting Window or
Timeout mode via bits WMC while the SBC is in Standby mode (note that Window mode
will only be activated when the SBC switches to Normal mode). Software Development
mode is activated via bits SDMC in non-volatile memory (see Table 8).
6.2.2 Watchdog behavior in Window mode
The watchdog runs continuously in Window mode. The watchdog will be in Window mode
if WMC = 100 and the UJA1164A is in Normal mode.
In Window mode, the watchdog can only be triggered during the second half of the
watchdog period. If the watchdog overflows, or is triggered in the first half of the watchdog
period (before ttrig(wd)1), a system reset is performed. After the system reset, the reset
source (either ‘watchdog triggered too early’ or ‘watchdog overflow’) can be read via the
reset source status bits (RSS) in the Main Status register (Table 5). If the watchdog is
triggered in the second half of the watchdog period (after ttrig(wd)1 but before ttrig(wd)2), the
watchdog timer is restarted.
6.2.3 Watchdog behavior in Timeout mode
The watchdog runs continuously in Timeout mode. The watchdog will be in Timeout mode
if WMC = 010 and the UJA1164A is in Normal or Standby mode. The watchdog will also
be in Timeout mode if WMC = 100 and the UJA1164A is in Standby mode. If Autonomous
mode is selected (WMC = 001), the watchdog will be in Timeout mode if one of the
conditions for Timeout mode listed in Table 10 has been satisfied.
In Timeout mode, the watchdog timer can be reset at any time by a watchdog trigger. If the
watchdog overflows, a watchdog failure event (WDF) is captured. If a WDF is already
pending when the watchdog overflows, a system reset is performed. In Timeout mode, the
watchdog can be used as a cyclic wake-up source for the microcontroller when the
UJA1164A is in Standby mode.
6.2.4 Watchdog behavior in Autonomous mode
Autonomous mode is selected when WMC = 001. In Autonomous mode, the watchdog is
either off or in Timeout mode, according to the conditions detailed in Table 10.
Table 10.
Watchdog status in Autonomous mode
UJA1164A operating mode
UJA1164A
Product data sheet
Watchdog status
SDMC = 0
SDMC = 1
Normal
Timeout mode
off
Standby; RXD HIGH
off
off
any other mode
off
off
Standby; RXD LOW
Timeout mode
off
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Mini high-speed CAN system basis chip with Standby mode &
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When Autonomous mode is selected, the watchdog will be in Timeout mode if the SBC is
in Normal mode or Standby mode with RXD LOW, provided Software Development mode
has been disabled (SDMC = 0). Otherwise the watchdog will be off.
In Autonomous mode, the watchdog will not be running when the SBC is in Standby mode
(RXD HIGH). If a wake-up event is captured, pin RXD is forced LOW to signal the event
and the watchdog is automatically restarted in Timeout mode.
6.3 System reset
When a system reset occurs, the SBC switches to Reset mode and initiates a process
that generates a low-level pulse on pin RSTN.
6.3.1 Characteristics of pin RSTN
Pin RSTN is a bidirectional open drain low side driver with integrated pull-up resistance,
as shown in Figure 4. With this configuration, the SBC can detect the pin being pulled
down externally, e.g. by the microcontroller. The input reset pulse width must be at least
tw(rst).
V1
RSTN
015aaa276
Fig 4.
RSTN internal pin configuration
6.3.2 Selecting the output reset pulse width
The duration of the output reset pulse is selected via bits RLC in the Start-up control
register (Table 11). The SBC distinguishes between a cold start and a warm start. A cold
start is performed if the reset event was combined with a V1 undervoltage event
(power-on reset, overtemperature reset, V1 undervoltage before entering or while in
Reset mode). The output reset pulse width for a cold start is determined by the setting of
bits RLC.
If any other reset event occurs without a V1 undervoltage (external reset, watchdog
failure, watchdog change attempt in Normal mode) the SBC uses the shortest reset length
(tw(rst) = 1 ms to 1.5 ms). This is called warm start of the microcontroller.
Table 11.
UJA1164A
Product data sheet
Start-up control register (address 73h)
Bit
Symbol
Access Value
7:6
reserved
R
Description
-
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Table 11.
Start-up control register (address 73h) …continued
Bit
Symbol
Access Value
Description
5:4
RLC
R/W
RSTN output reset pulse width:
3:0
[1]
reserved
R
00[1]
tw(rst) = 20 ms to 25 ms
01
tw(rst) = 10 ms to 12.5 ms
10
tw(rst) = 3.6 ms to 5 ms
11
tw(rst) = 1 ms to 1.5 ms
-
Factory preset value.
6.3.3 Reset sources
The following events will cause the UJA1164A to switch to Reset mode:
•
•
•
•
•
•
VV1 drops below the selected V1 undervoltage threshold defined by bits V1RTC
pin RSTN is pulled down externally
the watchdog overflows in Window mode
the watchdog is triggered too early in Window mode (before ttrig(wd)1)
the watchdog overflows in Timeout mode with WDF = 1 (watchdog failure pending)
an attempt is made to reconfigure the Watchdog control register while the SBC is in
Normal mode
• the SBC leaves Off or Overtemp mode
6.4 Global temperature protection
The temperature of the UJA1164A is monitored continuously, except in Off mode. The
SBC switches to Overtemp mode if the temperature exceeds the overtemperature
protection activation threshold, Tth(act)otp. In addition, pin RSTN is driven LOW and V1 and
the CAN transceiver are switched off. When the temperature drops below the
overtemperature protection release threshold, Tth(rel)otp, the SBC switches to Standby
mode via Reset mode.
In addition, the UJA1164A provides an overtemperature warning. When the IC
temperature rises about the overtemperature warning threshold (Tth(warn)otp), status bit
OTWS is set and an overtemperature warning event is captured (OTW = 1).
6.5 Power supplies
6.5.1 Battery supply voltage (VBAT)
The internal circuitry is supplied from the battery via pin BAT. The device needs to be
protected against negative supply voltages, e.g. by using an external series diode. If VBAT
falls below the power-off detection threshold, Vth(det)poff, the SBC switches to Off mode.
However, the microcontroller supply voltage (V1) remains active until VBAT falls below 2 V.
The SBC switches from Off mode to Reset mode tstartup after the battery voltage rises
above the power-on detection threshold, Vth(det)pon. Power-on event status bit PO is set to
1 to indicate the UJA1164A has powered up and left Off mode (see Table 19).
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6.5.2 Low-drop voltage supply for 5 V microcontroller (V1)
V1 is intended to supply the microcontroller and the internal CAN transceiver and delivers
up to 150 mA at 5 V. The output voltage on V1 is monitored. A system reset is generated
if the voltage on V1 drops below the selected undervoltage threshold (60 %, 70 %, 80 %
or 90 % of the nominal V1 output voltage, selected via V1RTC in the V1 control register;
see Table 12).
The internal CAN transceiver consumes 50 mA (max) when the bus is continuously
dominant, leaving 100 mA available for the external load on pin V1. In practice, the typical
current consumption of the CAN transceiver is lower (25 mA), depending on the
application, leaving more current available for the load.
The default value of the undervoltage threshold at power-up is determined by the value of
bits V1RTSUC in the SBC configuration control register (Table 8). The SBC configuration
control register is in non-volatile memory, allowing the user to define the undervoltage
threshold (V1RTC) at start-up.
In addition, an undervoltage warning (a V1U event; see Section 6.8) is generated if the
voltage on V1 falls below 90 % of the nominal value (and V1U event detection is enabled,
V1UE = 1; see Table 23). This information can be used as a warning, when the 60 %,
70 % or 80 % threshold is selected, to indicate that the level on V1 is outside the nominal
supply range. The status of V1, whether it is above or below the 90 % undervoltage
threshold, can be read via bit V1S in the Supply voltage status register (Table 13).
Table 12.
V1 control register (address 10h)
Bit
Symbol
Access Value
7:2
reserved
R
1:0
V1RTC[1]
R/W
[1]
set V1 reset threshold:
00
reset threshold set to 90 % of V1 nominal output voltage
01
reset threshold set to 80 % of V1 nominal output voltage
10
reset threshold set to 70 % of V1 nominal output voltage
11
reset threshold set to 60 % of V1 nominal output voltage
Default value at power-up defined by setting of bits V1RTSUC (see Table 8).
Table 13.
Supply voltage status register (address 1Bh)
Bit
Symbol
Access
Value
7:1
reserved
R
-
0
V1S
R/W
[1]
Description
Description
V1 status:
0[1]
V1 output voltage above 90 % undervoltage threshold
1
V1 output voltage below 90 % undervoltage threshold
Default value at power-up.
6.6 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2:2016 compliant. The CAN transmitter is
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supplied from V1. The UJA1164A includes additional timing parameters on loop delay
symmetry to ensure reliable communication in fast phase at data rates up to 5 Mbit/s, as
used in CAN FD networks.
The CAN transceiver supports autonomous CAN biasing, which helps to minimize RF
emissions. CANH and CANL are always biased to 2.5 V when the transceiver is in Active
or Listen-only modes (CMC = 01/10/11).
Autonomous biasing is active in CAN Offline mode - to 2.5 V if there is activity on the bus
(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence)
(CAN Offline mode).
This is useful when the node is disabled due to a malfunction in the microcontroller. The
SBC ensures that the CAN bus is correctly biased to avoid disturbing ongoing
communication between other nodes. The autonomous CAN bias voltage is derived
directly from VBAT.
6.6.1 CAN operating modes
The integrated CAN transceiver supports four operating modes: Active, Listen-only,
Offline and Offline Bias (see Figure 5). The CAN transceiver operating mode depends on
the UJA1164A operating mode and on the setting of bits CMC in the CAN control register
(Table 14).
When the UJA1164A is in Normal mode, the CAN transceiver operating mode (Active,
Listen-only or Offline) can be selected via bits CMC in the CAN control register (Table 14).
When the UJA1164A is in Standby mode, the transceiver is forced to Offline or Offline
Bias mode (depending on bus activity).
6.6.1.1
CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
CAN Active mode is selected when CMC = 01 or 10. When CMC = 01, V1/CAN
undervoltage detection is enabled and the transceiver will go to CAN Offline or CAN
Offline Bias mode when the voltage on V1 drops below the 90 % threshold. When
CMC = 10, V1/CAN undervoltage detection is disabled. The transmitter will remain active
until the voltage on V1 drops below the V1 reset threshold (selected via bits V1RTC). The
SBC will then switch to Reset mode and the transceiver will switch to CAN Offline or CAN
Offline Bias mode.
The CAN transceiver is in Active mode when:
• the UJA1164A is in Normal mode (MC = 111) and the CAN transceiver has been
enabled by setting bits CMC in the CAN control register to 01 or 10 (see Table 14)
and:
– if CMC = 01, the voltage on pin V1 is above the 90 % undervoltage threshold
– if CMC = 10, the voltage on pin V1 is above the V1 reset threshold
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If pin TXD is held LOW (e.g. by a short-circuit to GND) when CAN Active mode is selected
via bits CMC, the transceiver will not enter CAN Active mode but will switch to or remain in
CAN Listen-only mode. It will remain in Listen-only mode until pin TXD goes HIGH in
order to prevent a hardware and/or software application failure from driving the bus lines
to an unwanted dominant state.
In CAN Active mode, the CAN bias voltage is derived from V1.
The application can determine whether the CAN transceiver is ready to transmit/receive
data or is disabled by reading the CAN Transceiver Status (CTS) bit in the Transceiver
Status Register (Table 15).
6.6.1.2
CAN Listen-only mode
CAN Listen-only mode allows the UJA1164A to monitor bus activity while the transceiver
is inactive, without influencing bus levels. This facility could be used by development tools
that need to listen to the bus but do not need to transmit or receive data or for
software-driven selective wake-up. Dedicated microcontrollers could be used for selective
wake-up, providing an embedded low-power CAN engine designed to monitor the bus for
potential wake-up events.
In Listen-only mode the CAN transmitter is disabled, reducing current consumption. The
CAN receiver and CAN biasing remain active. This enables the host microcontroller to
switch to a low-power mode in which an embedded CAN protocol controller remains
active, waiting for a signal to wake up the microcontroller.
The CAN transceiver is in Listen-only mode when:
• the UJA1164A is in Normal mode and CMC = 11
The CAN transceiver will not leave Listen-only mode while TXD is LOW or CAN Active
mode is selected with CMC = 01 while the voltage on V1 is below the 90 % undervoltage
threshold.
6.6.1.3
CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event, provided
CAN wake-up detection is enabled (CWE = 1). CANH and CANL are biased to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN
bus is biased to 2.5 V. This mode is activated automatically when activity is detected on
the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to
CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than tto(silence).
The CAN transceiver switches to CAN Offline mode from CAN Active mode or CAN
Listen-only mode if:
• the SBC switches to Reset or Standby mode OR
• the SBC is in Normal mode and CMC = 00
provided the CAN-bus has been inactive for at least tto(silence). If the CAN-bus has been
inactive for less than tto(silence), the CAN transceiver switches first to CAN Offline Bias
mode and then to CAN Offline mode once the bus has been silent for tto(silence).
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The CAN transceiver switches to CAN Offline/Offline Bias mode from CAN Active mode if
CMC = 01 and the voltage on V1 drops below the 90 % undervoltage threshold or
CMC = 10 and the voltage on V1 drops below the V1 reset threshold.
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode if no activity is detected on the bus (no CAN edges) for
t > tto(silence) OR
• when the SBC switches from Off or Overtemp mode to Reset mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
• a standard wake-up pattern is detected on the CAN bus OR
• the SBC is in Normal mode, CMC = 01 or 10 and VV1 < 90 %
6.6.1.4
CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the SBC switches to Off or Overtemp mode OR
• VBAT falls below the CAN receiver undervoltage detection threshold, Vuvd(CAN)
It will be switched on again on entering CAN Offline mode when VBAT rises above the
undervoltage recovery threshold (Vuvr(CAN)) and the SBC is no longer in Off/Overtemp
mode. CAN Off mode prevents reverse currents flowing from the bus when the battery
supply to the SBC is lost.
UJA1164A
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CAN Active
[Reset OR Standby OR
(Normal & CMC = 00) OR
(CMC = 01 & V V1 < 90 %)]
& t > tto(silence)
transmitter: on
RXD: bitstream
CANH/CANL: terminated
to V1/2 (≈2.5 V)
Normal & CMC = 11
[Reset OR Standby OR
(Normal & CMC = 00) OR
(CMC = 01 & V V1 < 90 %)]
& t < tto(silence)
Normal &
Normal &
(CMC = 01 OR CMC = 10) &
(CMC = 01 OR CMC = 10) &
VV1 > 90 %(1)
VV1 > 90 %((1)
Normal & CMC = 11
CAN Offline Bias
transmitter: off
RXD: wake-up/int
CANH/CANL: terminated
to 2.5 V (from VBAT)
Normal &
(CMC = 01 OR
CMC = 10) &
VV1 > 90 %(1)
CAN Listen-only
transmitter: off
RXD: bitstream
CANH/CANL: terminated
to 2.5 V (from VBAT)
[Reset OR Standby OR
(Normal & CMC = 00)]
& t < tto(silence)
[Reset OR Standby OR Sleep OR
(Normal & CMC =00)]
& t > tto(silence)
Normal &
(CMC = 01 OR CMC = 10) &
VV1 < 90 %
from all modes
Normal & CMC = 11
CAN bus wake-up OR
[Normal & (CMC = 01 OR CMC = 10) &
VV1 < 90 %]
[Reset OR Standby OR
(Normal & CMC = 00)]
& t > tto(silence)
Off OR
Overtemp OR
VBAT < Vuvd(CAN)
CAN Offline
CAN Off
transmitter: off
RXD: wake-up/int
CANH/CANL: terminated
to GND
transmitter: off
RXD: wake-up/int
CANH/CANL: floating
leaving Off/Overtemp &
VBAT > Vuvr(CAN)
015aaa312
(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN
Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND)
Fig 5.
CAN transceiver state machine (with FNMC = 0)
6.6.2 CAN standard wake-up
If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), the
UJA1164A will monitor the bus for a wake-up pattern.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up
filter and trigger a wake-up event (see Figure 6; note that additional pulses may occur
between the recessive/dominant phases). The recessive and dominant phases must last
at least twake(busrec) and twake(busdom), respectively.
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CANH
VO(dif)
CANL
twake(busdom)
twake(busrec)
twake(busdom)
RXD
≤ tto(wake)bus
aaa-021858
Fig 6.
CAN wake-up timing
When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the
Transceiver event status register is set (see Table 21) and pin RXD is driven LOW.
6.6.3 CAN control and Transceiver status registers
Table 14.
Bit
Symbol
Access Value
7:2
reserved
R/W
1:0
CMC
R/W
Table 15.
CAN transceiver operating mode selection (available
when UJA1164A is in Normal mode; MC = 111):
00
Offline mode
01
Active mode; see Section 6.6.1.1 and Section 6.6.1.3
10
Active mode; see Section 6.6.1.1 and Section 6.6.1.3
11
Listen-only mode
Transceiver status register (address 22h)
Symbol
Access Value
Description
7
CTS
R
0
CAN transceiver not in Active mode
1
CAN transceiver in Active mode
6:4
reserved
R
-
3
CBSS
R
0
CAN bus active (communication detected on bus)
1
CAN bus inactive (for longer than tto(silence))
2
reserved
R
-
1
VCS[1]
R
0
the output voltage on V1 is above the 90 % threshold
1
the output voltage on V1 is below the 90 % threshold
0
no TXD dominant timeout event detected
1
CAN transmitter disabled due to a TXD dominant
timeout event
[1]
Product data sheet
Description
-
Bit
0
UJA1164A
CAN control register (address 20h)
CFS
R
Only active when CMC = 01.
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6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 4.4 kbit/s.
When the TXD dominant time-out time is exceeded, a CAN failure event is captured
(CF = 1; see Table 21), if enabled (CFE = 1; see Table 24). In addition, the status of the
TXD dominant timeout can be read via the CFS bit in the Transceiver status register
(Table 15) and bit CTS is cleared.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
6.7.3 V1 undervoltage event
When CMC = 01, a CAN failure event is captured (CF = 1) and status bit VCS is set to 1
when the supply to the CAN transceiver (VV1) falls below 90 % of its nominal value
(assuming CAN failure detection is enabled; CFE = 1).
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
6.8 Wake-up and interrupt event diagnosis via pin RXD
Wake-up and interrupt event diagnosis in the UJA1164A is intended to provide the
microcontroller with information on the status of a range of features and functions. This
information is stored in the event status registers (Table 19 to Table 21) and is signaled on
pin RXD, if enabled.
A distinction is made between regular CAN wake-up events and interrupt events.
UJA1164A
Product data sheet
Table 16.
Regular events
Symbol
Event
Power-on Description
CW
CAN wake-up
disabled
a CAN wake-up event was detected while the
transceiver was in CAN Offline mode.
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Table 17.
Diagnostic/interrupt events
Symbol
Event
Power-on
Description
PO
power-on
always
enabled
the UJA1164A has exited Off mode (after battery power has been
restored/connected)
OTW
overtemperature warning disabled
the IC temperature has exceeded the overtemperature warning
threshold
SPIF
SPI failure
disabled
SPI clock count error (only 16-, 24- and 32-bit commands are valid),
illegal WMC, NWP or MC code or attempted write access to locked
register
WDF
watchdog failure
always
enabled
watchdog overflow in Window or Timeout mode or watchdog triggered
too early in Window mode; a system reset is triggered immediately in
response to a watchdog failure in Window mode; when the watchdog
overflows in Timeout mode, a system reset is only performed if a WDF
is already pending (WDF = 1)
V1U
V1 undervoltage
disabled
voltage on V1 has dropped below the 90 % undervoltage threshold
when V1 is active. V1U event capture is independent of the setting of
bits V1RTC.
CBS
CAN bus silence
disabled
no activity on CAN bus for tto(silence) (detected only when CBSE = 1
while bus active)
CF
CAN failure
disabled
one of the following CAN failure events detected:
- CAN transceiver deactivated due to a V1 undervoltage
- CAN transceiver deactivated due to a dominant clamped TXD.
PO and WDF interrupts are always captured. Wake-up and interrupt detection can be
enabled/disabled for the remaining events individually via the event capture enable
registers (Table 22 to Table 24).
If an event occurs while the associated event capture function is enabled, the relevant
event status bit is set. If the transceiver is in CAN Offline mode with V1 active (SBC
Normal or Standby mode), pin RXD is forced LOW to indicate that a wake-up or interrupt
event has been detected.
The microcontroller can monitor events via the event status registers. An extra status
register, the Global event status register (Table 18), is provided to help speed up software
polling routines. By polling the Global event status register, the microcontroller can quickly
determine the type of event captured (system, supply or transceiver) and then query the
relevant table (Table 19, Table 20 or Table 21 respectively).
After the event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be
cleared in a single write operation by writing 1 to all relevant bits.
It is strongly recommended to clear only the status bits that were set to 1 when the status
registers were last read. This precaution ensures that events triggered just before the
write access are not lost.
6.8.1 Interrupt/wake-up delay
If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline
mode, they can have a significant impact on the software processing time (because pin
RXD is repeatedly driven LOW, requiring a response from the microcontroller each time
an interrupt/wake-up is generated). The UJA1164A incorporates an event delay timer to
limit the disturbance to the software.
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When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a
timer is started. If further events occur while the timer is running, the relevant status bits
are set. If one or more events are pending when the timer expires after td(event), pin RXD
goes LOW again to alert the microcontroller.
In this way, the microcontroller is interrupted once to process a number of events rather
than several times to process individual events.
If all events are cleared while the timer is running, RXD remains HIGH after the timer
expires, since there are no pending events. The event capture registers can be read at
any time.
The event capture delay timer is stopped immediately when pin RSTN goes low (triggered
by a HIGH-to-LOW transition on the pin). RSTN is driven LOW when the SBC enters
Reset, Overtemp and Off modes.
6.8.2 Event status and event capture registers
After an event source has been identified, the status flag should be cleared (set to
0) by writing 1 to the relevant status bit (writing 0 will have no effect).
Table 18.
Symbol
Access
Value
7:3
reserved
R
-
2
TRXE
R
0
1
transceiver event pending at address 0x63
1
SUPE
R
0
no pending supply event
1
supply event pending at address 0x62
0
no pending system event
1
system event pending at address 0x61
0
SYSE
Table 19.
no pending transceiver event
System event status register (address 61h)
Symbol
Access
Value
7:5
reserved
R
-
4
PO
R/W
0
no recent power-on
1
the UJA1164A has left Off mode after power-on
Description
3
reserved
R
-
2
OTW
R/W
0
overtemperature not detected
1
the global chip temperature has exceeded the
overtemperature warning threshold (Tth(warn)otp)
0
no SPI failure detected
1
SPI failure detected
0
no watchdog failure event captured
1
watchdog failure event captured
0
Product data sheet
R
Description
Bit
1
UJA1164A
Global event status register (address 60h)
Bit
SPIF
WDF
R/W
R/W
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Table 20.
Supply event status register (address 62h)
Bit
Symbol
Access
7:1
reserved
R
-
0
V1U
R/W
0
no V1 undervoltage event captured
1
V1 undervoltage event captured
Table 21.
Value
Transceiver event status register (address 63h)
Bit
Symbol
Access
Value
7:5
reserved
R
-
4
CBS
R/W
0
CAN bus active
1
no activity on CAN bus for tto(silence)
reserved
R
-
1
CF
R/W
0
no CAN failure detected
1
(CMC = 01 & CAN transceiver deactivated due to V1
undervoltage) OR dominant clamped TXD
CW
Table 22.
R/W
0
no CAN wake-up event detected
1
CAN wake-up event detected while the transceiver is
in CAN Offline Mode
System event capture enable register (address 04h)
Bit
Symbol
Access
Value
7:3
reserved
R
-
2
OTWE
R/W
1
1
0
SPIFE
reserved
Table 23.
R/W
R
overtemperature warning enabled
0
SPI failure detection disabled
1
SPI failure detection enabled
-
Supply event capture enable register (address 1Ch)
Symbol
Access
Value
7:1
reserved
R
-
0
V1UE
R/W
Description
V1 undervoltage detection:
0
V1 undervoltage detection disabled
1
V1 undervoltage detection enabled
Transceiver event capture enable register (address 23h)
Bit
Symbol
Access
Value
7:5
reserved
R
-
4
CBSE
R/W
3:2
overtemperature warning disabled
SPI failure detection:
Bit
Table 24.
Description
overtemperature warning event capture:
0
Product data sheet
Description
3:2
0
UJA1164A
Description
reserved
R
Description
CAN bus silence detection:
0
CAN bus silence detection disabled
1
CAN bus silence detection enabled
-
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Table 24.
Transceiver event capture enable register (address 23h)
Bit
Symbol
Access
1
CFE
R/W
Value
Description
CAN failure detection
0
CAN failure detection disabled
1
0
CWE
R/W
CAN failure detection enabled
CAN wake-up detection:
0
CAN wake-up detection disabled
1
CAN wake-up detection enabled
6.9 Non-volatile SBC configuration
The UJA1164A contains Multiple Time Programmable Non-Volatile (MTPNV) memory
cells that allow some of the default device settings to be reconfigured. The MTPNV
memory address range is from 0x73 to 0x74. An overview of the MTPNV registers is given
in Table 25.
Table 25.
Overview of MTPNV registers
Address Register Name
Bit:
7
6
5
4
3
0x73
Start-up control
(see Table 11)
reserved
RLC
reserved
0x74
SBC configuration control
(see Table 8)
reserved
V1RTSUC
FNMC
2
1
SDMC
reserved
0
6.9.1 Programming MTPNV cells
The UJA1164A must be in Forced Normal mode and the MTPNV cells must contain the
factory preset values before the non-volatile memory can be reprogrammed. The
UJA1164A will switch to Forced Normal mode after a reset event (e.g. pin RSTN LOW)
when the MTPNV cells contain the factory preset values (since FNMC = 1).
The factory presets may need to be restored before reprogramming can begin (see
Section 6.9.2). When the factory presets have been restored, a system reset is generated
automatically and UJA1164A switches to Forced Normal mode. This ensures that the
programming cycle cannot be interrupted by the watchdog.
Programming of the non-volatile memory registers is performed in two steps. Firstly, the
required values are written to addresses 0x73 and 0x74. In the second step,
reprogramming is confirmed by writing the correct CRC value to the MTPNV CRC control
register (see Section 6.9.1.1). The SBC starts reprogramming the MTPNV cells as soon
as the CRC value has been validated. If the CRC value is not correct, reprogramming is
aborted. On completion, a system reset is generated to indicate that the MTPNV cells
have been reprogrammed successfully. Note that the MTPNV cells cannot be read while
they are being reprogrammed.
After an MTPNV programming cycle has been completed, the non-volatile memory is
protected from being overwritten via a standard SPI write operation.
The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP; see
Table 42). Bit NVMPS in the MTPNV status register (Table 26) indicates whether or not
the non-volatile cells can be reprogramed. This register also contains a write counter,
WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a
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maximum value of 111111; there is no overflow; performing a factory reset also increments
the counter). This counter is provided for information purposes only; reprogramming will
not be rejected when it reaches its maximum value.
An error correction code status bit, ECCS, is set to indicate that the CRC check
mechanism in the SBC has detected a single bit failure in non-volatile memory. If more
than one bit failure is detected, the SBC will not restart after MTPNV reprogramming.
Check the ECCS flag at the end of the production cycle to verify the content of non-volatile
memory. When this flag is set, it indicates a device or ECU failure.
Table 26.
MTPNV status register (address 70h)
Bit
Symbol
Access
7:2
WRCNTS R
Value
write counter status:
xxxxxx
1
ECCS
0
[1]
6.9.1.1
R/W
NVMPS
Description
contains the number of times the MTPNV cells were
reprogrammed
error correction code status:
0
no bit failure detected in non-volatile memory
1
bit failure detected and corrected in non-volatile
memory
R/W
non-volatile memory programming status:
0
MTPNV memory cannot be overwritten
1[1]
MTPNV memory is ready to be reprogrammed
Factory preset value.
Calculating the CRC value for MTP programming
The cyclic redundancy check value stored in bits CRCC in the MTPNV CRC control
register is calculated using the data written to registers 0x73 and 0x74.
Table 27.
MTPNV CRC control register (address 75h)
Bit
Symbol
Access
Value
Description
7:0
CRCC
R/W
-
CRC control data
The CRC value is calculated using the data representation shown in Figure 7 and the
modulo-2 division with the generator polynomial: X8 + X5 + X3 + X2 + X + 1. The result of
this operation must be bitwise inverted.
7
6
1
0
7
register 0x73
Fig 7.
6
1
register 0x74
0
015aaa382
Data representation for CRC calculation
The following parameters can be used to calculate the CRC value (e.g. via the Autosar
method):
UJA1164A
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Table 28.
Parameters for CRC coding
Parameter
Value
CRC result width
8 bits
Polynomial
0x2F
Initial value
0xFF
Input data reflected
no
Result data reflected
no
XOR value
0xFF
Alternatively, the following algorithm can be used:
data = 0 // unsigned byte
crc = 0xFF
for i = 0 to 1
data = content_of_address(0x73 + i) EXOR crc
for j = 0 to 7
if data 128
data = data * 2 // shift left by 1
data = data EXOR 0x2F
else
data = data * 2 // shift left by 1
next j
crc = data
next i
crc = crc EXOR 0xFF
6.9.2 Restoring factory preset values
Factory preset values are restored if the following conditions apply for at least td(MTPNV)
during power-up:
• pin RSTN is held LOW
• CANH is pulled up to VBAT
• CANL is pulled down to GND
After the factory preset values have been restored, the SBC performs a system reset and
enters Forced normal Mode. Since the CAN bus is clamped dominant, pin RXDC is forced
LOW. During the factory preset restore process, this pin is forced HIGH; a falling edge on
this pin caused by bit PO being set after power-on then clearly indicates that the process
has been completed.
Note that the write counter, WRCNTS, in the MTPNV status register is incremented every
time the factory presets are restored.
6.10 Device ID
A byte is reserved at address 0x7E for a UJA1164A identification code.
Table 29.
UJA1164A
Product data sheet
Identification register (address 7Eh)
Bit
Symbol
Access
Value
Description
7:0
IDS[7:0]
R
80h
device identification code
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6.11 Lock control register
Sections of the register address area can be write-protected to protect against unintended
modifications. Note that this facility only protects locked bits from being modified via the
SPI and will not prevent the UJA1164A updating status registers etc.
Table 30.
Lock control register (address 0Ah)
Bit
Symbol
Access Value
7
reserved
R
6
LK6C
R/W
5
4
3
LK5C
LK4C
LK3C
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 5: address area 0x50 to 0x5F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 4: address area 0x40 to 0x4F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 3: address area 0x30 to 0x3F
1
1
0
LK2C
LK1C
LK0C
cleared for future use
lock control 6: address area 0x68 to 0x6F
0
2
Description
R/W
SPI write-access enabled
SPI write-access disabled
lock control 2: address area 0x20 to 0x2F - transceiver control
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 1: address area 0x10 to 0x1F - regulator control
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 0: address area 0x06 to 0x09 - general purpose
memory
0
SPI write-access enabled
1
SPI write-access disabled
6.12 General purpose memory
UJA1164A allocates 4 bytes of RAM as general purpose registers for storing user
information. The general purpose registers can be accessed via the SPI at address 0x06
to 0x09 (see Table 31).
UJA1164A
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6.13 SPI
6.13.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
•
•
•
•
SCSN: SPI chip select; active LOW
SCK: SPI clock; default level is LOW due to low-power concept (pull-down)
SDI: SPI data input
SDO: SPI data output; floating when pin SCSN is HIGH
Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the
rising edge, as illustrated in Figure 8.
SCSN
SCK
01
02
03
04
N-1
N
sampled
SDI
SDO
X
floating
X
MSB
MSB-1
MSB-2
MSB-3
LSB+1
LSB
MSB
MSB-1
MSB-2
MSB-3
LSB+1
LSB
X
floating
015aaa255
Fig 8.
SPI timing protocol
The SPI data in the UJA1164A is stored in a number of dedicated 8-bit registers. Each
register is assigned a unique 7-bit address. Two bytes must be transmitted to the SBC for
a single register write operation. The first byte contains the 7-bit address along with a
‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write operation (if this bit
is 1, a read operation is assumed and any data on the SDI pin is ignored). The second
byte contains the data to be written to the register.
24- and 32-bit read and write operations are also supported. The register address is
automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as
illustrated in Figure 9.
UJA1164A
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Register Address Range
0x00
0x01
0x02
0x03
0x04
ID=0x05
addr 0000101
A6
A5
A4
A3
A2
Address Bits
A1
0x05
0x06
data
data
data byte 1
0x07
0x7D
0x7F
data
data byte 2
data byte 3
A0 RO
x
x
x
Read-only Bit
x
x
x
x
x
x
x
x
Data Bits
x
x
x
x
x
x
x
Data Bits
Fig 9.
0x7E
x
x
x
Data Bits
x
x
x
015aaa289
SPI data structure for a write operation (16-, 24- or 32-bit)
During an SPI data read or write operation, the contents of the addressed register(s) is
returned via pin SDO.
The UJA1164A tolerates attempts to write to registers that don't exist. If the available
address space is exceeded during a write operation, the data above the valid address
range is ignored (without generating an SPI failure event).
During a write operation, the UJA1164A monitors the number of SPI bits transmitted. If the
number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure
event is captured (SPIF = 1).
If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on
SDI is reflected on SDO from bit 33 onwards.
UJA1164A
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6.13.2 Register map
The addressable register space contains 128 registers with addresses from 0x00 to 0x7F.
An overview of the register mapping is provided in Table 31 to Table 38. The functionality
of individual bits is discussed in more detail in relevant sections of the data sheet.
Table 31.
Overview of primary control registers
Address Register Name
Bit:
7
6
5
4
0x00
Watchdog control
WMC
0x01
Mode control
reserved
0x03
Main status
reserved OTWS
0x04
System event enable
reserved
0x05
Watchdog status
reserved
0x06
Memory 0
GPM[7:0]
0x07
Memory 1
GPM[15:8]
0x08
Memory 2
GPM[23:16]
0x09
Memory 3
GPM[31:24]
0x0A
Lock control
reserved LK6C
Table 32.
Overview of V1 and transceiver control registers
Address Register Name
2
1
0
OTWE
SPIFE
reserved
FNMS
SDMS
WDS
LK3C
LK2C
LK1C
reserved NWP
MC
NMS
LK5C
RSS
LK4C
LK0C
Bit:
7
0x10
3
6
5
4
3
2
1
0
V1 control
reserved
0x1B
Supply status
reserved
V1S
0x1C
Supply event enable
reserved
V1UE
0x20
CAN control
reserved
0x22
Transceiver status
CTS
0x23
Transceiver event enable
reserved
Table 33.
Overview of event capture registers
Address
Register Name
Global event status
reserved
0x61
System event status
reserved
0x62
Supply event status
reserved
0x63
Transceiver event status
reserved
Table 34.
Overview of MTPNV status register
MTPNV status
UJA1164A
Product data sheet
CBSS
CBSE
reserved
reserved
VCS
CFS
CFE
CWE
5
4
3
2
1
PO
reserved OTW
TRXE
0
SUPE
SYSE
SPIF
WDF
V1U
CBS
reserved
4
3
CF
CW
1
0
ECCS
NVMPS
Bit:
7
0x70
reserved
6
0x60
Register Name
CMC
Bit:
7
Address
V1RTC
6
5
WRCNTS
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Table 35.
Overview of Startup control register
Address
Register Name
Bit:
0x73
Startup control
reserved
7
Table 36.
6
Register Name
0x74
SBC configuration control reserved
3
2
1
0
reserved
Bit:
7
6
5
4
V1RTSUC
3
2
1
FNMC
SDMC
reserved
0
Overview of CRC control register
Address
Register Name
Bit:
0x75
MTPNV CRC control
CRCC[7:0]
7
Table 38.
4
Overview of SBC configuration control register
Address
Table 37.
5
RLC
6
5
4
3
2
1
0
5
4
3
2
1
0
Overview of Identification register
Address
Register Name
Bit:
0x7E
Identification
IDS[7:0]
7
6
6.13.3 Register configuration in UJA1164A operating modes
A number of register bits may change state automatically when the UJA1164A switches
from one operating mode to another. This is particularly evident when the UJA1164A
switches to Off mode. These changes are summarized in Table 39. If an SPI transmission
is in progress when the UJA1164A changes state, the transmission is ignored (automatic
state changes have priority).
Table 39.
Symbol
UJA1164A
Product data sheet
Register bit settings in UJA1164A operating modes
Off (power-on
default)
Standby
Normal
Overtemp
Reset
CBS
0
no change
no change
no change
no change
CBSE
0
no change
no change
no change
no change
CBSS
1
actual state
actual state
actual state
actual state
CF
0
no change
no change
no change
no change
CFE
0
no change
no change
no change
no change
CFS
0
actual state
actual state
actual state
actual state
CMC
00
no change
no change
no change
no change
CRCC
00000000
no change
no change
no change
no change
CTS
0
0
actual state
0
0
CW
0
no change
no change
no change
no change
CWE
0
no change
no change
no change
no change
ECCS
actual state
actual state
actual state
actual state
actual state
FNMC
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
FNMS
0
actual state
actual state
actual state
actual state
GPMn
00000000
no change
no change
no change
no change
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Table 39.
Off (power-on
default)
Standby
Normal
Overtemp
Reset
IDS
see Table 29
no change
no change
no change
no change
LKnC
0
no change
no change
no change
no change
MC
100
100
111
don’t care
100
NMS
1
no change
0
no change
no change
NVMPS
actual state
actual state
actual state
actual state
actual state
NWP
0100
no change
no change
0100
0100
OTW
0
no change
no change
no change
no change
OTWE
0
no change
no change
no change
no change
OTWS
0
actual state
actual state
actual state
actual state
PO
1
no change
no change
no change
no change
RLC
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
RSS
00000
no change
no change
10010
reset source
SDMC
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
SDMS
0
actual state
actual state
actual state
actual state
SPIF
0
no change
no change
no change
no change
SPIFE
0
no change
no change
no change
no change
SUPE
0
no change
no change
no change
no change
SYSE
1
no change
no change
no change
no change
TRXE
0
no change
no change
no change
no change
V1RTC
defined by
V1RTSUC
no change
no change
no change
no change
V1RTSUC
MTPNV
MTPNV
MTPNV
MTPNV
MTPNV
V1S
0
actual state
actual state
actual state
actual state
V1UE
0
no change
no change
no change
no change
V1U
0
no change
no change
no change
no change
VCS
0
actual state
actual state
actual state
actual state
WDF
0
no change
no change
no change
no change
WDS
0
actual state
actual state
actual state
actual state
WMC
[1]
no change
no change
no change
[1]
WRCNTS
actual state
actual state
actual state
actual state
actual state
[1]
UJA1164A
Product data sheet
Register bit settings in UJA1164A operating modes …continued
Symbol
001 if SDMC = 1; otherwise 010.
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7. Limiting values
Table 40. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
voltage on pin
Vx
Conditions
x[1]
V(CANH-CANL)
voltage between pin
CANH and pin CANL
Vtrt
transient voltage
Min
Max
Unit
pin V1
[2]
0.2
+6
V
pins TXD, RXD, SDI, SDO, SCK, SCSN, RSTN
[3]
0.2
VV1 + 0.2 V
pin BAT
0.2
+40
V
pins CANH and CANL with respect to any other pin
58
+58
V
40
+40
V
pulse 1
100
-
V
pulse 2a
-
75
V
pulse 3a
150
-
V
-
100
V
6
+6
kV
on pins CANL, CANH, BAT
[4]
pulse 3b
VESD
electrostatic
discharge voltage
IEC 61000-4-2 (150 pF, 330 ) discharge circuit
[5]
on pins CANH and CANL; pin BAT with capacitor
Human Body Model (HBM)
on any pin
[6]
2
+2
kV
on pins BAT
[7]
4
+4
kV
on pins CANH, CANL
[8]
8
+8
kV
100
+100
V
on corner pins
750
+750
V
on any other pin
500
+500
V
40
+150
C
0
+125
C
55
+150
C
Machine Model (MM)
[9]
on any pin
Charged Device Model (CDM)
virtual junction
temperature
Tvj
[11]
when programming the MTPNV cells
storage temperature
Tstg
[10]
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2]
When the device is not powered up, IV1 (max) = 25 mA.
[3]
Maximum voltage should never exceed 6 V.
[4]
Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2.
[5]
Verified by an external test house according to IEC TS 62228, Section 4.3.
[6]
According to AEC-Q100-002.
[7]
Pins stressed to reference group containing all grounds, emulating the application circuit (Figure 14). HBM pulse as specified in
AEC-Q100-002 used.
[8]
Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (Figure 14). HBM pulse as
specified in AEC-Q100-002 used.
[9]
According to AEC-Q100-003.
[10] According to AEC-Q100-011.
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[11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
8. Thermal characteristics
Table 41.
Symbol
Rth(vj-a)
[1]
Thermal characteristics
Parameter
Conditions
[1]
thermal resistance from virtual junction to ambient
Typ
Unit
60
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
9. Static characteristics
Table 42. Static characteristics
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
Vth(det)pon
power-on detection threshold
voltage
VBAT rising
4.2
-
4.55
V
Vth(det)poff
power-off detection threshold
voltage
VBAT falling
2.8
-
3
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
VBAT rising
4.5
-
5
V
Vuvd(CAN)
CAN undervoltage detection
voltage
VBAT falling
4.2
-
4.55
V
IBAT
battery supply current
Normal mode; MC = 111;
CAN Active mode
CAN recessive; VTXD = VV1
-
4
7.5
mA
CAN dominant; VTXD = 0 V
-
46
67
mA
Standby mode; MC = 100;
CWE = 1; CAN Offline mode;
IV1 = 0 A; VBAT = 7 V to 18 V;
40 C < Tvj < 85 C
-
[2]
91
A
additional current in CAN Offline
Bias mode; 40 C < Tvj < 85 C
-
38
55
A
VBAT = 5.5 V to 28 V;
IV1 = 120 mA to 0 mA; VTXD = VV1
4.9
5
5.1
V
VBAT = 5.65 V to 28 V; VTXD = VV1;
IV1 = 150 mA to 0 mA;
4.9
5
5.1
V
VBAT = 5.65 V to 28 V;
IV1 = 100 mA to 0 mA;
VTXD = 0 V; VCANH = 0 V
4.9
5
5.1
V
VBAT = 2 V to 3 V; IV1 = 2 mA
-
-
100
mV
10
mV
Voltage source: pin V1
VO
Vret(RAM)
output voltage
RAM retention voltage difference
VBAT = 2 V to 3 V; IV1 = 200 A
UJA1164A
Product data sheet
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Table 42. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R(BAT-V1)
resistance between pin BAT and
pin V1
VBAT = 4 V to 6 V; IV1 = 120 mA;
Tvj < 150 C
-
-
5
VBAT = 3 V to 4 V; IV1 = 40 mA
-
2.625
-
Vuvd(nom) = 90 %
4.5
-
4.75
V
Vuvd(nom) = 80 %
4
-
4.25
V
Vuvd(nom) = 70 %
3.5
3.75
V
Vuvd(nom) = 60 %
3
-
3.25
V
4.5
-
4.75
V
300
-
150
mA
-
-
59
mA
Vuvd
undervoltage detection voltage
Vuvr
undervoltage recovery voltage
IO(sc)
short-circuit output current
ICAN(int)V1
internal CAN supply current from
V1
Normal mode; MC = 111; CAN
Active mode; CAN dominant;
VTXD = 0 V; short-circuit on bus
lines;
3 V < (VCANH = VCANL) < +18 V
Serial peripheral interface inputs; pins SDI, SCK and SCSN
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VV1 -
-
V
Rpd(SCK)
pull-down resistance on pin SCK
40
60
80
k
Rpu(SCSN)
pull-up resistance on pin SCSN
40
60
80
k
Rpd(SDI)
pull-down resistance on pin SDI
VSDI < Vth(sw)
40
60
80
k
Rpu(SDI)
pull-up resistance on pin SDI
VSDI > Vth(sw)
40
60
80
k
Serial peripheral interface data output; pin SDO
VOH
HIGH-level output voltage
IOH = 4 mA
VV1
0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
ILO(off)
off-state output leakage current
VSCSN = VV1; VO = 0 V to VV1
5
-
+5
A
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VV1 -
-
V
Rpu
pull-up resistance
40
60
80
k
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VV1
0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
Rpu
pull-up resistance
CAN Offline mode
40
60
80
k
pin CANH; RL = 50 to 65
2.75
3.5
4.5
V
pin CANL; RL = 50 to 65
0.5
1.5
2.25
V
High-speed CAN bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
UJA1164A
Product data sheet
CAN Active mode; VTXD = 0 V;
t < tto(dom)TXD
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UJA1164A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
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Table 42. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdom(TX)sym
transmitter dominant voltage
symmetry
Vdom(TX)sym = VV1 VCANH VCANL;
VV1 = 5 V
400
-
+400
mV
VTXsym
transmitter voltage symmetry
VTXsym = VCANH + VCANL;
fTXD = 250 kHz, 1 MHz or 2.5 MHz;
CSPLIT = 4.7 nF
0.9VV1
-
1.1VV1
V
VO(dif)
differential output voltage
RL = 50 to 65
1.5
-
3
V
RL = 45 to 70
1.4
-
3.3
V
RL = 2240
1.5
-
5
V
CAN Active/Listen-only/Offline
Bias mode; VTXD = VV1
50
-
+50
mV
CAN Offline mode
0.2
-
+0.2
V
CAN Active mode; VTXD = VV1
RL = no load
2
0.5VV1 3
V
CAN Offline mode;
RL = no load
0.1
-
+0.1
V
CAN Offline Bias/Listen-only
modes; RL = no load
2
2.5
3
V
pin CANH;
VCANH = 3 V to +27 V
55
-
-
mA
pin CANL;
VCANL = 15 V to +18 V
-
-
+55
mA
3
-
+3
mA
CAN Active/Listen-only modes
0.5
0.7
0.9
V
CAN Offline mode
0.4
0.7
1.15
V
CAN Active/Listen-only modes
4[3]
-
+0.5
V
CAN Offline/Offline Bias modes
4[3]
-
+0.4
V
0.9
-
9.0[3]
V
1.15
-
9.0[3]
V
1
30
60
mV
[3]
[4]
CAN Active mode (dominant);
VTXD = 0 V; VV1 = 4.75 V to 5.5 V;
t < tto(dom)TXD
recessive; RL = no load
VO(rec)
IO(sc)dom
recessive output voltage
dominant short-circuit output
current
CAN Active mode;
VTXD = 0 V; VV1 = 5 V
IO(sc)rec
recessive short-circuit output
current
VCANL = VCANH = 27 V to +32 V;
VTXD = VV1
Vth(RX)dif
differential receiver threshold
voltage
12 V VCANL +12 V;
12 V VCANH +12 V
Vrec(RX)
Vdom(RX)
12 V VCANL +12 V;
12 V VCANH +12 V
receiver recessive voltage
12 V VCANL +12 V;
12 V VCANH +12 V
receiver dominant voltage
CAN Active/Listen-only modes
CAN Offline/Offline Bias modes
Vhys(RX)dif
differential receiver hysteresis
voltage
UJA1164A
Product data sheet
CAN Active/Listen-only modes;
12 V VCANL +12 V;
12 V VCANH +12 V
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
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Table 42. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ri
input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
9
15
28
k
Ri
input resistance deviation
V VCANL +5 V;
V VCANH +5 V
1
-
+1
%
Ri(dif)
differential input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
19
30
52
k
Ci(cm)
common-mode input capacitance
[3]
-
-
20
pF
Ci(dif)
differential input capacitance
[3]
-
-
10
pF
IL
leakage current
5
-
+5
A
VBAT = VV1 = 0 V or VBAT = VV1 =
shorted to ground via 47 k;
VCANH = VCANL = 5 V
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold temperature
167
177
187
C
Tth(rel)otp
overtemperature protection
release threshold temperature
127
137
147
C
Tth(warn)otp
overtemperature protection
warning threshold temperature
127
137
147
C
0
-
0.2VV1
V
60
80
k
Reset output; pin RSTN
VOL
LOW-level output voltage
VV1 = 1.0 V to 5.5 V; pull-up
resistor to VV1 900
Rpu
pull-up resistance
40
Vth(sw)
switching threshold voltage
0.25VV1 -
0.75VV1 V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VV1 -
-
V
-
200
-
MTP non-volatile memory
Ncy(W)MTP
[1]
number of MTP write cycles
VBAT = 6 V to 28 V;
Tvj = 0 C to +125 C
-
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 10.
[3]
Not tested in production; guaranteed by design.
[4]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 16.
UJA1164A
Product data sheet
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Rev. 1 — 23 August 2019
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
aaa-034539
100
IBAT
(μA)
80
(1)
60
40
20
0
-50
-25
0
25
50
75
Tvj (°C)
100
(1) Standby Mode: MC = 100, CWE = 1, CAN Offline mode, VBAT = 12 V, IV1 = 0 A.
Fig 10. UJA1164A typical Standby quiescent current (A)
UJA1164A
Product data sheet
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
10. Dynamic characteristics
Table 43. Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
from VBAT exceeding the power-on
detection threshold until VV1 exceeds
the 90 % undervoltage threshold;
CV1 = 4.7 F
-
2.8
4.7
ms
6
-
54
s
-
-
63
s
-
-
5
ms
Voltage source; pin V1
tstartup
start-up time
td(uvd)
undervoltage detection delay
time
td(uvd-RSTNL)
delay time from undervoltage
detection to RSTN LOW
td(buswake-VOH)
delay time from bus wake-up to HIGH = 0.8VO(V1);
HIGH-level output voltage
IV1 100 mA
undervoltage on V1
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO; see Figure 13
tcy(clk)
clock cycle time
250
-
-
ns
tSPILEAD
SPI enable lead time
50
-
-
ns
tSPILAG
SPI enable lag time
50
-
-
ns
tclk(H)
clock HIGH time
100
-
-
ns
tclk(L)
clock LOW time
100
-
-
ns
tsu(D)
data input set-up time
50
-
-
ns
th(D)
data input hold time
50
-
-
ns
tv(Q)
data output valid time
pin SDO; CL = 20 pF
-
-
50
ns
td(SDI-SDO)
SDI to SDO delay time
SPI address bits and read-only bit;
CL = 20 pF
-
-
50
ns
tWH(S)
chip select pulse width HIGH
pin SCSN
250
-
-
ns
td(SCKL-SCSNL)
delay time from SCK LOW to
SCSN LOW
50
-
-
ns
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXD-busdom)
delay time from TXD to bus
dominant
[2]
-
80
-
ns
td(TXD-busrec)
delay time from TXD to bus
recessive
[2]
-
80
-
ns
td(busdom-RXD)
delay time from bus dominant
to RXD
[2]
-
105
-
ns
td(busrec-RXD)
delay time from bus recessive
to RXD
[2]
-
120
-
ns
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
tbit(TXD) = 200 ns
[3]
-
-
255
ns
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
tbit(TXD) = 200 ns
[3]
-
-
255
ns
tbit(bus)
transmitted recessive bit width
tbit(TXD) = 500 ns
[3]
435
-
530
ns
tbit(TXD) = 200 ns
[3]
155
-
210
ns
UJA1164A
Product data sheet
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Table 43. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
tbit(RXD)
trec
twake(busdom)
twake(busrec)
Parameter
Conditions
bit time on pin RXD
receiver timing symmetry
bus dominant wake-up time
bus recessive wake-up time
Min
Typ
Max
Unit
tbit(TXD) = 500 ns
[3]
400
-
550
ns
tbit(TXD) = 200 ns
[3]
120
-
220
ns
tbit(TXD) = 500 ns
65
-
+40
ns
tbit(TXD) = 200 ns
45
-
+15
ns
first pulse (after first recessive) for
wake-up on pins CANH and CANL;
CAN Offline mode
0.5
-
1.8
s
second pulse for wake-up on pins
CANH and CANL
0.5
-
1.8
s
first pulse for wake-up on pins CANH
and CANL; CAN Offline mode
0.5
-
1.8
s
second pulse (after first dominant) for
wake-up on pins CANH and CANL
0.5
-
1.8
s
tto(wake)bus
bus wake-up time-out time
between first and second dominant
pulses; CAN Offline mode
0.8
-
10
ms
tto(dom)TXD
TXD dominant time-out time
CAN Active mode;
VTXD = 0 V
2.7
-
3.3
ms
tto(silence)
bus silence time-out time
recessive time measurement started
in all CAN modes
0.95
-
1.17
s
td(busact-bias)
delay time from bus active to
bias
-
-
200
s
tstartup(CAN)
CAN start-up time
-
-
220
s
when switching to Active mode
(CTS = 1)
Pin RXD: event capture timing (valid in CAN Offline mode only)
td(event)
event capture delay time
CAN Offline mode
0.9
-
1.1
ms
tblank
blanking time
when switching from Offline to
Active/Listen-only mode
-
-
25
s
ttrig(wd)1
watchdog trigger time 1
Normal mode; watchdog Window
mode only
[4]
0.45 NWP[5]
0.55 ms
NWP[5]
ttrig(wd)2
watchdog trigger time 2
Normal/Standby mode
[6]
0.9
NWP[5]
1.11 ms
NWP[5]
[7]
-
-
0.2
ms
RLC = 00
20
-
25
ms
RLC = 01
10
-
12.5
ms
RLC = 10
3.6
-
5
ms
RLC = 11
1
-
1.5
ms
18
-
-
s
Watchdog
td(SCSNH-RSTNL) delay time from SCSN HIGH to rising edge to falling edge; watchdog
RSTN LOW
in window mode, triggered in the
first half of the watchdog period
(before ttrig(wd)1)
Pin RSTN: reset pulse width
tw(rst)
reset pulse width
output pulse width
input pulse width
MTP non-volatile memory
UJA1164A
Product data sheet
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UJA1164A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
Table 43. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; RL = R(CANH-CANL) = 60 ; all voltages are defined with respect to ground;
positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tret(data)
data retention time
Tvj = 90 C
20
-
-
year
td(MTPNV)
MTPNV delay time
before factory presets are restored;
VBAT = 6 V to 28 V
0.9
-
1.1
s
tprog(MTPNV)
MTPNV programming time
correct CRC code received at address
0x75; VBAT = 6 V to 28 V
10
12
14
ms
MC = 111; delay before CAN
transceiver gets activated after the
SBC switches to Normal mode
-
-
320
s
Mode transition
td(act)norm
[1]
normal mode activation delay
time
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 11 and Figure 15.
[3]
See Figure 12 and Figure 15.
[4]
A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog
period (or in the first half of the watchdog period).
[5]
The nominal watchdog period is programmed via the NWP control bits.
[6]
The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
ttrig(wd)2 after the start of the watchdog period (watchdog overflows).
[7]
Not tested in production; guaranteed by design.
UJA1164A
Product data sheet
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Mini high-speed CAN system basis chip with Standby mode &
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HIGH
TXD
70 %
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
HIGH
70 %
RXD
30 %
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
aaa-029311
Fig 11. CAN transceiver timing diagram
70 %
TXD
30 %
30 %
td(TXDL-RXDL)
5 x tbit(TXD)
tbit(TXD)
0.9 V
VO(dif)
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Fig 12. CAN FD timing definitions according to ISO 11898-2:2016
UJA1164A
Product data sheet
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UJA1164A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
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SCSN
tSPILEAD
tWH(S)
tclk(H) tclk(L)
td(SCKL-SCSNL)
SCK
tSPILAG
tcy(clk)
X
th(D)
tsu(D)
SDI
X
th(D)
tv(Q)(2)
MSB
LSB
X
td(SDI-SDO)(1)
SDO
X
MSB
LSB
X
time
aaa-027898
(1) The SDI to SDO delay time is valid for SPI address bits and the read-only bit.
(2) The data output valid time is valid for the SPI data bits.
Fig 13. SPI timing diagram
UJA1164A
Product data sheet
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NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
11. Application information
11.1 Application diagram
BAT
22 μF
(1)
44 μF
BAT
V1
10
3
5
14
6
UJA1164A
8
11
GND
4
2
13
12
CANH
RT (2)
1
RSTN
RSTN
VCC
MICROCONTROLLER
SCSN
SDO
SCK
standard
μC ports
SDI
RXD
TXD
RXD
TXD
VSS
CANL
RT (2)
e.g.
4.7 nF
aaa-023213
(1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 6.8 F).
(2) For bus line end nodes, RT = 60 in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’
termination of e.g. RT = 1.3 k can be used, if required by the OEM.
Fig 14. Typical application using the UJA1164A
11.2 Application hints
Further information on the application of the UJA1164A can be found in the NXP
application hints document AH1902 Application Hints - Mini high speed CAN system basis
chips UJA116xA.
UJA1164A
Product data sheet
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Rev. 1 — 23 August 2019
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12. Test information
TXD
CANH
RL
60 Ω
RXD
CL
100 pF
CANL
15 pF
aaa-030850
Fig 15. Timing test circuit for CAN transceiver
TXD
CANH
30 Ω
fTXD
CSPLIT
4.7 nF
RXD
30 Ω
CANL
aaa-030851
Fig 16. Test circuit for measuring transceiver driver symmetry
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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13. Package outline
HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
B
D
A
A
E
A1
c
terminal 1
index area
detail X
e1
terminal 1
index area
e
v
w
b
1
7
C
C A B
C
y1 C
y
L
k
Eh
14
8
Dh
0
2.5
Dimensions
Unit
mm
5 mm
scale
A
A1
b
max 1.00 0.05 0.35
nom 0.85 0.03 0.32
min 0.80 0.00 0.29
c
D
Dh
E
Eh
0.2
4.6
4.5
4.4
4.25
4.20
4.15
3.1
3.0
2.9
e
e1
1.65
1.60 0.65
1.55
3.9
k
L
0.35 0.45
0.30 0.40
0.25 0.35
v
0.1
w
y
0.05 0.05
y1
0.1
sot1086-2
References
Outline
version
IEC
JEDEC
JEITA
SOT1086-2
---
MO-229
---
European
projection
Issue date
10-07-14
10-07-15
Fig 17. Package outline SOT1086-2 (HVSON14)
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14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 44 and 45
Table 44.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 45.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Soldering of HVSON packages
Section 15 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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17. Appendix: ISO 11898-2:201x parameter cross-reference list
Table 46.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
VO(rec)
recessive output voltage
Differential output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
Dominant state differential input voltage range
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
Ri
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
tRec
trec
receiver timing symmetry
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Table 46.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
tFilter
twake(busdom)[1] bus dominant wake-up time
HS-PMA bus biasing control timings
CAN activity filter time, long
twake(busrec)[1]
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Timeout for bus inactivity
tSilence
tto(silence)
bus silence time-out time
Bus Bias reaction time
tBias
td(busact-bias)
delay time from bus active to bias
CAN activity filter time, short
Wake-up timeout, short
Wake-up timeout, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
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18. Revision history
Table 47.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UJA1164A v.1
20190823
Product data sheet
-
-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
UJA1164A
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
6.1.1.7
6.1.2
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.3.1
6.3.2
6.3.3
6.4
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.6.1.4
6.6.2
6.6.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Designed for automotive applications. . . . . . . . 1
Low-drop voltage regulator for 5 V microcontroller
supply (V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Power Management . . . . . . . . . . . . . . . . . . . . . 2
System control and diagnostic features . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
System controller . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 7
Forced Normal mode . . . . . . . . . . . . . . . . . . . . 7
Hardware characterization for the UJA1164A
operating modes . . . . . . . . . . . . . . . . . . . . . . . . 8
System control registers . . . . . . . . . . . . . . . . . . 8
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Software Development mode . . . . . . . . . . . . . 12
Watchdog behavior in Window mode . . . . . . . 12
Watchdog behavior in Timeout mode . . . . . . . 12
Watchdog behavior in Autonomous mode . . . 12
System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Characteristics of pin RSTN . . . . . . . . . . . . . . 13
Selecting the output reset pulse width . . . . . . 13
Reset sources. . . . . . . . . . . . . . . . . . . . . . . . . 14
Global temperature protection . . . . . . . . . . . . 14
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 14
Battery supply voltage (VBAT) . . . . . . . . . . . . . 14
Low-drop voltage supply for 5 V microcontroller
(V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High-speed CAN transceiver . . . . . . . . . . . . . 15
CAN operating modes . . . . . . . . . . . . . . . . . . 16
CAN Active mode . . . . . . . . . . . . . . . . . . . . . . 16
CAN Listen-only mode . . . . . . . . . . . . . . . . . . 17
CAN Offline and Offline Bias modes. . . . . . . . 17
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 18
CAN standard wake-up . . . . . . . . . . . . . . . . . 19
CAN control and Transceiver status registers 20
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.8
CAN fail-safe features . . . . . . . . . . . . . . . . . . 21
TXD dominant timeout . . . . . . . . . . . . . . . . . . 21
Pull-up on TXD pin . . . . . . . . . . . . . . . . . . . . . 21
V1 undervoltage event . . . . . . . . . . . . . . . . . . 21
Loss of power at pin BAT . . . . . . . . . . . . . . . . 21
Wake-up and interrupt event diagnosis via pin
RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.8.1
Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 22
6.8.2
Event status and event capture registers. . . . 23
6.9
Non-volatile SBC configuration . . . . . . . . . . . 25
6.9.1
Programming MTPNV cells . . . . . . . . . . . . . . 25
6.9.1.1
Calculating the CRC value for MTP programming
26
6.9.2
Restoring factory preset values . . . . . . . . . . . 27
6.10
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.11
Lock control register. . . . . . . . . . . . . . . . . . . . 28
6.12
General purpose memory . . . . . . . . . . . . . . . 28
6.13
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.13.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.13.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.13.3
Register configuration in UJA1164A operating
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34
8
Thermal characteristics . . . . . . . . . . . . . . . . . 35
9
Static characteristics . . . . . . . . . . . . . . . . . . . 35
10
Dynamic characteristics. . . . . . . . . . . . . . . . . 40
11
Application information . . . . . . . . . . . . . . . . . 45
11.1
Application diagram . . . . . . . . . . . . . . . . . . . . 45
11.2
Application hints. . . . . . . . . . . . . . . . . . . . . . . 45
12
Test information . . . . . . . . . . . . . . . . . . . . . . . 46
12.1
Quality information . . . . . . . . . . . . . . . . . . . . . 46
13
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47
14
Handling information . . . . . . . . . . . . . . . . . . . 48
15
Soldering of SMD packages. . . . . . . . . . . . . . 48
15.1
Introduction to soldering. . . . . . . . . . . . . . . . . 48
15.2
Wave and reflow soldering. . . . . . . . . . . . . . . 48
15.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 48
15.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 49
16
Soldering of HVSON packages . . . . . . . . . . . 50
17
Appendix: ISO 11898-2:201x parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . . 51
18
Revision history . . . . . . . . . . . . . . . . . . . . . . . 53
19
Legal information . . . . . . . . . . . . . . . . . . . . . . 54
19.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 54
19.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
continued >>
UJA1164A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
56 of 57
UJA1164A
NXP Semiconductors
Mini high-speed CAN system basis chip with Standby mode &
watchdog
19.3
19.4
20
21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
55
55
56
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2019
Document identifier: UJA1164A
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