NB2304A

NB2304A 3.3 V Zero Delay Clock Buffer The NB2304A is a versatile, 3.3 V zero delay buffer designed to distribute high−speed clocks in PC, workstation, datacom, telecom and other high−performance applications. It is available in an 8 pin package. The part has an on−chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input−to−output propagation delay is guaranteed to be less than 250 ps, and the output−to−output skew is guaranteed to be less than 200 ps. The NB2304A has two Banks of two outputs each. Multiple NB2304A devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 500 ps. The NB2304A is available in two different configurations (Refer to NB2304A Configurations Table). The NB2304Ax1* is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The NB2304Ax1H is the high−drive version of the −1 and the rise and fall times on this device are much faster. The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X frequencies on each output Bank. The exact configuration and output frequencies depend on which output drives the feedback pin. Features http://onsemi.com MARKING DIAGRAM* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 XXXX ALYW G XXXX A L Y W G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. • Zero Input − Output Propagation Delay, Adjustable by Capacitive • • • • • • • • • • • • Load on FBK Input Multiple Configurations − Refer to NB2304A Configurations Table Input Frequency Range: 15 MHz to 133 MHz Multiple Low−Skew Outputs Output−Output Skew < 200 ps Device−Device Skew < 500 ps Two Banks of Four Outputs Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H) Available in Space Saving, 8 pin 150 mil SOIC Package 3.3 V Operation Advanced 0.35 m CMOS Technology Industrial Temperature Available These are Pb−Free Devices ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. *x = C for Commercial; I for Industrial. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 5 1 Publication Order Number: NB2304A/D NB2304A FBK CLKA1 REF PLL CLKA2 B2 Extra Divider (−2) CLKB1 CLKB2 Figure 1. Basic Block Diagram (see Figures 11 and 12 for device specific Block Diagrams) Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial) Device NB2304Ax1 NB2304Ax1H NB2304Ax2 NB2304Ax2 Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Frequency Reference Reference Reference 2 X Reference Bank B Frequency Reference Reference Reference B2 Reference REF CLKA1 CLKA2 GND 1 2 8 7 FBK VDD CLKB2 CLKB1 Table 2. PIN DESCRIPTION Pin # 1 2 3 4 5 Pin Name REF (Note 1) CLKA1 (Note 2) CLKA2 (Note 2) GND CLKB1 (Note 2) CLKB2 (Note 2) VDD FBK Description Input reference frequency, 5 V tolerant input. Buffered clock output, Bank A. Buffered clock output, Bank A. Ground. Buffered clock output, Bank B. Buffered clock output, Bank B. 3.3 V supply. PLL feedback input. NB2304A 3 4 6 5 Figure 2. Pin Configuration 6 7 8 1. Weak pulldown. 2. Weak pulldown on all outputs. http://onsemi.com 2 NB2304A Table 3. MAXIMUM RATINGS Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Maximum Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL−STD−883, Method 3015) Min −0.5 −0.5 −0.5 −65 Max +7.0 VDD + 0.5 7 +150 260 150 > 2000 Unit V V V °C °C °C V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Table 4. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, 15 MHz to 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance (Note 3) Commercial Industrial Description Min 3.0 0 −40 Max 3.6 70 85 30 15 7 Unit V °C pF pF pF 3. Applies to both REF Clock and FBK. Table 5. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current VIN = 0 V VIN = VDD IOL = 8 mA (−1, −2) IOL = 12 mA (−1H) IOH = −8 mA (−1, −2) IOH = −12 mA (−1H) Unloaded outputs 100 MHz REF Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (−1, −2) Unloaded outputs, 33 MHz REF (−1, −2) 2.4 45 32 18 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V mA mA V V mA http://onsemi.com 3 NB2304A Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES Parameter t1 Description Output Frequency Duty Cycle = (t2 / t1) * 100 (all devices) Test Conditions 30 pF load (all devices) 15 pF load (−1, −2) Measured at 1.4 V, FOUT = 66.66 MHz 30 pF load Measured at 1.4 V, FOUT v 50 MHz 15 pF load t3 Output Rise Time (−1, −2) Measured between 0.8 V and 2.0 V 30 pF load Measured between 0.8 V and 2.0 V 15 pF load Output Rise Time (−1H) t4 Output Fall Time (−1, −2) Measured between 0.8 V and 2.0 V 30 pF load Measured between 2.0 V and 0.8 V 30 pF load Measured between 2.0 V and 0.8 V 15 pF load Output Fall Time (−1H) t5 Output−to−Output Skew on same Bank (−1, −2) Output−to−Output Skew (−1H) Output Bank A−to−Output Bank B Skew (−1) Output Bank A−to−Output Bank B Skew (−2) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge Device−to−Device Skew Output Slew Rate Cycle−to−Cycle Jitter (−1, −1H) Measured between 2.0 V and 0.8 V 30 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Cycle−to−Cycle Jitter (−2) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load tLOCK PLL Lock Time Stable power supply, valid clock presented on REF and FBK pins 1 175 200 100 400 375 1.0 ms ps 0 0 Min 15 15 40.0 45.0 50.0 50.0 Typ Max 133 133.3 60.0 55.0 2.20 1.50 1.50 2.20 1.50 1.25 200 200 200 400 ±250 500 ps ps V/ns ps ps ns ns Unit MHz % http://onsemi.com 4 NB2304A Table 7. ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL TEMPERATURE DEVICES Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Supply Current VIN = 0 V VIN = VDD IOL = 8 mA (−1, −2) IOL = 12 mA (−1H) IOH = −8 mA (−1, −2) IOH = −12 mA (−1H) Unloaded outputs 100 MHz REF Select inputs at VDD or GND Unloaded outputs, 66 MHz REF (−1, −2) Unloaded outputs, 33 MHz REF (−1, −2) 2.4 45 35 20 2.0 50.0 100.0 0.4 Test Conditions Min Max 0.8 Unit V V mA mA V V mA http://onsemi.com 5 NB2304A Table 8. SWITCHING CHARACTERISTICS FOR INDUSTRIAL TEMPERATURE DEVICES (All parameters are specified with loaded outputs) Parameter t1 t1 Description Output Frequency Duty Cycle = (t2 / t1) * 100 (all devices) Test Conditions 30 pF load (all devices) 15 pF load (−1, −2) Measured at 1.4 V, FOUT v 66.66 MHz 30 pF load Measured at 1.4 V, FOUT v 50 MHz 15 pF load t3 Output Rise Time (−1, −2) Measured between 0.8 V and 2.0 V 30 pF load Measured between 0.8 V and 2.0 V 15 pF load Output Rise Time (−1H) t4 Output Fall Time (−1, −2) Measured between 0.8 V and 2.0 V 30 pF load Measured between 2.0 V and 0.8 V 30 pF load Measured between 2.0 V and 0.8 V 15 pF load Output Fall Time (−1H) t5 Output−to−Output Skew on same Bank (−1, −2) Output−to−Output Skew (−1H) Output Bank A−to−Output Bank B skew (−1) Output Bank A−to−Output Bank B skew (−2) t6 t7 t8 tJ Delay, REF Rising Edge to FBK Rising Edge Device−to−Device Skew Output Slew Rate Cycle−to−Cycle Jitter (−1, −1H) Measured between 2.0 V and 0.8 V 30 pF load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8 V and 2.0 V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Cycle−to−Cycle Jitter (−2) Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 66.67 MHz, loaded outputs, 15 pF load tLOCK PLL Lock Time Stable power supply, valid clock presented on REF and FBK pins 1 180 200 100 400 380 1.0 ms ps 0 0 Min 15 15 40.0 45.0 50.0 50.0 Typ Max 100 133.3 60.0 55.0 2.50 1.50 1.50 2.50 1.50 1.25 200 200 200 400 ±250 500 ps ps V/ns ps ps ns ns Unit MHz % http://onsemi.com 6 NB2304A Zero Delay and Skew Control For applications requiring zero input−output delay, all outputs must be equally loaded. 1500 REF INPUT TO CLKA/CLKB DELAY (ps) 1000 500 0 −500 −1000 −1500 −30 −25 −20 −15 −10 To close the feedback loop of the NB2304A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in Figure 3. For applications requiring zero input−output delay, all outputs including the one providing feedback should be equally loaded. If input−output delay adjustments are required, use Figure 3 to calculate loading differences between the feedback output and remaining outputs. For zero output−output skew, be sure to load outputs equally. −5 0 5 10 15 20 25 30 OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF) Figure 3. REF Input to CLKA/CLKB Delay vs. Difference in Loading between FBK Pin and CLKA/CLKB Pins SWITCHING WAVEFORMS t1 t2 1.4 V 1.4 V 1.4 V OUTPUT 2.0 V 0.8 V t3 2.0 V 0.8 V t4 0V 3.3 V Figure 4. Duty Cycle Timing Figure 5. All Outputs Rise/Fall Time OUTPUT OUTPUT 1.4 V 1.4 V t5 INPUT OUTPUT t6 V DD 2 V DD 2 Figure 6. Output − Output Skew Figure 7. Input − Output Propagation Delay FBK_Device 1 FBK_Device 2 t7 V DD 2 V DD 2 Figure 8. Device − Device Skew http://onsemi.com 7 NB2304A TEST CIRCUITS VDD VDD 0.1 mF VDD CLOAD VDD 0.1 mF GND GND 0.1 mF 0.1 mF 1 kW OUTPUTS 1 kW VDD GND GND 10 pF OUTPUTS Figure 9. Test Circuit #1 Figure 10. Test Circuit #2 For parameter t8 (output slew rate) on −1H devices BLOCK DIAGRAMS FBK FBK CLKA1 CLKA2 CLKA2 REF PLL CLKB1 REF PLL B2 CLKB1 CLKA1 CLKB2 CLKB2 Figure 11. NB2304Ax1 and NB2304Ax1H Figure 12. NB2304Ax2 http://onsemi.com 8 NB2304A ORDERING INFORMATION Device NB2304AC1DG NB2304AC1DR2G NB2304AI1DG NB2304AI1DR2G NB2304AC1HDG NB2304AC1HDR2G NB2304AI1HDG NB2304AI1HDR2G NB2304AC2DG NB2304AC2DR2G NB2304AI2DG NB2304AI2DR2G Marking 4C1 4C1 4I1 4I1 4C1H 4C1H 4I1H 4I1H 4C2 4C2 4I2 4I2 Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) SOIC−8 (Pb−Free) Shipping† 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel 98 Units / Rail 2500 Tape & Reel Availability Now Now Now Now Now Now Now Now Now Now Now Now †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB2304A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AG − X− A 8 5 B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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