NB3N2304NZ

NB3N2304NZ 3.3V 1:4 Clock Fanout Buffer Description The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer, designed for high speed clock distribution such as in PCI−X applications. The NB3N2304NZ guarantees low output−to−output skew. Optimal design, layout and processing minimizes skew within a device and from device−to−device. The Output Enable (OE) pin forces the outputs LOW when LOW. Features http://onsemi.com MARKING DIAGRAM* NB3N 2304 YWWA G • • • • • • • • Input/Output Clock Frequency up to 140 MHz Low Skew Outputs (100 ps) Output Enable Operating Range: VDD = 3.0 V to 3.6 V Ideal for PCI−X and networking clocks Packaged in 8−pin TSSOP, 4.4 mm x 3 mm Industrial Temperature Range These are Pb−Free Devices* TSSOP−8 DT SUFFIX CASE 948S 1 DFN8 TBD SUFFIX CASE 506AA A Y WW G 1 XX M 4 = Assembly Location = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 0 1 Publication Order Number: NB3N2304NZ/D NB3N2304NZ OE Logic Control Q1 Q2 IN Q3 Q4 IN OE Q1 GND 1 2 3 4 8 7 6 5 Q4 Q3 VDD Q2 Figure 2. Block Diagram Figure 3. NB3N2304NZ Package Pinout (Top View) Table 1. PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 Pin Name IN OE Q1 GND Q2 VDD Q3 Q4 Type LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Output Power (LV)CMOS/(LV)TTL Input Power (LV)CMOS/(LV)TTL Output (LV)CMOS/(LV)TTL Input Clock Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs are forced to logic LOW when OE is forced LOW. Clock Output 1 Negative Supply Voltage; Connect to Ground, 0 V Clock Output 2 Positive Supply Voltage (3.0 V to 3.6 V) Clock Output 3 Clock Output 4 Description Table 2. OE, OUTPUT ENABLE FUNCTION TABLE Inputs IN L H L H OE L L H H L L L H Outputs http://onsemi.com 2 NB3N2304NZ Table 3. ATTRIBUTES Characteristics ESD Protection Human Body Model Machine Model Value > 2kV > 200 V Level 1 UL 94 V−O @ 0.125 in 480 Devices Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Table 4. MAXIMUM RATINGS Symbol VDD VI TA Tstg qJA qJC TSOL Parameter Positive Power Supply Input Voltage Operating Temperature Range, Industrial Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Wave Solder Pb−Free (Note 2) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 265 Condition 1 GND = 0 V Condition 2 Rating VDD + 0.5V GND – 0.5 v VI v VDD + 0.5 w −40 to v +85 −65 to +150 Unit V V °C °C °C/W °C/W °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. EDEC standard multilayer board − 2S2P (2 signal, 2 power). http://onsemi.com 3 NB3N2304NZ Table 5. DC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C Symbol IDD VOH VOL VIH VIL IIH IIL CIN Characteristic Power Supply Current @ 66.66 MHz, Unloaded Outputs Output HIGH Voltage Output LOW Voltage Input HIGH Voltage, IN and OE (Note 3) Input LOW Voltage, IN and OE (Note 3) Input HIGH Current, VIN = VDD Input LOW Current, VIN = 0 V Input Capacitance, IN, OE −50 −100 5 − IOH = −24 mA −IOH = −12 mA −IOL = 24 mA −IOL = 12 mA 2.0 0.8 50 100 7 2.0 2.4 0.8 0.55 Min Typ 12 Max 25 Unit mA V V V V mA mA pF NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. IN input has a threshold voltage of VDD/2. Table 6. AC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 4) (Figure 4) Symbol fin tDCskew tr/tf tpd tskew tpu Input Clock Frequency Duty Cycle Skew = t2 ÷ t1 (Figure 4) Measured at 1.5 V Output Rise and Fall Times; 0.8 V to 2.0 V Propagation Delay, IN−to−Qn (Note 5) Output−to−Output Skew; (Note 5) Powerup Time for VDD to Reach Minimum Specified Voltage 0.05 2.5 Characteristic Min DC 40 50 0.9 3.5 Typ Max 140 60 1.5 5 100 50 Unit MHz % ns ns ps ms NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. All outputs loaded equally with CL = 25 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between VDD and GND. 5. Measured on rising edges at VDD B 2; all outputs with equal loading. http://onsemi.com 4 NB3N2304NZ Duty Cycle Timing t1 t2 1.5 V All Outputs Rise/Fall Time 2.0 V 0.8 V OUTPUT tr 2.0 V 0.8 V tf 3.3 V 0V 1.5 V 1.5 V Output−Output Skew 1.5 V OUTPUT OUTPUT tSKEW Input−Output Propagation Delay VDD/2 INPUT 1.5 V OUTPUT tpd VDD/2 Figure 4. Switching Waveforms ORDERING INFORMATION Device NB3N2304NZDTG NB3N2304NZDTR2G NB3N2304NZMNR4G* Package TSSOP−8 (Pb−Free) TSSOP−8 (Pb−Free) DFN8 (Pb−Free) Shipping † 100 Units / Rail 2500 / Tape & Reel 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Contact a sales representative. http://onsemi.com 5 NB3N2304NZ PACKAGE DIMENSIONS TSSOP−8 CASE 948S−01 ISSUE B 8x K REF 0.10 (0.004) M 0.20 (0.008) T U S TU S V S L PIN 1 IDENT 1 4 B − U− J J1 0.20 (0.008) T U S A −V− C 0.076 (0.003) D −T− SEATING PLANE G P N P1 DETAIL E N http://onsemi.com 6 É ÉÉÉÉ ÇÇÇ ÉÉÉÉ ÇÉÉÉ ÇÇ K1 K 0.25 (0.010) M F DETAIL E 2X L/2 8 5 SECTION N−N −W− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS MIN MAX 2.90 3.10 4.30 4.50 −−− 1.10 0.05 0.15 0.50 0.70 0.65 BSC 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ −−− 2.20 −−− 3.20 INCHES MIN MAX 0.114 0.122 0.169 0.177 −−− 0.043 0.002 0.006 0.020 0.028 0.026 BSC 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −−− 0.087 −−− 0.126 DIM A B C D F G J J1 K K1 L M P P1 NB3N2304NZ PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D D A B PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.20 −−− 0.25 0.35 E 2X 0.10 C 2X 0.10 C 0.10 C 8X 0.08 C SEATING PLANE A1 e/2 1 8X 4 L K ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ D2 8 TOP VIEW A (A3) C e SIDE VIEW E2 5 8X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW http://onsemi.com 7 NB3N2304NZ/D