NB4N441MNGEVB

NB4N441MNGEVB NB4N441MNGEVB Evaluation Board User's Manual Device Name: NB4N441MN http://onsemi.com EVAL BOARD USER’S MANUAL Description Board Features The NB4N441MNG is a precision clock PLL based synthesizer which generates select differential LVPECL clock output frequencies from 12.5 MHz to 425 MHz. A Serial Peripheral Interface (SPI) is used to configure the device to produce output frequencies from a single 27 MHz crystal input reference by programming three internal registers, P (pre−scale), M (PLL Feedback Divider), and N (Output Divider) using a three line LVTTL/LVCMOS Serial Data Interface (SDI) consisting of a SERIAL DATA (SDATA) input, a SERIAL CLOCK (SCLOCK) input, and a SERIAL LOAD (SLOAD). The NB4N441MNGEVB Evaluation board is designed to provide a flexible and convenient platform to quickly program, evaluate and verify the performance and operation of the NB4N441MNG device under test: With the device removed, this NB4N441MNGEVB Evaluation board is designed accept a 24 LD QFN GCI socket (M&M Specialties, Inc., 1−800−892−8760, www.mmspec.com, Dwg No.50−000−00306) to permit use as an insertion test fixture. • On board 27 MHz crystal source, or input external • • • • clock source (SMA) On board serial data loader with 16−bit DIP switches, or externally serial program through SMA connectors. PLL In Lock LED status indicator. 3.3 V split−power supply operation (banana jack and anvil supply connectors for VCC, SMAGND, and DUTGND) LVPECL differential output signals via SMA connectors with provision for termination resistors. Contents Description Board Features Board Layout Map Test and Measurement Setup Procedures Appendix 1: Device Information Appendix 2: Schematics Appendix 3: Bill Of Materials, Lamination Stackup FRONT BACK Figure 1. NB4N441MNGEVB Evaluation Board © Semiconductor Components Industries, LLC, 2012 February, 2012 − Rev. 1 1 Publication Order Number: EVBUM2073/D NB4N441MNGEVB BOARD LAYOUT MAP SW1 OUTPUT EN VCC SMAGND DUTGND DEVICE UNDER TEST D3 OUTPUT EN LED THEVENIN PARALLEL RESISTOR PADS (Unpopulated) J2 CLK (out) J12 JUMPERS J4 CLK (out) J1 INPUT CLK J11 OUTPUT EN J8 PLL LOCKED J7 SLOAD PLL LOCKED LED J9 SDATA PLL not LOCKED LED J10 SCLOCK LED for LEDS and PLD PWR SEL[3:0] NOT USED LED for Standard Protocols (SW5 switch R) P[4:0] M[9:0] N[2:0] SW8 RECONFIGURE LED for CUSTOM FREQUENCIES FRONT 27 MHz Crystal SMAGND DUTGND VCC Through Hole of INPUT CLOCK trace J5 BACK Figure 2. Board Layout Map http://onsemi.com 2 NB4N441MNGEVB TEST AND MEASUREMENT SETUP AND PROCEDURE Step 1: Equipment (or equivalent) ready for use. NOTE: If an external clock reference is used, then dismount the crystal and connect a clock signal (10 MHz − 50 MHz, 3.3 VPP amplitude) with LEVELS OFFSET −1.3 V: as +2.0 V HIGH and −1.3 V LOW into CLK/XTAL1 (J1). Also short from the bottom side “through hole trace” of INPUT CLOCK to J5 (not J3). Do not drive XTAL2. Termination of the signal generator may be needed with 50 W to SMA ground. 4. Program SDI: The P, M, and N internal registers may be programmed by (A) the onboard PLD or (B) by using the three line 3.3 VPP amplitude (offset LVTTL/LVCMOS) Serial Data Interface (SDI) consisting of a SERIAL DATA (SDATA) input, a SERIAL CLOCK (SCLOCK) input, and a SERIAL LOAD (SLOAD) as follows: A. Onboard PLD 1. Insure all 4 of the J12 (441 CONFIG) jumpers are all installed connecting the PLD output to the Device 2. Insure JP1 LED/PLD indicates power is applied to the PLD (LED on); 3. Insure J3 (external CLOCK line from J1) is open, not LOADED, DRIVEN, or shorted; 4. Insure SW5 (LEFT: CUSTOM 441, RIGHT:STANDARD 442) select is set to the LEFT (bypassing SW2, SEL[3:0]. Note LED will light for “CUSTOM FREQUENCIES”. 5. Set SW4, SW6, and SW7 rocker switches to desired P, M, and N programming values: UP =0 LOGIC LOW (LED indicator OFF); DOWN = 1 LOGIC HIGH (LED indicator ON). 6. Load program values by depressing momentary switch SW8, or send a pulse signal (125 ns min) through J13 SMA connector (when installed) with OFFSET LVCMOS/LVTTL LEVELS of +2.0 V HIGH and −1.3 V LOW. B. External SDI 1. See datasheet DC Table, AC Table, as well as Figures 5 and 6. 2. To use the SDI (serial data input) port, generate and input SCLOCK, SDATA, and SLOAD signals with OFFSET LVCMOS/LVTTL LEVELS of +2.0 V HIGH and −1.3 V LOW. The SCLOCK signal will sample the information presented on SDATA line. Values are loaded and indexed into a 18 bit shift register. The register shifts once per rising edge of the SCLOCK input. The serial input SDATA bits must each meet setup and 1. Agilent Signal Generator #33250A for CLK input 2. Tektronix TDS8000 Oscilloscope or Frequency Counter 3. Agilent #6624A DC Power Supply 4. Digital Voltmeter 5. Matched high−speed cables with SMA connectors Step 2: Lab Setup Procedure for Split Supplies (into LOW impedance 50 W equipment or probes) 1. Output Enable OFF: Switch SW1 (UP) or externally LOW through J11 (offset LVCMOS/ LVTTL of 2.0 V HIGH and −1.3 V LOW) to disable the output during setup. LED D3 indicator will be off to indicate disabled output. 2. Supplies: Connect a “split” power supply to the evaluation board for 3.3 V operation as follows: VCC (RED banana jack or clip anvil) at +2.0 V SMAGND (YELLOW banana jack or clip anvil) at 0 V DUTGND (BLACK banana jack or clip anvil) −1.3 V 3. Output: Connect LVPECL Output CLOCK and Output CLOCK outputs to the oscilloscope with matched cables. NOTE: The readings of the output voltage levels will be offset by −1.3 V from standard LVPECL levels. With this split supply, the device outputs will be parallel terminated by the oscilloscope (or frequency counter) input module’s internal 50 W to GND impedance. See the data sheet Figure 10, where SMAGND = VTT = VCC − 2.0 V = 0 V= OSCILLOSCOPE GND. An alternative thevenin parallel termination scheme can been accommodated by using the unpopulated Resistor Pads (R76, R77, R78, and R79) provided on the OUTPUT CLOCK and OUTPUT CLOCK lines near the SMA connectors. See AND8020 for additional details. Do not use both thevenin parallel termination scheme and LOW IMPEDANCE (50 W) termination schemes on the same output at the same time (double termination). 4. Trigger: Ensure the oscilloscope trigger input is properly setup and adjusted and has a 50 W termination to ground. The board does not provide 50 W source termination resistors. Two possible oscilloscope trigger methods might be 1. “T” connector from CLKOUT to the trigger of the scope, 2. Use CLKOUT directly to the trigger. 3. XTAL/CLK Input: Determine if the onboard crystal or an external signal reference will be used. Onboard Crystal signal source (27 MHz) is default http://onsemi.com 3 NB4N441MNGEVB real−time high impedance input scope will not require an external trigger connection. 5. XTAL/CLK Input: Determine if the onboard crystal or an external signal reference will be used. Onboard Crystal signal source is default ready for use. NOTE: If an external clock reference is used, then dismount crystal and connect a clock signal (10 MHz − 50 MHz) with standard LVTTL/LVCMOS into INPUT CLOCK (J1). Also short from the bottom side “through hole trace” of INPUT CLOCK to J5 (not J3). Do not drive XTAL2. Termination of the signal generator may be needed with 50 W to SMA ground. 6. Program SDI: The P, M, and N internal registers may be programmed by (A) the onboard PLD or (B) by using the three line LVTTL/LVCMOS Serial Data Interface (SDI) consisting of a SERIAL DATA (SDATA) input, a SERIAL CLOCK (SCLOCK) input, and a SERIAL LOAD (SLOAD) as follows: A. Onboard PLD 1. Insure all 4 of the J12 (441 CONFIG) jumpers are all installed connecting the PLD output to the Device 2. Insure JP1 LED/PLD indicates power is applied to the PLD (LED on) 3. Insure J3 (external CLOCK line from J1) is open, not LOADED, DRIVEN, or shorted; 4. Insure SW5 (LEFT: CUSTOM 441, RIGHT:STANDARD 442) select is set to the LEFT (bypassing SW2, SEL[3:0]. Note LED will light for “CUSTOM FREQUENCIES”. 5. Set SW4, SW6, and SW7 rocker switches to desired P, M, and N programming values: UP =0 LOGIC LOW (LED indicator OFF); DOWN = 1 LOGIC HIGH (LED indicator ON). 6. Load program values by depressing momentary switch SW8, or send a pulse signal through J13 SMA connector (when installed) with standard LVTTL/LVCMOS levels. B. External SDI 1. See datasheet DC Table, AC Table, as well as Figures 5 and 6. 2. To use the SDI serial data input port, generate and input SCLOCK, SDATA, and SLOAD signals with standard LVTTL/LVCMOS levels. The SCLOCK signal will sample the information presented on SDATA line. Values are loaded and indexed into a 18 bit shift register. The register shifts once per rising edge of the SCLOCK input. The serial input SDATA bits must each meet setup and hold hold timing to the respective SCLOCK rising edge as specified in the AC Characteristics section of the datasheet document. The MOST Significant Bit (MSB), P4, is indexed in first followed by P3, P2, P1, N2, N1, N0, M9 through the LEAST Significant Bit (LSB), M0, indexed in last. A Pulse on the SLOAD pin after the SHIFT register is fully indexed (18 clocks) will load and latch the data values for the internal P, M, and N registers. The SLOAD pulse Low to HIGH rising edge transition transfers the data from the SHIFT register to the LATCH register. The SLOAD Pulse HIGH to LOW transition will lock the new data values into the LATCH register. 5. Output Enable ON: Switch SW1 (DOWN) or externally HIGH through J11 (offset LVCMOS/ LVTTL of 2.0V HIGH and −1.3 V LOW) to enable the output after setup. LED D3 indicator will be ON to indicate an enabled output. ALTERNATE STEP 2: LAB SET−UP PROCEDURE FOR SINGLE SUPPLY (INTO HIGH IMPEDANCE PROBES) 1. Output Enable OFF: Switch SW1 (UP) or externally LOW through J11 (standard LVCMOS/ LVTTL of 2.0V HIGH and 0.8 V LOW) to disable the output during setup. LED D3 indicator will be off to indicate disabled output. 2. Supplies: Connect a “single” power supply to the evaluation board for 3.3 V operation as follows: VCC (RED banana jack or clip anvil) at +3.3 V SMAGND (YELLOW banana jack or clip anvil) at 0 V DUTGND (BLACK banana jack or clip anvil) 0V 3. Output: Connect LVPECL OUTPUT CLOCK and OUTPUT CLOCK outputs to the oscilloscope with matched cables. The device outputs will require proper termination. A thevenin parallel termination scheme can be accomplished by populating Resistor Pads (R76, R77, R78, and R79) provided on the OUTPUT CLOCK and OUTPUT CLOCK lines near the SMA connectors. Install 127 Ohm resistors R77 at SG4 and R78 at SG5. Install 83 Ohm resistors R76 at SG2 and R79 at SG2. See AND8020 for additional details. Use HIGH IMPEDANCE (FET) Probes or equipment only. Do not use LOW IMPEDANCE (50 W) equipment or probes when using thevenin parallel termination or the signal will be double terminated. 4. Trigger: Ensure the oscilloscope trigger input is setup and adjusted properly. A self triggered http://onsemi.com 4 NB4N441MNGEVB SLOAD pulse Low to HIGH rising edge transition transfers the data from the SHIFT register to the LATCH register. The SLOAD Pulse HIGH to LOW transition will lock the new data values into the LATCH register. timing to the respective SCLOCK rising edge as specified in the AC Characteristics section of the datasheet document. The MOST Significant Bit (MSB), P4, is indexed in first followed by P3, P2, P1, N2, N1, N0, M9 through the LEAST Significant Bit (LSB), M0, indexed in last. A Pulse on the SLOAD pin after the SHIFT register is fully indexed (18 clocks) will load and latch the data values for the internal P, M, and N registers. The 7. Output Enable ON: Switch SW1 (DOWN) or externally HIGH through J11 to enable the output after setup. LED D3 indicator will be ON to indicate an enabled output. http://onsemi.com 5 NB4N441MNGEVB APPENDIX 1: DEVICE AND BOARD INFORMATION SEE CURRENT DATASHEET DEVICE PINS: Pin Name Open Pin Default Pin # 441 I/O 1 GND Supply 2 NC 3 VCCPLL 4 NC No Connect 5 NC No Connect Type Function Negative Power Supply (Ground) No Connect Supply 6 GND Supply 7 XTAL2 Input 8 CLK/XTAL1 Input 9 GND Supply 10 NC Positive supply for the PLL and is connected to +3.3 V Negative Power Supply (Ground) Crystal Oscillator Interface − Crystal Input CMOS/TTL Crystal Oscillator Interface − Crystal Input or External Clock Input Negative Power Supply (Ground) No Connect 11 VCC Supply Positive Power Supply 12 VCC Supply Positive Power Supply 13 VCC Supply Positive Power Supply 14 NC 15 SLOAD Input L CMOS/TTL Serial Load Input 16 SDATA Input L CMOS/TTL Serial Data Input 17 SCLOCK Input L CMOS/TTL Serial Clock Input 18 GND Supply 19 GND Supply 20 LOCKED Output 21 OE Input 22 CLKOUT Output LVPECL Differential Clock Output 23 CLKOUT Output LVPECL Differential Clock Output 24 VCC Supply No Connect Negative Power Supply (Ground) Negative Power Supply (Ground) CMOS/TTL PLL Locked Indicator H CMOS/TTL Synchronous Output Enable. Active HIGH. The Enable is synchronous to the output clock to eliminate the possibility of runt pulses on the CLKOUT outputs. Positive Power Supply Board Pins Serial Pins (NB4N441) SCLOCK, SDATA and SLOAD pins have board traces connected to SMA connectors J10, J9 and J7 for external control. There are no 50 W termination resistors on these nodes. If signal sources requiring output termination are needed to drive SCLOCK, SDATA and SLOAD, a 50 W resistor can be added, from the board trace at the SMA conductor to SMA ground. Output Enable: The Output Enable function is carried out manually with the switch, SW1, or externally via SMA connector J11, and observing the OUTPUT CLOCK & OUTPUT CLOCK CLKOUT pins. PLL LOCKED There are two convenient PLL indicator LEDs, green for when the device is PLL LOCKED and red for PLL not LOCKED. LED/PLD Power: The LED and PLD power can be disabled by leaving JP1 open or removing shunt from JP1. Input Clock: An SMA connector (J1) board trace to CLK/XTAL1 device pin contains a gap placed on the board trace at the crystal pin (J5). This board trace and connector are open and not connected to the crystal pin and has no impedance affect on the crystal pin. A short must bridge this gap to connect the INPUT CLOCK SMA to the device CLK/XTAL1 pin. A 50 W termination resistor may be added from the board trace from CLK to SMAGND at the SMA connector, or, install a 50 W resistor in place of C6. SW4, 6 and 7 are the M, N, and P SELECT: DIP switches JP1 is an LED power supply jumper provided to disable the LED’s and their current. Disabling the LEDs will allow measuring only the device power supply current. Output CLOCK and Output CLOCK: The outputs have equal length board traces with SMA connectors, J2 & J4. Use matched cables to connect the outputs to an oscilloscope or frequency counter. Alternative connection pads are supplied for installation of a Thevenin termination scheme. http://onsemi.com 6 NB4N441MNGEVB APPENDIX 2: SCHEMATICS +3.3PLL +3.3V 1 +3.3V GND 2 NC2 VCCPLL NC4 3 VCC CLKOUT U1 NB4N441/2 CLKOUT OE LOCKED 14 15 16 17 GND R76 DNI R79 DNI SG2 Solder Gap SG3 Solder Gap 24 23 Note: No Stubs Between CLKOUT and CLKOUT_L and Solder Gaps. J2 CLKOUT SMA 22 CLKOUT_L J4 SMA 21 20 SG4 Solder Gap OUTPUT CLOCK OUTPUT CLOCK SG5 Solder Gap Note: CLKOUT and CLKOUT_L Traces Should be Equal Length. 19 GND NC/SEL3 SLOAD/SEL2 SDATA/SEL1 SCLK/SEL0 NC5 5 4 +3.3V R77 DNI 18 Figure 3. Outputs http://onsemi.com 7 R78 DNI NB4N441MNGEVB +3.3V No Stub Between Crystal and Solder Gap SG1 DNI J3 0673 Y1 DN1 4.88mm R5 DN1 XTAL2 7 XTAL1 8 9 10 J5 0673 +3.3V C6 DNI 11 12 GND C5 5 4 XTAL2 U1 NB4N441 XTAL1/CLK GND NC10 VCC VCC VCC These components as close to clock driver as possible. 13 Y2 27MHz XTAL 14 1516 17 This crystal is an HC49 leaded crystal that plugs into the two pin headers next to the clock driver. Figure 4. Input Clock and Crystal 10 +3.3V 11 12 J7 U1 NB4N441 GND NC10 VCC VCC SMA J9 SDATA/SEL1 13 SMA J10 SCLOCK/SEL0 Note: SELx Signals Have Internal 75k Pulldowns. SMA [2,4] SLD/S2 [2,4] SDAT/S1 [2,4] SCLK/S0 Figure 5. SDI Inputs http://onsemi.com 8 NC VCC SLOAD/SEL2 XTAL1/CLK 14 SCLK/SEL0 9 SDATA/SEL1 8 SLOAD/SEL2 XTAL1 3 VCCPLL 6 Solder Gap SMA NC5 NC4 CLK_IN NC/SEL3 SLOAD/SEL2 SDATA/SEL1 SCLK/SEL1 J1 INPUT CLOCK 15 16 17 NB4N441MNGEVB 10 NC10 OE U1 NB4N441 LOCKED 13 SDATA/SEL1 SCLK/SEL1 GND 20 19 GND NC/SEL3 VCC VCC VCC 12 SLOAD/SEL2 11 21 18 14 15 16 17 +3.3V_LED Note: OE Signal Has an Internal 37.5k Pullup. 1 R6 200W 1/16W D3 LED_GRN 3 2 OUTPUT ENABLED 2 Q2 BSS138W J11 OUTPUT ENABLE CLKOUT_OE 1 SW1 4 2 SMA 3 6 SW SPDT OUTPUT DISABLE Figure 6. Output Enable http://onsemi.com 9 1 NB4N441MNGEVB CLKOUT OE SDATA/SEL1 SCLK/SEL1 LOCKED GND 20 J8 LOCKED PLL LOCKED SMA 19 GND SLOAD/SEL2 CLKOUT_L 21 U1 NB4N441 NC/SEL3 22 +3.3V_LED +3.3V_LED 18 2 14 15 16 17 1 R2 200W 1/16W Place LED’s Near LOCKED Connector 1 1 3 Q8 BSS84W D1 LED_GRN D2 LED_RED PLL Not LOCKED 2 2 PLL LOCKED 3 R1 200W 1/16W Q1 BSS138W 2 1 Figure 7. Output LOCKED/Not LOCKED 1 R1 0 2 SW2 5 6 7 8 1 4 3 2 1 1 3 Q4 BSS138W 2 LED_ORN 1 D5 R13 200W 1/16W 2 2 LED_ORN 1 D6 R14 200W 1/16W 2 LED_ORN 1 D7 R15 200W 1/16W 3 Q3 BSS138W 3 Q6 BSS138W 1 2 1 R16 R17 R18 R19 3 Q6 BSS138W 2 LED_ORN D4 R12 +3.3V_LED 200W 1/16W 3 2 Inputs to Clock Driver or Driven by External Source Through SMA Connectors. [4] [4] [4] [4] 2 SEL3 SEL2 SEL1 SEL0 1 +3.3V_LED Inputs to PLD 75k 75k 75k 75k 0 R7 R8 R9 R10 J18 4.7k 4.7k 4.7k 4.7k DNI R20 R21 R22 R23 Figure 8. Inputs to PLD http://onsemi.com 10 0 0 0 0 S3 SLD/32 SDAT/S1 SCLK/S0 [1.4] [1.4] [1.4] [1.4] NB4N441MNGEVB 4 2 LED_AMB 1 D8 R43 200W 1/16W 3 2 LED_AMB 1 D9 R44 200W 1/16W 2 2 LED_AMB 1 D10 R46 200W 1/16W 1 2 LED_AMB 1 D11 R47 200W 1/16W 0 2 LED_AMB 1 D12 R49 200W 1/16W 9 2 LED_ORN 1 D14 R50 200W 1/16W 8 2 LED_ORN 1 D16 R52 200W 1/16W 7 2 LED_ORN 1 D17 R53 200W 1/16W 6 2 LED_ORN 1 D19 R55 200W 1/16W 5 +3.3V_LED 2 LED_ORN 1 D20 R57 200W 1/16W 4 5 4 3 2 1 [4] [4] [4] 2 LED_ORN 1 D21 R58 200W 1/16W 3 6 7 8 9 10 SW4 N2 N1 N0 [4] 2 LED_ORN 1 D22 R59 200W 1/16W 2 150k 150k 150k [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] 2 LED_ORN 1 D23 R60 200W 1/16W 1 R40 R41 R42 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 [4] 2 LED_ORN 1 D24 R61 200W 1/16W 0 150k 150k 150k 150k 150k 150k 150k 150k 150k 150k [4] 2 LED_ORN 1 D25 R62 2 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 P4 P3 P2 P1 P0 2 LED_YLW 1 D26 R63 200W 1/16W 1 150k 150k 150k 150k 150k 2 LED_YLW 1 D27 R64 200W 1/16W 0 R25 R26 R27 R28 R29 P[4:0] INPUT FEEDBACK +3.3V_LED 2 LED_YLW 1 D28 R65 200W 1/16W SW6 M[9:0] PLL FEEDBACK DIVIDER SW PianoDIP−5 10 9 8 7 6 5 4 3 2 1 11 12 13 14 15 16 17 18 19 20 200W 1/16W OUTPUT FREQUENCY DIVIDER N[2:0] SW PianoDIP−10 SW7 4 5 6 3 2 1 SW PianoDIP−3 Figure 9. Switches and LED http://onsemi.com 11 NB4N441MNGEVB +3.3V_LED DNI R45 PLD_OEn [4] SW3 +3.3V_LED 1 3 6 4 SW SPST 2 1 D12 R48 On−Board Serial Enabled +3.3V_LED Use Custom Frequencies 2 3 1 D15 R51 200W 1/16W 1 D18 R54 200W 1/16W LED_GRN Q7 BSS138W 2 1 2 DNI DNI LED_GRN Use Standard Protocols R56 150k SW5 1 3 6 4 STDn [4] SW SPST Figure 10. Output Enable http://onsemi.com 12 NB4N441MNGEVB +3.3V_LED [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 [3] N2 N1 N0 [3] [3] +3.3V_LED R73 20 21 22 23 25 27 28 30 31 33 34 35 37 4.7k 1 3 SMA SW8 2 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 N2 R68 DNI N1 GND OUT 39 RCFGn CLK 4MHz Spare1 DNI R69 DNI 40 GCLK1 4MHz Oscillator 4 16 24 36 Figure 11. PLD http://onsemi.com 13 R71 1k R72 1k X R74 1k 4 3 DNI R67 PLD_TDI TD1 1 RCFGn GND VDD R66 TCK 26 PLD_TCK TDO 32 PLD_TDO TMS 7 PLD_TMS GND 2 OE Spare2 R70 1k N0 +3.3V_LED Y3 [1,2] [1,2] [1,2] [1,2] +3.3V_LED GND 1 S3 SLD/S2 SDAT/S1 SCLK/S0 EPM7032AETC44 GND CLK_OE S_NC SLOAD SDAT SCLK 43 Spare2 Spare1 42 SW MOM PB−SPDT +3.3V_LED 5 NC/S3 3 SLD/S2 2 SDAT/S1 44 SCLK/S0 +3.3V_LED 38 PLD_OEn [3] PLD_OEn J13 RCFG+EXT RECONFIGURE P4 P3 P2 P1 P0 VCC SEL3 SEL2 SEL1 SEL0 VCC SEL3 8 SEL2 10 SEL1 11 SEL0 12 STDn 13 P4 14 P3 15 P2 18 P1 19 P0 VCC 6 [3] STDn [3] [3] [3] [3] [3] VCC 9 10 11 12 [2] [2] [2] [2] +3.3V_LED J14 1 3 5 7 9 2 4 6 8 10 X X JTAG HEADER NB4N441MNGEVB +3.3V J15 VCC DUTGND Caps near power connector. 2 1 Red Banana Jack J16 2 SMAGND 1 YLW Banana Jack J17 +3.3V 16V 20% 16V 20% + + C7 22mF C12 22mF C8 0.01mF C13 0.01mF +3.3V C9 0.1mF C14 0.1mF Place resistor under inductor so only one can be installed. +3.3PLL L1 R75 +DN1 13W + C10 0.1mF 1/8W 2 1 BLK Banana Jack M6 #4−40 Hex Standoff. 3/4”x1/4” M7 #4−40 Hex Standoff. 3/4”x1/4” M8 #4−40 Hex Standoff. 3/4”x1/4” M9 #4−40 Hex Standoff. 3/4”x1/4” M10 #4−40 Phillips Panhead 1/4” Zn−Plated Machine Screw M11 #4−40 Phillips Panhead 1/4” Zn−Plated Machine Screw M12 #4−40 Phillips Panhead 1/4” Zn−Plated Machine Screw M13 #4−40 Phillips Panhead 1/4” Zn−Plated Machine Screw Caps near Clock Driver Pin 3. Place one cap by each Clock Driver VCC or GND Pin. +3.3V C15 0.01mF C24 0.01mF C16 0.01mF C25 0.01mF +3.3V LED C17 0.01mF C26 0.01mF C11 22mF 16V C18 0.01mF C27 0.01mF C19 0.1mF C28 0.01mF C20 0.1mF C21 0.1mF C22 0.1mF C23 0.1mF Place one cap by each PLD and OSC VCC Pin. +3.3V +3.3V M5 0.1” Shunt +3.3V LED JP1 1 2 Header2x1 X1 X2 Mounding Mounding Hole Hole X TP1 TP2 Jumper allows user to isolate clock driver for power estimation. X3 Mounding Hole X4 Mounding Hole X X X PCB Notes: 1. Use GETEK Board Material 2. Board Impedance: 50 W Figure 12. Power and Hardware http://onsemi.com 14 TP4 TP3 Three Power Planes: VCC (+3.3V) SMAGND (+1.3V) DUTGND (GND) TP5 NB4N441MNGEVB APPENDIX 3: BILL OF MATERIALS, LAMINATION STACKUP, AND ASSEMBLY NOTES Item Mfg Part # 1 Description Manufacturer DNI 2 T494D226K016AS 3 Reference Vendor Part # Vendor C1,C2,R3,C3,R4,C4,R 5,C5,C6,R45,R48,R66 ,R67,R68,R69,R76, R77,R78,R79 Qty 19 22mF Kemet C7,C11,C12 399−1782−1−ND Digikey 3 C0603C103K5RACTU 0.01mF Kemet C8,C10,C13,C15,C16, C17,C18,C24,C25, C26,C27,C28 399−1091−1−ND Digikey 12 4 ECJ−1VB1C104K 0.1mF Panasonic C9,C14 PCC1762CT−ND Digikey 2 5 ECJ−1VB1C104K 0.1mF Panasonic C19,C20,C21,C22, C23 PCC1762CT−ND Digikey 5 6 LTST_C190GKT LED_GRN Lite−On D3,D1 160−1183−1−ND Digikey 2 7 LTST_C190CKT LED_RED Lite−On D2 160−1181−1−ND Digikey 1 8 LTST_C190EKT LED_ORN Lite−On D4,D5,D6,D7 160−1182−1−ND Digikey 4 9 LTST_C190AKT LED_AMB Lite−On D8,D9,D10,D11,D13 160−1180−1−ND Digikey 5 LTST_C190EKT LED_ORN 160−1182−1−ND Digikey 10 10 11 DNI D12 Lite−On D14,D16,D17,D19, D20,D21, 1 D22,D23,D24,D25 12 LTST_C190GKT LED_GRN Lite−On D15,D18 160−1183−1−ND Digikey 2 13 LTST_C190YKT LED_YLW Lite−On D26,D27,D28 160−1184−1−ND Digikey 3 14 22−03−2021 Header2x1 Molex JP1 WM4000−ND Digikey 1 15 142−0701−801 SMA Johnson Components J1,J2,J4,J7,J8,J9,J10, J11 J502−ND Digikey 8 16 0673−0−15−01−30−02−10 −0 0673 Mill−Max J3,J5 17 142−0701−801 SMA Johnson Components J6 J502−ND Digikey 1 18 10−89−1081 Molex J12 WM6808−ND Digikey 1 19 142−0701−801 Johnson Components J13 J502−ND Digikey 1 20 10−89−1101 JTAG HEADER Molex J14 WM6810−ND Digikey 1 21 571−0500 RED BANANA JACK Deltron J15 150−039 Farnell / Newark 1 22 571−0700 YLW BANANA JACK Deltron J16 150−043 Farnell / Newark 1 23 571−0100 BLK BANANA JACK Deltron J17 150−040 Farnell / Newark 1 24 10−89−1081 DNI Molex J18 WM6808−ND Digikey 1 25 CDRH74−102MC DNI Sumida L1 308−1197−1−ND Digikey 1 26 382811−5 0.1” Shunt AMP/Tyco M1,M2,M3,M4 A26229−ND Digikey 4 27 382811−5 0.1” Shunt AMP/Tyco M5 A26229−ND Digikey 1 28 1895 #4−40 Hex Standoff, 3/4”x1/4” Keystone M6,M7,M8,M9 1895K−ND Digikey 4 29 PMS 440 0025 PH Building Fasteners M10,M11,M12,M13 H342−ND Digikey 4 30 50−000−00306 M&M Specialties M14 M&M Specialties 1 31 BSS138W−7 BSS138W Diodes Inc. Q1,Q2,Q3,Q4,Q5,Q6 BSS138WDICT−ND Digikey 6 32 BSS138W−7 BSS138W Diodes Inc. Q7 BSS138WDICT−ND Digikey 1 33 BSS84W−7 BSS84W Diodes Inc. Q8 621−BSS84W Mouser 1 34 ERJ−3GEYJ221V 200W Panasonic R1,R2,R6,R12,R13, R14,R15 P220GCT−ND Digikey 7 8−pin Header SMA #4−40 Phillips Panhead 1/4” Zn−plated Machine Screw 24 LD QFN GCI Flex Socket http://onsemi.com 15 2 50−000−00306 NB4N441MNGEVB Item Mfg Part # Description Manufacturer Reference Vendor Part # Vendor Qty 35 ERJ−3GEYJ753V 75k Panasonic R7,R8,R9,R10 P75KGCT−ND Digikey 4 36 ERJ−3GEY0R00V 0.0 Panasonic R11 P0.0GCT−ND Digikey 1 37 ERJ−3GEYJ472V 4.7k Panasonic R16,R17,R18,R19 P4.7KGCT−ND Digikey 4 38 ERJ−3GEY0R00V 0.0 Panasonic R20,R21,R22,R23 P0.0GCT−ND Digikey 4 39 ERJ−3GEY0R00V 0.0 Panasonic R24 P0.0GCT−ND Digikey 1 40 ERJ−3GEYJ154V 150k Panasonic R25,R26,R27,R28,R2 9,R30,R31,R32,R33,R 34,R35,R36,R37,R38, R39,R40,R41,R42, R56 P150KGCT−ND Digikey 19 41 ERJ−3GEYJ221V 200W Panasonic R43,R44,R46,R47,R4 9,R50,R51,R52,R53,R 54,R55,R57,R58,R59, R60,R61,R62,R63, R64,R65 P220GCT−ND Digikey 20 42 ERJ−3GEYJ102V 1K Panasonic R70,R71,R72,R74 P1.0KGCT−ND Digikey 4 43 ERJ−3GEYJ472V 4.7k Panasonic R73 P4.7KGCT−ND Digikey 1 44 ERJ−6GEYJ130V 13W Panasonic R75 P13ACT−ND Digikey 1 45 GT11MSCKETR SW SPDT C&K SW1 CKN1099CT−ND Digikey 1 46 76PSB04 SW DIP−4 Grayhill SW2 GH1215−ND Digikey 1 47 DNI 48 76PSB05 49 GT12MSCKETR 50 76PSB10 SW PianoDIP−10 51 76PSB03 SW PianoDIP−3 52 EP12SD1SAKE 53 5015 54 NB4N441 55 EPM7032AETC44−10 56 SW PianoDIP−5 SW SPST SW MOM PB−SPDT TP_SMT_KEYSTONE NB4N441 EPM7032AETC44 SW3 SW4 GH1216−ND Digikey 1 C&K SW5 CKN1100CT−ND Digikey 1 Grayhill SW6 GH1221−ND Digikey 1 Grayhill SW7 GH1214−ND Digikey 1 C&K SW8 CKN4056CT−ND Digikey 1 Keystone TP1,TP2,TP3,TP4, TP5 5015KCT−ND Digikey 5 ON Semiconductor U1 Altera U2 Mounting Hole 57 HCM49−21.47727MABJT 58 HC49US27.000MABJ 59 CSX750FBC4.000000MTR 1 Grayhill 1 EPM7032AETC44−10 Arrow X1,X2,X3,X4 1 4 DNI Citizen Y1 300−6143−1−ND Digikey 1 27MHz XTAL Citizen Y2 300−6050−ND Digikey 1 4MHz Oscillator Citizen Y3 300−7232−1−ND Digikey 1 http://onsemi.com 16 NB4N441MNGEVB LAMINATION STACK L1 L2 L3 L4 Signal SMAGND VCC and DUTGND DUTGND and Signal LAMINATION DIAGRAM Layer Number Layer Name Copper Thickness Dielectric Thickness Layer Material Trace Width ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 2 TOP SMAGND 3 4 PWR DUTGND 1/2 OZ. 0.012 0.006 GETEK Adjust GETEK 0.006 GETEK 1 OZ. −−− 1 OZ. −−− 1/2 OZ. 0.011 FINISHED PCB THICKNESS TO BE: 0.64 ±0.003 ASSEMBLY NOTES: Notes (Unless Otherwise Specified) Material: micro−inches thick) over electrodeposited nickel plate in accordance with ANSI/IPC−A−6000, Section 4.0, Class 3 (200−600 micro−inches thick). 7. Drill sizes are finished. Plated through holes to have a minimum barrel plating of 0.0008 in. 8. Board twist and warp not to exceed 0.005 in (5%) per linear inch. Front to back registration to be within 0.003 in. 9. True position tolerance shall be determined by a minimum anular ring of 0.005 in. 10. Plated holes shall not be rough or irregular so as to hinder proper solder wicking. 11. Soldermask: Green LPI: B0 12. Apply Legend (SILKSCREEN) to both sides using a nonconductive, white, Epoxy based ink per artwork. 13. No board shop logo on board. 14. Each PCB shall be serialized, in legend, in the area shown, as follow: 0005−1−1 (Sequential Number (assigned per panel)−Panel Number (assigned per log)−Year and Week). 1. GETEK Laminate Epoxy/Polyphenylene Oxide Resin Type NEMA FR−4 (IPC−L−1088/04). See Layer Table. Inner Layers: 1 oz. Copper clad Outer Layers: 1/2 oz. Copper Foil Plated to 1 1/2 oz finished. 2. Refer to Stacking Diagram for Finished Board Thickness. Tooling: 3. Photo etch circuitry per artwork drill locations controlled by drill file.drl fabrication print. 4. The dielectric thickness of the controlled impedance layers is for reference only. Final acceptance shall be determined by these layer pairs having a characteristic impedance of 52.5 W $10%. The vendor can make width adjustments on only the critical conductor widths of $0.0005. All other adjustments must have prior approval from Baldwin Tech Layer Grouping (1.2). 5. Finished conductor width to be 0.012”. Finish: Testing: 6. Plating Specification: Electrodeposited hard gold plate, Type 1 (99.7% min gold) Grade C (Knoop Hardness 130−200), Class 1 (50−100 micro−inches thick) in accordance with MIL−G−4520C and ANSI/IPC−A−6000. Section 4.0 (surface placing acceptability requirements), Class 3 (50−100 15. Final Electrical Test shall be preformed per provided IPC−356 netlist. The PCB shall have a verification stamp. Connectivity to be verified against IPC format net list. 16. A TDR report for each layer shall be provided by vendor at time of shipment. http://onsemi.com 17 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. The evaluation board/kit (research and development board/kit) (hereinafter the “board”) is not a finished product and is not available for sale to consumers. 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