NVTFS5C466NL
MOSFET - Power, Single
N-Channel
40 V, 7.3 mW, 51 A
Features
•
•
•
•
•
•
Small Footprint (3.3 x 3.3 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVTFS5C466NLWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(on) MAX
ID MAX
7.3 m @ 10 V
40 V
12 m @ 4.5 V
51 A
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
51
A
Continuous Drain
Current RJC
(Notes 1, 2, 3, 4)
TC = 25°C
Power Dissipation
RJC (Notes 1, 2, 3)
Continuous Drain
Current RJA
(Notes 1, 3, 4)
Steady
State
TC = 100°C
TC = 25°C
Pulsed Drain Current
PD
Steady
State
S (1, 2, 3)
19
ID
A
14
TA = 100°C
TA = 25°C
G (4)
W
38
TC = 100°C
TA = 25°C
Power Dissipation
RJA (Notes 1, 3)
36
MARKING DIAGRAM
12
PD
W
3.1
TA = 100°C
1.5
IDM
214
A
TJ, Tstg
−55 to
+175
°C
IS
31.3
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 3 A)
EAS
72
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
TA = 25°C, tp = 10 s
Operating Junction and Storage Temperature
Range
Source Current (Body Diode)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
N−Channel
D (5 − 8)
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 3)
RJC
4.0
°C/W
Junction−to−Ambient − Steady State (Note 3)
RJA
48
1
WDFN8
(m8FL)
CASE 511AB
XXXX
A
Y
WW
G
1
S
S
S
G
XXXX
AYWWG
G
D
D
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi () is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second is higher but is dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2017
August, 2019 − Rev. 4
1
Publication Order Number:
NVTFS5C466NL/D
NVTFS5C466NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
V(BR)DSS
VGS = 0 V, ID = 250 A
40
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown
Voltage Temperature Coefficient
V(BR)DSS/
TJ
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
29
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 30 A
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V, ID = 10 A
A
100
nA
2.2
V
6.1
7.3
m
12
ON CHARACTERISTICS (Note 5)
1.2
VGS = 4.5 V, ID = 10 A
9.7
gFS
VDS = 15 V, ID = 25 A
33
S
Input Capacitance
Ciss
880
pF
Output Capacitance
Coss
VGS = 0 V, f = 1.0 MHz,
VDS = 25 V
Reverse Transfer Capacitance
Crss
16
Total Gate Charge
QG(TOT)
7.0
nC
Threshold Gate Charge
QG(TH)
1.8
nC
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Forward Transconductance
CHARGES AND CAPACITANCES
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 32 V, ID = 25 A
340
3.3
2.5
VGS = 10 V, VDS = 32 V, ID = 25 A
16
nC
td(on)
10
ns
tr
67
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 4.5 V, VDS = 32 V,
ID = 25 A, RG = 2.5
tf
26
32
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
TJ = 25°C
0.9
TJ = 125°C
0.8
22
VGS = 0 V, dlS/dt = 100 A/s,
IS = 25 A
QRR
1.2
V
ns
10
12
6.0
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
NVTFS5C466NL
TYPICAL CHARACTERISTICS
100
VGS = 10 to 5 V
ID, DRAIN CURRENT (A)
50
3.8 V
40
3.6 V
30
3.4 V
20
3.2 V
10
70
60
50
40
30
TJ = 25°C
20
0.5
1.0
1.5
2.0
2.5
0
3.0
0
2
1
TJ = −55°C
3
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
20
15
10
5
4
5
6
7
8
9
10
12
TJ = 25°C
11
6
5
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 25 A
TJ = 25°C
3
TJ = 125°C
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
25
0
80
10
VGS = 4.5 V
10
9
8
7
VGS = 10 V
6
5
4
10
15
20
25
30
40
35
45
50
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.1
2.0
ID = 25 A
1.9
V
GS = 10 V
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
−50 −25
0
100K
TJ = 150°C
10K
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (m)
0
VDS = 10 V
90
4.5 V
60
ID, DRAIN CURRENT (A)
70
TJ = 125°C
1K
TJ = 85°C
100
TJ = 25°C
10
25
50
75
100
125
150
1
175
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVTFS5C466NL
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10K
Ciss
1K
Coss
100
Crss
10
1
TJ = 25°C
VGS = 0 V
f = 1 MHz
0
5
15
10
20
25
30
35
40
5
Qgs
4
td(off)
3
VDS = 32 V
ID = 25 A
TJ = 25°C
2
1
0
0
2
4
6
8
10
12
14
td(on)
VGS = 4.5 V
VDS = 32 V
ID = 25 A
1
10
TJ = 125°C
1
0.1
100
16
VGS = 0 V
TJ = 25°C
0.3
0.4
0.5
0.6
TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
Single Pulse
VGS ≤ 10 V
TC = 25°C
TJ(initial) = 25°C
IPEAK (A)
10
10
1
0.1
Qgd
Figure 8. Gate−to−Source vs. Total Charge
IS, SOURCE CURRENT (A)
t, TIME (ns)
6
Figure 7. Capacitance Variation
tr
10
ID, DRAIN CURRENT (A)
7
Qg, TOTAL GATE CHARGE (nC)
tf
100
8
10
100
1000
9
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
10
10 s
0.5 ms
1 ms
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
TJ(initial) = 100°C
1
0.1
0.00001
100
0.0001
0.001
0.01
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TIME IN AVALANCHE (s)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Drain Current vs. Time in
Avalanche
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4
NVTFS5C466NL
TYPICAL CHARACTERISTICS
100
50% Duty Cycle
R(t) (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
0.01
Single Pulse
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 13. Thermal Response
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5
1
10
100
1000
NVTFS5C466NL
DEVICE ORDERING INFORMATION
Marking
Package
Shipping†
NVTFS5C466NLTAG
466L
WDFN8
(Pb−Free)
1500 / Tape & Reel
NVTFS5C466NLWFTAG
66LW
WDFN8
(Pb−Free)
1500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P
CASE 511AB
ISSUE D
1
SCALE 2:1
DATE 23 APR 2012
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH
PROTRUSIONS OR GATE BURRS.
0.20 C
D
A
D1
B
2X
0.20 C
8 7 6 5
4X
E1 E
q
c
1 2 3 4
A1
TOP VIEW
0.10 C
A
e
SIDE VIEW
0.10
8X b
C A B
0.05
C
4X
DETAIL A
8X
e/2
1
0.42
4
INCHES
NOM
0.030
−−−
0.012
0.008
0.130 BSC
0.116
0.120
0.078
0.083
0.130 BSC
0.116
0.120
0.058
0.063
0.009
0.012
0.026 BSC
0.012
0.016
0.026
0.032
0.012
0.017
0.002
0.005
0.055
0.059
0_
−−−
MIN
0.028
0.000
0.009
0.006
MAX
0.031
0.002
0.016
0.010
0.124
0.088
0.124
0.068
0.016
0.020
0.037
0.022
0.008
0.063
12 _
0.65
PITCH
PACKAGE
OUTLINE
4X
0.66
M
E3
8
5
D2
BOTTOM VIEW
1
3.60
L1
GENERIC
MARKING DIAGRAM*
XXXXX
A
Y
WW
G
MILLIMETERS
MIN
NOM
MAX
0.70
0.75
0.80
0.00
−−−
0.05
0.23
0.30
0.40
0.15
0.20
0.25
3.30 BSC
2.95
3.05
3.15
1.98
2.11
2.24
3.30 BSC
2.95
3.05
3.15
1.47
1.60
1.73
0.23
0.30
0.40
0.65 BSC
0.30
0.41
0.51
0.65
0.80
0.95
0.30
0.43
0.56
0.06
0.13
0.20
1.40
1.50
1.60
0_
−−−
12 _
SOLDERING FOOTPRINT*
L
G
SEATING
PLANE
DETAIL A
K
E2
C
6X
0.10 C
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
E3
e
G
K
L
L1
M
q
XXXXX
AYWWG
G
0.75
2.30
0.57
0.47
2.37
3.46
DIMENSION: MILLIMETERS
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30561E
WDFN8 3.3X3.3, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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