HEF4527BN

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4527B MSI BCD rate multiplier Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification BCD rate multiplier DESCRIPTION The HEF4527B is a BCD rate multiplier with two buffered rate outputs (O1 and O1), two buffered terminal count outputs (TC and TC), four BCD rate select inputs (SA, SB, SC, SD), a common clock input (CP), a preset input (PL), an overriding asynchronous clear input (CL), a strobe input (STR), a cascade input (CAS) and an active LOW count enable input (CE). The BCD rate multiplier provides an output pulse rate based upon the BCD input number. For example, if 6 is the BCD number, there will be six output pulses for every ten clock input pulses. The output is clocked on the negative-going transition of the clock. When CE, STR, CAS, CL and PL are LOW, the rate pulses are available at the outputs O1 and O1, the terminal count pulses at TC and TC. HEF4527B MSI A HIGH on CL resets the counter, independent of all other input conditions and a rate of 10 pulses is available at O1 and O1 when SD is HIGH. When CE is HIGH, the counter is disabled, the state of the outputs (O1, O1) depend on the content of the counter. A HIGH on PL sets the counter in the ‘9’ state and TC becomes HIGH. A HIGH on STR inhibits the outputs O1 and O1. A HIGH on CAS forces the output O1 to HIGH, while the state of O1 depends on the inputs SA to SD (see lines 1 to 16 of function table). This device may be used to perform arithmetic operations. For the add mode and multiply mode see Figs 5 and 6. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification BCD rate multiplier HEF4527B MSI HEF4527BP(N): HEF4527BD(F): HEF4527BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. PINNING CP PL CL CE STR CAS SA to SD O1 to O1 TC TC clock input preset to ‘9’ input counter clear input count enable input (active LOW) strobe input cascade input rate select inputs rate outputs terminal count output (active HIGH) terminal count output (active LOW) January 1995 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 4 Product specification Fig.3 Logic diagram. Philips Semiconductors BCD rate multiplier HEF4527B MSI Philips Semiconductors Product specification BCD rate multiplier FUNCTION TABLE INPUTS NUMBER OF PULSES OR LOGIC LEVEL SD L L L L L L L L H H H H H H H H X X X H L X Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. Same output as the first 16 lines of this function table (depends on the values of SA to SD). 5. Depends on internal state of the counter. SC L L L L H H H H L L L L H H H H X X X X X X SB L L H H L L H H L L H H L L H H X X X X X X SA L H L H L H L H L H L H L H L H X X X X X X CP 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 X 10 10 10 X X CE STR CAS L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L H L L L CL L L L L L L L L L L L L L L L L L L L H H L PL L L L L L L L L L L L L L L L L L L L X X H OUTPUTS NUMBER OF PULSES OR LOGIC LEVEL O1 L 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 (5) HEF4527B MSI MODE OF OPERATION O1 H 1 2 3 4 5 6 7 8 9 8 9 8 9 8 9 (5) TC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L TC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (5) rate pulses at the outputs depend on the BCD input number at SA to SD CE = H; counter disabled outputs O1 and O2 disabled output O1 disabled CL = H counter reset PL = H; preset to ‘9’ L H 10 L L H (4) 1 1 L L H 10 H H January 1995 5 Philips Semiconductors Product specification BCD rate multiplier AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns. PARAMETER Propagation delays CP → O1, O1 HIGH to LOW 5 10 15 5 LOW to HIGH CP → TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CP → TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CAS → O1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH STR → O1, O1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CE →TC HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 130 50 35 130 50 35 175 65 45 160 65 45 175 65 50 150 60 45 90 35 25 70 30 25 100 40 30 85 35 25 95 35 25 65 30 20 260 ns 100 ns 70 ns 260 ns 100 ns 70 ns 350 ns 130 ns 90 ns 320 ns 130 ns 90 ns 350 ns 130 ns 100 ns 300 ns 120 ns 90 ns 180 ns 70 ns 50 ns 140 ns 60 ns 50 ns 200 ns 80 ns 60 ns 170 ns 70 ns 50 ns 190 ns 70 ns 50 ns 130 ns 60 ns 40 ns VDD V SYMBOL MIN. TYP. MAX. UNIT HEF4527B MSI TYPICAL EXTRAPOLATION FORMULA 103 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 103 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 148 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 133 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 148 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 123 ns + (0,55 ns/pF) CL 49 ns + (0,23 ns/pF) CL 37 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 38 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL January 1995 6 Philips Semiconductors Product specification BCD rate multiplier HEF4527B MSI VDD V 5 10 15 5 10 15 tPLH tPHL SYMBOL MIN. TYP. 145 55 40 145 55 40 260 tPHL 100 70 235 tPLH 90 50 45 tWCPH 18 12 20 tWCLH 12 10 50 tWPLH 30 tsu 20 12 20 tRCL 16 10 80 tRPL 36 25 4,5 fmax 11 16 20 15 15 10 5 10 8 5 40 18 10 9 22 32 MAX. UNIT TYPICAL EXTRAPOLATION FORMULA 118 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 118 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 233 ns + (0,55 ns/pF) CL 89 ns + (0,23 ns/pF) CL 62 ns + (0,16 ns/pF) CL 208 ns + (0,55 ns/pF) CL 79 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL PARAMETER CL → O1 HIGH to LOW CL → O1 LOW to HIGH Propagation delays PL → O1, O1 HIGH to LOW 290 ns 110 ns 80 ns 290 ns 110 ns 80 ns 520 ns 200 ns 140 ns 470 ns 180 ns 100 ns 90 ns 36 ns 24 ns 40 ns 24 ns 20 ns 100 ns 40 ns 30 ns ns ns ns ns ns ns ns ns ns MHz MHz MHz 5 10 15 5 LOW to HIGH Minimum clock pulse width HIGH Minimum CL pulse width; HIGH Minimum PL pulse width; HIGH Set-up times CE → CP Recovery times CL → CP 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 PL → CP Maximum clock pulse frequency 10 15 5 10 15 January 1995 7 Philips Semiconductors Product specification BCD rate multiplier AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 1 050 fi + ∑ (foCL) × VDD2 4 500 fi + ∑ (foCL) × VDD 2 HEF4527B MSI where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) 10 500 fi + ∑ (foCL) × VDD2 January 1995 8 Philips Semiconductors Product specification BCD rate multiplier HEF4527B MSI Fig.4 Timing diagram. January 1995 9 Philips Semiconductors Product specification BCD rate multiplier APPLICATION INFORMATION Add mode HEF4527B MSI Output rate = 10n (0,1 BCD1 + 0,01 BCD2 + 0,01 BCD3 + ........), in where n = number of cascaded RMs. Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 + 0,01 × 4) = 94. Fig.5 Two HEF4527B cascaded in the add mode. Multiply mode Output rate = 10n (0,1 BCD1 × 0,1 BCD2 × 0,1 BCD3 × ........), in where n = number of cascaded RMs. Example: RM1 preset to 9 and RM2 preset to 4, output rate is 102 (0,1 × 9 × 0,1 × 4) = 36. Fig.6 Two HEF4527B cascaded in the multiply mode. January 1995 10