5V41236PGG8

DATASHEET 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Recommended Applications Features/Benefits Four output synthesizer for PCIe Gen1/2/3 • 20-TSSOP package; small board footprint • Spread spectrum capable; reduces EMI • Outputs can be terminated to LVDS; can drive a wider General Description variety of devices The 5V41236 is a PCIe Gen1/2/3 compliant spread spectrum capable clock generator. The device has 4 differential HCSL outputs and can be used in communication or embedded systems to substantially reduce electro-magnetic interference (EMI). The spread amount and output frequency are selectable via select pins. • Power-down pin; greater system power management • OE control pin; greater system power management • Spread% and frequency pin selection; no software required to configure device • Industrial temperature range available; supports demanding embedded applications Output Features Key Specifications • Four 0.7V current mode differential HCSL output pairs • • • • Cycle-to-cycle jitter < 100ps Output-to-output skew < 50ps PCIe Gen2 phase jitter < 3.0ps RMS PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram VDD 2 SEL[2:0] 3 Spread Spectrum/ Output clock selection PD OE Spread Spectrum Circuitry CLKOUTA 25 MHz crystal or clock X1 Clock Oscillator X2 CLKOUTA CLKOUTB PLL Clock Synthesis CLKOUTB CLKOUTC CLKOUTC CLKOUTD CLKOUTD Optional tuning crystal capacitors 2 Rr(IREF) GND IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 1 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Pin Assignment VDDXD 1 20 CLKA S0 2 19 CLKA S1 3 18 CLKB S2 4 17 CLKB X1 5 16 GNDODA X2 6 15 VDDODA PD 7 14 CLKC OE 8 13 CLKC GNDXD 9 12 CLKD 10 11 CLKD IREF 20-pin (173 mil) TSSOP Spread Spectrum Selection Table S2 S1 S0 Spread% Spread Type 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable -0.5 Down -1.0 Down -1.5 Down No Spread Not Applicable IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Output Frequency 100 100 100 100 200 200 200 200 2 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Pin Descriptions Pin No. Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 VDDXD S0 S1 S2 X1 X2 PD# OE Power Input Input Input Input Output Input Input Connect to +3.3V digital supply. Spread spectrum select pin #0. See table above. Internal pull-up resistor. Spread spectrum select pin #1. See table above Internal pull-up resistor. Spread spectrum select pin #2. See table above. Internal pull-up resistor. Crystal connection. Connect to a fundamental mode crystal or clock input. Crystal connection. Connect to a fundamental mode crystal or leave open. Powers down all PLLs and tri-states outputs when low. Internal pull-up resistor. Provides output on, tri-states output (High = enable outputs; Low = disable outputs). Internal pull-up resistor. 9 10 11 12 13 14 15 16 GND IREF CLKD# CLKD CLKC# CLKC VDDODA GND Power Output Output Output Output Output Power Power Connect to digital ground. Precision resistor attached to this pin is connected to the internal current reference. Selectable 100/200MHz spread spectrum differential complement output clock D. Selectable 100/200MHz spread spectrum differential true output clock D. Selectable 100/200MHz spread spectrum differential complement output clock C. Selectable 100/200MHz spread spectrum differential true output clock C. Connect to +3.3V analog supply. Connect to analog ground. 17 CLKB# Output Selectable 100/200MHz spread spectrum differential complement output clock B. 18 CLKB Output Selectable 100/200MHz spread spectrum differential true output clock B. 19 CLKA# Output Selectable 100/200MHz spread spectrum differential complement output clock A. 20 CLKA Output Selectable 100/200MHz spread spectrum differential true output clock A. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 3 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Application Information Decoupling Capacitors Load Resistors RL As with any high-performance mixed-signal IC, the 5V41236 must be isolated from system power supply noise to perform optimally. Since the clock outputs are open source outputs, 50 external resistors to ground are to be connected at each clock output. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. Output Termination The PCI-Express differential clock outputs of the 5V41236 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. The 5V41236 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the 5V41236. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be connected between VDD and GND pairs (1,9 and 15,16) as close to the device as possible. On chip capacitors- Crystal capacitors should be connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value (in pf) of these crystal caps equal (CL - 12) × 2 in this equation, CL = crystal load capacitance in pf. For example, for a crystal with a 16pF load cap, each external crystal cap would be 8pF. [(16 - 12) × 2] = 8. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50, then Rr = 475 (1%), providing IREF of 2.32mA, output current (IOH) is equal to 6 × IREF. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 4 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Output Structures 6*IREF IREF =2.3 mA R R 475 See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the 5V41236.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 5 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Layout Guidelines SRC Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt D imension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 2 min to 16 max 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 0.25 to 14 max 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 6 PCI Express Add-in Board REF_CLK Input L3 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 7 PCIe Device REF_CLK Input 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.52 V 0.175 V tOF 0.52 V 0.175 V Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 1250 mV 1150 mV 500 ps tOF 1250 mV 1150 mV IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 8 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 5V41236. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD, VDDA 5.5V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature (commercial) 0 to +70C Ambient Operating Temperature (industrial) -40 to +85C Storage Temperature -65 to +150C Junction Temperature 125C Soldering Temperature 260C ESD Protection (Input) 2000V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85C Parameter Symbol Supply Voltage Conditions VDD Input High Voltage 1 Min. Typ. Max. Units 3.135 3.3 3.465 V VIH S0, S1, S2, OE, X1, PD# 2.2 VDD + 0.3 V VIL S0, S1, S2, OE, X1, PD# VSS - 0.3 0.8 V Input Leakage Current IIL 0 < Vin < VDD 5 A Operating Supply Current at100 MHz IDD RS = 33RP = 50, CL = 2 pF 113 125 mA OE = Low 42 50 mA Input pin capacitance 7 pF Output pin capacitance Input Low Voltage 1 2 Input Capacitance IDDOE CIN -5 Output Capacitance COUT 6 pF X1, X2 Capacitance CINX 5 pF Pin Inductance LPIN 5 nH Output Impedance Zo Pull-up Resistance RPUP CLK outputs 3.0 S0, S1, OE, S2, PD# k 100 k 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 9 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER AC Electrical Characteristics - CLKOUT (A:D) Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85C Parameter Symbol Conditions Min. Input Frequency HCSL termination Output Max. Voltage1,2 Voltage1,2 Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 25 660 863 VMIN -300 -53 250 377 Absolute Variation over all edges Modulation Frequency Fall Time1,2 Time1,2 Rise/Fall Time Variation1,2 200 MHz 1150 mV mV 550 mV 45 140 mV 29 125 ps Spread spectrum 30 32.9 33 kHz tOR From 0.175V to 0.525V 175 237 700 ps tOF From 0.525V to 0.175V 175 286 700 ps 73 125 ps 8 50 ps 52 55 % Skew between Outputs Duty Units MHz VMAX Jitter, Cycle-to-Cycle1,3 Rise Max. 25 Output Frequency Output Min. Typ. Cycle1,3 45 Time5 All outputs 100 ns Output Disable Time5 All outputs 100 ns 1.8 ms 30 ms Output Enable Stabilization Time tSTABLE From power-up VDD = 3.3V Spread Change Time tSPREAD Settling period after spread change 1 Test 1 setup is RS = 33RP = 50 with CL = 2pF, Rr = 475 (1%). 2 Measurement taken from a single-ended waveform. 3 Measurement taken from a differential waveform. 4 Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. 5 CLKOUT pins are tri-stated when OE is asserted low. CLKOUT is driven differential when OE is high unless its PD = low. Electrical Characteristics - Differential Phase Jitter TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5% PARAMETER Symbol tjphaseG1 tjphaseG2High Conditions PCIe Gen 1 PCIe Gen 2 10kHz < f < 1.5MHz PCIe Gen 2 1.5MHz < f < Nyquist (50MHz) tjphaseG3 PCIe Gen 3 tjphaseG2Lo Jitter, Phase Min Typ 30 SPEC Max 86 1 3 2.3 3.1 0.7 1 Units ps (p-p) ps (RMS) ps (RMS) ps (RMS) Notes 1,2,3 1,2,3 1,2,3 1,2,3 1 Guaranteed by design and characterization, not 100% tested in production. See http://www.pcisig.com for complete specs 2 3 Applies to 100MHz, spread off and 0.5% down spread only. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 10 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Conditions Max. Units Still air 93 C/W JA 1 m/s air flow 78 C/W JA 3 m/s air flow 65 C/W 20 C/W Marking Diagram (5V41236PGGI) Marking Diagram (5V41236PGG) 20 11 11 IDT5V412 36PGGI YYWW$ IDT5V412 36PGG YYWW$ 1 Typ. JA JC Thermal Resistance Junction to Case 20 Min. 1 10 10 Notes: 1.”**” denotes lot sequence; “YYWW” or “YWW” – Date code; “$” – mark code. 2. “G” after the two-letter package code designates RoHS compliant package. 3. “I” at the end of part number indicates industrial temperature range. 4. Bottom marking: country of origin if not USA. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 11 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/pgg20-package-outline-drawing-44-mm-body-065mm-pitch-tssop Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 5V41236PGG see page 11 Tubes 20-TSSOP 0 to +70C 5V41236PGG8 Tape and Reel 20-TSSOP 0 to +70C 5V41236PGGI Tubes 20-TSSOP -40 to +85C 5V41236PGGI8 Tape and Reel 20-TSSOP -40 to +85C “G” after the two-letter package code are the Pb-Free configuration, RoHS compliant. Revision History Date Description of Change September 26, 2011 Initial release. November 22, 2011 1. Changed title to “4 Output PCIe GEN1/2/3 Synthesizer” 2. Updated Differential Phase Jitter table. February 4, 2014 June 6, 2016 February 13, 17 April 4, 2017 September 18, 2019 Typo in VFQFPN T&R ordering information and VFQFPN device markings. 1. Updated “Operating Supply Current” parameters/values and Conditions in DC Electrical Characteristics table. 2. Updated RPUP, VIH and VIL conditions. 1. Updated Operating Supply Current [IDD] typical and maximum values. 2. Added typical values to AC Electrical Characteristics CLKOUT (A:D) table. 3. Updated typical values in Differential Phase Jitter table. 4. Updated 20-VFQFPN POD drawing. 1. Update “AC Electrical Characteristics - CLKOUT(A:D)” table values to latest PCIe specifications and characterization data. 2. Updated package outline drawings. 3. Updated legal disclaimer. Removed all references to 20-VFQFPN. IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 12 5V41236 SEPTEMBER 18, 2019 5V41236 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.idt.com/go/sales www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com DISCLAIMER Integrated Device Technology, Inc. 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