X28C512/X28C513
512K
64K x 8 Bit
5 Volt, Byte Alterable EEPROM
FEATURES
• Access time: 90ns
• Simple byte and page write
—Single 5V supply
• No external high voltages or VPP control
circuits
—Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
—Active: 50mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable Direct Write™ cell
—Endurance: 100,000 write cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
—Toggle bit polling
• Two PLCC and LCC pinouts
—X28C512
• X28C010 EPROM pin compatible
—X28C513
• Compatible with lower density EEPROMs
DESCRIPTION
The X28C512/513 is a 64K x 8 EEPROM, fabricated
with Xicor’s proprietary, high performance, floating
gate CMOS technology. Like all Xicor programmable
nonvolatile memories, the X28C512/513 is a 5V only
device. The X28C512/513 features the JEDEC
approved pin out for byte wide memories, compatible
with industry standard EPROMS.
The X28C512/513 supports a 128-byte page write
operation, effectively providing a 39µs/byte write cycle
and enabling the entire memory to be written in less
than 2.5 seconds. The X28C512/513 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion
of a write cycle. In addition, the X28C512/513 supports
the software data protection option.
BLOCK DIAGRAM
A7–A15
X Buffers
Latches and
Decoder
A0–A6
Y Buffers
Latches and
Decoder
CE
OE
WE
Control
Logic and
Timing
512Kbit
EEPROM
Array
I/O Buffers
and Latches
I/O0–I/O7
Data Inputs/Outputs
VCC
VSS
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Characteristics subject to change without notice.
1 of 24
X28C512/X28C513
PIN CONFIGURATIONS
TSOP
31
WE
A15
3
30
NC
A12
4
29
A14
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
X28C512
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE
A0
12
21
I/O5
I/O0
13
20
I/O4
I/O1
14
19
I/O3
I/O2
15
18
VSS
16
17
I/O2
A12
A15
NC
NC
VCC
WE
NC
OE
A10
CE
I/O7
PGA
I/O 3
I/O 5
19
21
I/O0
15
I/O 2
17
A1
13
A0
14
I/O 1
VSS
I/O 7
I/O 4
16
18
23
20
A2
12
A3
11
A4
10
A6
8
I/O1
A5
I/O 6
22
Bottom
View
9
A7
7
A15
A12
6
5
NC
2
NC
4
NC
3
PIN DESCRIPTIONS
Addresses (A0–A15)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption is reduced.
VCC
NC
CE
24
OE
A10
25
26
A11
27
A9
28
A8
29
A13
30
NC
36
34
32
NC
1
WE
35
NC
33
A14
31
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
30
32 31 29
1
28
6
7
27
26
8
X28C513
9
(Top View) 25
24
10
11
23
12
22
13 15 16 17 18 19 20
21
14
54 3 2
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28C512/513.
PIN NAMES
Symbol
Description
A0–A15
Address Inputs
I/O0–I/O7
Data Input/Output
WE
Write Enable
Output Enable (OE)
The Output Enable input controls the data output buffers and is used to initiate read operations.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C512/513
through the I/O pins.
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A2
A1
A0
I/O0
A14
A13
A8
A9
A11
I/O6
2
30
32 31 29
1
28
6
7
27
26
8
X28C512
25
9
(Top View)
24
10
11
23
12
22
13 15 16 17 18 19 20
21
14
54 3 2
I/O5
NC
X28C512
A7
A6
A5
A4
A3
I/O3
I/O4
I/O5
VCC
PLCC/LCC
NC
I/O3
I/O4
32
OE
A 10
CE
I/O 7
I/O6
I/O 5
I/O 4
I/O 3
NC
NC
V SS
NC
NC
I/O 2
I/O1
I/O 0
A0
A1
A2
A3
I/O1
I/O2
VSS
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A7
A12
A14
A15
VCC
WE
A13
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O1
I/O2
VSS
Plastic DIP
CERDIP
FLAt Pack
SOIC (R)
A 11
A9
A8
A13
A14
NC
NC
NC
WE
V CC
NC
NC
NC
NC
A15
A12
A7
A6
A5
A4
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CE
Chip Enable
OE
Output Enable
VCC
+5V
VSS
Ground
NC
No Connect
Characteristics subject to change without notice.
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X28C512/X28C513
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture eliminates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Write Operation Status Bits
The X28C512/513 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto
the I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28C512/513 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C512/513 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to one hundred twenty-eight bytes of data to
be consecutively written to the X28C512/513, prior to
the commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A7 through
A15) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by
the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected
within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively, the page write window is infinitely
wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
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DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O7)
The X28C512/513 features DATA polling as a method
to indicate to the host system that the byte write or
page write cycle has completed. DATA Polling allows a
simple bit test operation to determine the status of the
X28C512/513, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true
data.
Toggle Bit (I/O6)
The X28C512/513 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle, I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete, the toggling will cease, and the device will
be accessible for additional read or write operations.
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Characteristics subject to change without notice.
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X28C512/X28C513
DATA POLLING I/O7
Figure 2a. DATA Polling Bus Sequence
WE
Last
Write
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
A0–A15
An
An
An
Figure 2b. DATA Polling Software Flow
Write Data
X28C512/513
Ready
An
An
An
An
DATA Polling can effectively halve the time for writing to
the X28C512/513. The timing diagram in Figure 2a
illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method
of implementing the routine.
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO7
Compare?
No
Yes
Ready
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X28C512/X28C513
THE TOGGLE BIT I/O6
Figure 3a. Toggle Bit Bus Sequence
Last
WE Write
CE
OE
VOH
I/O6
*
HIGH Z
VOL
*
X28C512/513
Ready
* Beginning and ending state of I/O6 will vary.
Figure 3b. Toggle Bit Software Flow
provide a method for status checking in multiprocessor
applications. The timing diagram in Figure 3a illustrates
the sequence of events on the bus. The software flow
diagram in Figure 3b illustrates a method for polling the
Toggle Bit.
Last Write
HARDWARE DATA PROTECTION
The X28C512/513 provides three hardware features
that protect nonvolatile data from inadvertent writes.
Load Accum
From Addr N
– Noise Protection—A WE pulse typically less than
10ns will not initiate a write cycle.
– Default VCC Sense—All write functions are inhibited
when VCC is 3.6V.
Compare
Accum with
Addr N
Compare
Ok?
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data
integrity. Write cycle timing specifications must be
observed concurrently.
No
Yes
SOFTWARE DATA PROTECTION
X28C512
Ready
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an
array comprised of multiple X28C512/513 memories
that is frequently updated. Toggle Bit Polling can also
REV 1.0 6/27/00
The X28C512/513 offers a software controlled data
protection feature. The X28C512/513 is shipped from
Xicor with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read
and write access of the device once VCC was stable.
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Characteristics subject to change without notice.
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X28C512/X28C513
The X28C512/513 can be automatically protected during power-up and power-down without the need for
external circuits by employing the software data protection feature. The internal software data protection
circuit is enabled after the first write operation utilizing
the software algorithm. This circuit is nonvolatile and
will remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28C512/
513 is also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional
data to the device. Note: The data in the three-byte
enable sequence is not written to the memory array.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 4a and 4b for the
sequence. The three byte sequence opens the page
write window, enabling the host to write from one to
one hundred twenty-eight bytes of data. Once the page
load cycle has been completed, the device will automatically be returned to the data protected state.
Software Data Protection
Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write
VCC
(VCC)
0V
Data
Addr
AAA
5555
55
2AAA
A0
5555
Writes
ok
tWC
Write
Protected
CE
≤ tBLC MAX
WE
Byte
or
Page
Note: All other timings and control pins are per page write timing requirements
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X28C512/X28C513
Figure 4b. Write Sequence for Software Data
Protection
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Regardless of whether the device has previously been
protected or not, once the software data protected
algorithm is used and data has been written, the
X28C512/513 will automatically disable further writes,
unless another command is issued to cancel it. If no
further commands are issued the X28C512/513 will be
write protected during power-down and after any subsequent power-up. The state of A15 while executing the
algorithm is don’t care.
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data 80
to Address
5555
Write Data XX
to any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After tWC
Re-Enters Data
Protected State
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X28C512/X28C513
Resetting Software Data Protection
Figure 5a. Reset Software Data Protection Timing Sequence
VCC
Data
Addr
AAA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥ tWC
Standard
Operating
Mode
CE
WE
Note: All other timings and control pins are per page write timing requirements
Figure 5b. Software Sequence to Deactivate
Software Data Protection
Note: Once initiated, the sequence of write operations
should not be interrupted.
SYSTEM CONSIDERATIONS
Write Data AA
to Address
5555
Because the X28C512/513 is frequently used in large
memory arrays it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipation and eliminate the possibility of contention where
multiple I/O pins share the same bus.
Write Data 55
to Address
2AAA
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is/are outputting data on the bus.
Write Data A0
to Address
5555
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC,
the X28C512/513 will be in standard operating mode.
REV 1.0 6/27/00
Because the X28C512/513 has two power modes,
(standby and active), proper decoupling of the memory
array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
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Characteristics subject to change without notice.
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X28C512/X28C513
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each 8 devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused
by the inductive effects of the PC board traces.
ICC (RD) by Temperature Over Frequency
70
5.0 VCC
60
Active Supply Current vs. Ambient Temperature
ICC (mA)
14
VCC = 5V
ICC (mA)
13
–55°C
+25°C
+125°C
50
40
30
12
20
11
10
10
0
6
9
12
15
Frequency (MHz)
9
8
–55
3
–10
+35
+80
+125
Ambient Temperature (°C)
Standby Supply Current vs. Ambient Temperature
0.24
VCC = 5V
0.22
ISB (mA)
0.2
0.18
0.16
0.14
0.12
0.1
–55
–10
+35
+80
+125
Ambient Temperature (°C)
REV 1.0 6/27/00
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Characteristics subject to change without notice.
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X28C512/X28C513
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
X28C512/513...................................–10°C to +85°C
X28C512I/513I...............................–65°C to +135°C
X28C512M/513M...........................–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage on any pin with
respect to VSS ......................................... –1V to +7V
D.C. output current ............................................... 5mA
Lead temperature
(soldering, 10 seconds) ..................................300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indicated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMEND OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
0°C
+70°C
X28C512/513
5V ±10%
Industrial
–40°C
+85°C
Military
–55°C
+125°C
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
ICC
Min.
Max.
Unit
Test Conditions
VCC current (active) (TTL inputs)
50
mA
CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = .4V/2.4V Levels @ f = 5MHz
ISB1
VCC current (standby) (TTL
inputs)
3
mA
CE = VIH, OE = VIL, All I/O’s = open, other
inputs = VIH
ISB2
VCC current (standby) (CMOS
inputs)
500
µA
CE = VCC – 0.3V, OE = VIL, All I/O’s = Open,
Other Inputs = VIH
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC, CE = VIH
(1)
Input LOW voltage
–1
0.8
V
(1)
VIH
Input HIGH voltage
2
VCC + 1
V
VOL
Output LOW voltage
0.4
V
IOL = 2.1mA
VOH
Output HIGH voltage
V
IOH = –400µA
VlL
Note:
2.4
(1) VIL min. and VIH max. are for reference only and are not tested.
POWER-UP TIMING
Symbol
(2)
(2)
tPUR
tPUW
REV 1.0 6/27/00
Parameter
Max.
Unit
Power-up to read operation
100
µs
Power-up to write operation
5
ms
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Characteristics subject to change without notice.
10 of 24
X28C512/X28C513
CAPACITANCE TA = +25°C, F = 1MHZ, VCC = 5V
Symbol
Parameter
CI/O(2)
(2)
CIN
Max.
Unit
Test Conditions
Input/output capacitance
10
pF
VI/O = 0V
Input capacitance
10
pF
VIN = 0V
ENDURANCE AND DATA RETENTION
Parameter
Min.
Max.
Unit
Endurance
10,000
Cycles per byte
Endurance
100,000
Cycles per page
Data retention
100
Years
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input and output timing levels
1.5V
WAVEFORM
MODE SELECTION
CE
OE
WE
Mode
I/O
Power
L
L
H
Read
DOUT
Active
L
H
L
Write
DIN
Active
High Z
Standby
H
X
X
Standby and
write inhibit
X
L
X
Write inhibit
—
—
X
X
H
Write inhibit
—
—
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
Output
1.37KΩ
Note:
100pF
(2) This parameter is periodically sampled and not 100%
tested.
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Characteristics subject to change without notice.
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X28C512/X28C513
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28C512-90 X28C512-12 X28C512-15 X28C512-20 X28C512-25
X28C513-90 X28C513-12 X28C513-15 X28C513-20 X28C513-25
Symbol
Parameter
Min.
Max.
Read cycle time
tCE
Chip enable access time
90
120
150
200
250
ns
tAA
Address access time
90
120
150
200
250
ns
tOE
Output enable access time
40
50
50
50
50
ns
tLZ
(3)
tOLZ
(3)
120
150
200
Max. Unit
tRC
(3)
90
Min. Max. Min. Max. Min. Max. Min.
250
ns
CE LOW to active output
0
0
0
0
0
ns
OE LOW to active output
0
0
0
0
0
ns
CE HIGH to high Z output
40
50
50
50
50
ns
tOHZ
OE HIGH to high Z output
40
50
50
50
50
ns
tOH
Output hold from address
change
tHZ
(3)
0
0
0
0
0
ns
Read Cycle
tRC
Address
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
Data I/O
tOH
tHZ
HIGH Z
Data Valid
Data Valid
tAA
Note:
(3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF
from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
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Characteristics subject to change without notice.
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X28C512/X28C513
WRITE CYCLE LIMITS
Symbol
tWC(4)
Parameter
Min.
Write cycle time
Max.
Unit
10
ms
tAS
Address setup time
0
ns
tAH
Address hold time
50
ns
tCS
Write setup time
0
ns
tCH
Write hold time
0
ns
tCW
CE pulse width
100
ns
tOES
OE HIGH setup time
10
ns
tOEH
OE HIGH hold time
10
ns
tWP
WE pulse width
100
ns
WE High recovery
100
ns
tWPH
tDV
Data valid
1
tDS
Data setup
50
ns
tDH
Data hold
0
ns
tDW
Delay to next write
10
µs
tBLC
Byte load cycle
0.2
100
µs
µs
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tDV
Data In
Data Valid
tDH
tDS
HIGH Z
Data Out
Note:
(4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
time the device requires to complete the internal write operation.
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Characteristics subject to change without notice.
13 of 24
X28C512/X28C513
CE Controlled Write Cycle
tWC
Address
tAS
tAH
tCW
CE
tWPH
tOES
OE
tOEH
tCS
tCH
WE
tDV
Data Valid
Data In
tDS
tDH
HIGH Z
Data Out
Page Write Cycle
OE(5)
CE
tWP
tBLC
WE
tWPH
Address*(6)
Last Byte
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
Byte n+2
tWC
*For each successive write within the page write operation, A7–A15 should be the same or
writes to an unknown address could occur.
Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
(6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
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Characteristics subject to change without notice.
14 of 24
X28C512/X28C513
DATA Polling Timing Diagram(7)
Address
An
An
An
CE
WE
tOEH
tOES
OE
tDW
I/O7
DIN = X
DOUT = X
DOUT = X
tWC
Toggle Bit Timing Diagram
CE
WE
tOES
tOEH
OE
tDW
I/O6
HIGH Z
*
*
tWC
*Starting and ending state will vary, depending upon actual tWC.
Note:
(7) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
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Characteristics subject to change without notice.
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Hermetic Dual In-Line Package Type D
1.690 (42.95)
Max.
0.610 (15.49)
0.500 (12.70)
Pin 1
0.005 (0.13) Min.
0.100 (2.54) Max.
Seating
Plane
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
0.065 (1.65)
0.033 (0.84)
Typ. 0.055 (1.40)
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X28C512/X28C513
PACKAGING INFORMATION
32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.015 (0.38)
0.003 (0.08)
0.020 (0.51) x 45° Ref.
0.095 (2.41)
0.075 (1.91)
Pin 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
TYP. (4) PLCS.
0.200 (5.08)
BSC
0.015 (0.38)
Min.
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.050 (1.27) BSC
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.458 (11.63)
0.442 (11.22)
0.120 (3.05)
0.060 (1.52)
0.458 (11.63)
––
0.560 (14.22)
0.540 (13.71)
0.558 (14.17)
––
0.088 (2.24)
0.050 (1.27)
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
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Characteristics subject to change without notice.
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Ceramic Flat Pack Type F
1.228 (31.19)
1.000 (25.40)
Pin 1 Index
1
0.019 (0.48)
0.015 (0.38)
32
0.050 (1.27) BSC
0.830 (21.08) Max.
0.045 (1.14) Max.
0.005 (0.13) Min.
0.488
0.430 (10.93)
0.007 (0.18)
0.004 (0.10)
0.120 (3.05)
0.090 (2.29)
0.370 (9.40)
0.270 (6.86)
0.347 (8.82)
0.330 (8.38)
0.045 (1.14)
0.026 (0.66)
0.030 (0.76)
Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.045 (1.14) x 45°
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
±0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.300 (7.62)
Ref.
0.048 (1.22)
0.042 (1.07)
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
(10.16)Ref.
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
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19 of 24
X28C512/X28C513
PACKAGING INFORMATION
32-Lead Plastic Dual In-Line Package Type P
1.665 (42.29)
1.644 (41.76)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.500 (38.10)
Ref.
0.160 (4.06)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.125 (3.17)
0.110 (2.79)
0.090 (2.29)
0.070 (17.78)
0.030 (7.62)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
15°
Typ. 0.010 (0.25)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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X28C512/X28C513
PACKAGING INFORMATION
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom.
See Detail “A”
For Lead
Information
0.020 Min.
0.165 Typ.
0.340
±0.007
0.015 R Typ.
0.015 R
Typ.
0.035 Typ.
0.035 Min.
Detail “A”
0.050"
Typical
0.0192
0.0138
0.050"
Typical
0.840
Max.
0.750
±0.005
0.050
0.560"
Typical
FOOTPRINT
0.030" Typical
32 Places
0.440 Max.
0.560 Nom.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
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X28C512/X28C513
PACKAGING INFORMATION
36-Lead Ceramic Pin Grid Array Package Type K
15
17
19
21
22
A
0.008 (0.20)
13
14
12
11
16
18
20
23
24
25
26
0.050 (1.27)
A
10
9
27
28
8
7
29
30
NOTE: Leads 5, 14, 23, & 32
Typ. 0.100 (2.54)
All Leads
6
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
5
2
36
34
32
4
3
1
35
33
31
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
Pin 1 Index
0.770 (19.56)
0.750 (19.05)
SQ
A
0.020 (0.51)
0.016 (0.41)
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
REV 1.0 6/27/00
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Characteristics subject to change without notice.
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X28C512/X28C513
PACKAGING INFORMATION
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
0.035 (0.889) Pin #1 Ident
O 0.040 (1.016) 0.005 (0.127) Dp.
O 0.030 (0.762) X 0.003 (0.076) Dp.
(0.038)
0.965
0.048 (1.219)
1
0.0197 (0.500)
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° Typ.
A
0.0025 (0.065)
Seating
Plane
0.557 (14.148)
0.547 (13.894)
Seating
Plane
0.010 (0.254)
0.006 (0.152)
0.040 (1.016)
Detail A
0.032 (0.813) Typ.
0.006 (0.152)
Typ.
4° Typ.
0.017 (0.432)
0.017 (0.432)
0.020 (0.508) Typ.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
Solder
Pads
FOOTPRINT
(0.012 ± 0.002)
Typical
40 Places
0.17 (0.007)
0.03 (0.001) 1.30 ± 0.05
(0.051 ± 0.002)
15 Eq. Spc.@ 0.50 ± 0.04
0.0197 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) Overall
Tol. Non-Cumulative
0.50 ± 0.04
(0.0197 ± 0.0016)
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
REV 1.0 6/27/00
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Characteristics subject to change without notice.
23 of 24
X28C512/X28C513
Ordering Information
X28C512
X
X
-X
Access Time
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
X28C513
Device
X
X
-X
Access Time
–90 = 90ns
–12 = 120ns
–15 = 150ns
–20 = 200ns
–25 = 250ns
Package
D = 32-Lead CerDip
E = 32-Pad LCC
F = 32-Lead Flat Pack
J = 32-Lead PLCC
K = 36-Lead Pin Grid Array
P = 32-Lead Plastic Dip
R = 32-Lead Ceramic SOIC
T = 40-Lead TSOP
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = Mil-STD-883
Package
E = 32-Pad LCC
J = 32-Lead PLCC
LIMITED WARRANTY
©Xicor, Inc. 2000 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
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Characteristics subject to change without notice.
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