STFU15NM65N

STFU15NM65N N-channel 650 V, 0.35 Ω typ., 12 A MDmesh™ II Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2    3 Order code VDS RDS(on) max ID STFU15NM65N 650 V 0.38 Ω 12 A 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Applications TO-220FP ultra narrow leads  Figure 1: Internal schematic diagram Switching applications Description This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packaging STFU15NM65N 15NM65N TO-220FP ultra narrow leads Tube September 2015 DocID027631 Rev 2 This is information on a product in full production. 1/12 www.st.com Contents STFU15NM65N Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuit ....................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 TO-220FP ultra narrow leads package information ........................... 9 Revision history ............................................................................ 11 DocID027631 Rev 2 STFU15NM65N 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain source voltage 650 V VGS Gate source voltage ± 25 V Drain current (continuous) at TC = 25 °C 12(1) Drain current (continuous) at TC = 100 °C 7.56 ID A IDM(2) Drain current (pulsed) 48 A PTOT Total dissipation at TC = 25 °C 30 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V 15 V/ns - 55 to 150 °C dv/dt (3) Tstg Peak diode recovery voltage slope Storage temperature Tj Operating junction temperature Notes: (1)Limited (2)Pulse (3)I SD by maximum junction temperature. width limited by safe operating area. ≤ 12 A, di/dt ≤ 400 A/µs; VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS. Table 3: Thermal data Symbol Parameter Value Rthj-case Thermal resistance junction-case max 4.17 Rthj-amb Thermal resistance junction-ambient max 62.5 Unit °C/W Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) DocID027631 Rev 2 Value Unit 3 A 187 mJ 3/12 Electrical characteristics 2 STFU15NM65N Electrical characteristics (TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage ID = 1 mA, VGS = 0 V Min. Typ. Max. 650 Unit V 1 µA VDS = 650 V, TC = 125 °C 100 µA Gate-body leakage current (VDS = 0) VGS = ± 25 V ±100 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 6 A 0.35 0.38 Ω Min. Typ. Max. Unit - 983 - - 57 - - 4.5 - IDSS Zero gate voltage drain current (VGS = 0) IGSS VDS = 650 V 2 Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 146 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 4.9 - Ω Qg Total gate charge - 33.3 - - 5.7 - - 17 - Qgs Gate-source charge Qgd Gate-drain charge VDS = 50 V, f = 1 MHz, VGS = 0 V VDD = 520 V, ID = 12 A, VGS = 10 V pF nC Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Test conditions Turn-on delay time Rise time Turn-off delay time VDD = 325 V, ID = 6 A, RG = 4.7 Ω, VGS = 10 V Fall time DocID027631 Rev 2 Min. Typ. Max. - 55.5 - - 8.5 - - 14 - - 11.4 - Unit ns STFU15NM65N Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 12 A ISDM(1) Source-drain current (pulsed) - 48 A VSD(2) Forward on voltage - 1.6 V trr ISD = 12 A, VGS = 0 V Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current trr ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current ISD = 12 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C - 428 ns - 4.7 µC - 21.5 A - 570 ns - 6.2 µC - 22 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID027631 Rev 2 5/12 Electrical characteristics 2.1 6/12 STFU15NM65N Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Static drain-source on-resistance Figure 7: Gate charge vs gate-source voltage DocID027631 Rev 2 STFU15NM65N Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Source-drain diode forward characteristics Figure 12: Normalized V(BR)DSS vs temperature DocID027631 Rev 2 7/12 Test circuit 3 8/12 STFU15NM65N Test circuit Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID027631 Rev 2 STFU15NM65N 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 19: TO-220FP ultra narrow leads package outline 8576148_1 DocID027631 Rev 2 9/12 Package information STFU15NM65N Table 9: TO-220FP ultra narrow leads mechanical data mm Dim. Min. 10/12 Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID027631 Rev 2 2.54 2.70 STFU15NM65N 5 Revision history Revision history Table 10: Document revision history Date Revision Changes 16-Mar-2015 1 Initial release 09-Sep-2015 2 Datasheet status promoted from preliminary to production data. DocID027631 Rev 2 11/12 STFU15NM65N IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 12/12 DocID027631 Rev 2