STG4210QTR

STG4210 Low voltage 1 Ω dual SPST analog switch Features ■ Ultra low power dissipation: ICC = 0.2 μA (max.) at TA = 85 °C ) s ( t c u d o ) r s ( P t c e t u e d l o o r s Description P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ■ RPEAK = 1.30 Ω max (TA = 25 °C) at VCC = 4.3 V ■ Wide operating voltage range: VCC (opr) = 1.65 to 4.3 V single supply ■ 4.3 V tolerant and 1.8 V compatible threshold on digital control input at VCC = 1.65 to 4.3 V ■ Typical bandwidth (-3 dB) at 58 MHz ■ Latch-up performance exceeds 100 mA per JESD 78, Class II ■ ESD performance exceeds JESD22 2000-V human body model (A114-A) QFN10L (1.8 x 1.4 mm) The STG4210 is a high-speed CMOS low voltage dual analog SPST (single pole single throw) switch fabricated in silicon gate C2MOS technology. The STG4210 is designed to operate from 1.65 to 4.3 V, making this device ideal for portable applications. The SELn inputs are provided to control the switch operation. The switch Sn is “on” (connected to common ports Dn) when the SELn input is held high and “off” (high impedance state exists between the two ports) when SELn is held low. Additional key features are fast switching speed and ultra low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. Table 1. Device summary Order code Package Packaging STG4210QTR QFN10L (1.8 x 1.4 mm) Tape and reel August 2008 Rev 1 1/21 www.st.com 21 Table of contents STG4210 Table of contents 1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 STG4210 Pin settings Pin connection (top through view) NC SEL1 Figure 1. D1 1 Pin settings 10 9 8 1 GND ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 7 S2 VCC 3 6 NC 4 5 D2 2 SEL2 S1 CS00035 Table 2. Pin description Pin number Symbol Name and function 1 NC No connection 2 S1 Independent channel 3 VCC Positive supply voltage 4 SEL2 Selection control 5 D2 Common channel 6 NC No connection 7 S2 Independent channel 8 GND Ground (0 V) 9 SEL1 Selection control 10 D1 Common channel 3/21 Logic diagram 2 STG4210 Logic diagram Figure 2. Logic block diagram SEL1 S1 D1 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O S2 D2 SEL2 CS00066 Table 3. Truth table 1. High impedance 4/21 SELn Switch Sn L OFF(1) H Sn is connected to Dn STG4210 3 Maximum rating Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol VCC Parameter Value Supply voltage VIC DC control input voltage VO DC output voltage IIKC DC input diode current on control pin (VSEL < 0 V) IIK DC input diode current (VSEL < 0 V) IOK DC output diode current IO DC output current IOP DC output current peak (pulse at 1 ms, 10% duty cycle) e t e l so b O TL b O - Power dissipation at TA=70 °C(1) u d o Pr (s) V -0.5 to 5.5 V Lead temperature (10 sec) Pr ) s t( -0.5 to VCC + 0.5 V − 50 mA c u d ± 50 ro P e let so ICC or IGND DC VCC or ground current Storage temperature -0.5 to VCC + 0.5 u d o )- s ( t c V ct DC input voltage TSTG (s) -0.5 to 5.5 VI PD Unit mA ± 20 mA ± 300 mA ± 500 mA ± 100 mA 1120 mW -65 to 150 °C 300 °C t c u 1. Derate above 70 °C by 18.5 mW/°C ete l o s b O d o r P e t e l o s b O 5/21 Maximum rating 3.1 STG4210 Recommended operating conditions Table 5. Recommended operating conditions Symbol VCC Parameter Supply voltage Value Unit 1.65 to 4.3 V VI Input voltage 0 to VCC V VIC Control input voltage 0 to 4.3 V VO Output voltage 0 to VCC V Top Operating temperature -40 to 85 °C VCC = 1.65 V to 2.7 V ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O dt/dv 6/21 Input rise and fall time control input 0 to 20 ns/V VCC = 3.0 V to 4.3 V 0 to 10 STG4210 4 Electrical characteristics Electrical characteristics Table 6. DC specifications Value Symbol VCC (V) Parameter TA = 25 °C Test condition Min VIH High level input voltage Typ Max 0.65 VCC 0.65 VCC 2.3 −2.5 1.2 1.2 2.7 −3.0 1.3 1.3 3.0 −3.6 1.4 4.3 1.5 3.0 −3.6 o s b 4.3 4.3 O ) e t le 3.6 RPEAK Switch ON resistance t(s 3.0 c u d e t e l ΔRON o s b O ON resistance match (1) RFLAT 1.8 (s) ct u d o r P e t e l o s b O o r P 2.7 ON resistance flatness (2) IOFF OFF state leakage current (Sn), (Dn) ISEL SEL leakage current 4.3 VS = 0 V to VCC IS = 100 mA so b O - 3.6 3.0 ) s t( 0.25 uc 0.25 Pr V 0.25 0.25 od 0.30 (s) 1.5 d o r P e let 2.7 −3.0 Max t c u 1.4 0.25 2.3 −2.5 Low level input voltage Min 1.65 −1.95 1.65 −1.95 VIL -40 to 85 °C Unit 0.25 V 0.30 0.40 0.40 1.10 1.3 1.5 1.15 1.4 1.6 1.25 1.5 1.8 1.35 1.6 1.9 2.20 2.9 3.5 Ω 10 14 VS at RPEAK IS = 100 mA 14 mΩ 2.7 15 1.8 30 4.3 0.45 0.50 0.55 0.45 0.50 0.55 0.50 0.55 0.60 2.7 0.55 0.60 0.70 1.8 1.10 1.70 2.00 VS = 0.3 or 4 V ±0.1 ±1 μA VSEL = 0 to 4.3 V ±0.05 ±1 μA 3.6 3.0 4.3 0 −4.3 VS = 0 to VCC IS = 100 mA Ω 7/21 Electrical characteristics Table 6. STG4210 DC specifications Value Symbol VCC (V) Parameter TA = 25 °C Test condition Min ICC Quiescent supply current ICCLV Quiescent supply current low voltage driving 1.65 −4.3 4.3 Typ Max VSEL = VCC or GND -40 to 85 °C Unit Min Max ±0.05 ±0.2 VSEL = 1.65 V ±37 ±50 ±100 VSEL = 1.80 V ±33 ±40 ±50 VSEL = 2.60 V ±12 ±20 ±30 μA μA ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 1. ΔRON = RON(max) - RON(min). 2. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns) Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min tPLH, tPHL Propagation delay 1.65 −−1.95 0.45 2.3 −−2.7 0.45 3.0 −−3.3 0.30 3.6 −−4.3 0.30 Turn-ON time 2.3 −−2.7 3.0 −−3.3 1.65 −−1.95 VS = 0.8 V Turn-OFF time 2.3 −−2.7 3.0 −−3.3 1.65 −−1.95 Charge injection 2.3 −−2.7 3.0 −−3.3 8/21 Off isolation(1) 1.65 −4.3 120 65 85 90 42 55 65 40 55 65 18 30 40 16 30 40 15 30 40 45 43 CL = 100 pF RL = 1 MΩ VGEN = 0 V RGEN = 0 Ω 3.6 −−4.3 OIRR Max ns VS = 1.5 V 3.6 −−4.3 Q Min ns VS = 1.5 V 3.6 −−4.3 tOFF Max Unit ns 1.65 −−1.95 VS = 0.8 V tON Typ -40 to 85 °C 51 pC 51 49 VS = 1 VRMS f = 100 KHz -66 dB STG4210 Electrical characteristics Table 7. AC electrical characteristics (CL = 35 pF, RL = 50 Ω, tr = tf ≤5 ns) Value Symbol Parameter VCC (V) Test condition TA = 25 °C Min Xtalk THD Crosstalk 1.65 −4.3 Total harmonic distortion 2.3 −4.3 -3dB bandwidth 1.65 −4.3 VS = 1 VRMS f = 100 KHz f = 20 Hz to 20 kHz RL = 600 Ω CL = 50 pF VIN = 2 VP-P VDC = VCC/2 Typ Max -40 to 85 °C Min Unit Max -72 dB 0.01 % ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O BW RL = 50 Ω Signal = 0 dBm 58 VCC = 0 V 9 CSEL Control pin input capacitance CON Port capacitance when switch is enabled 3.3 f = 1 MHz 113 COFF Port capacitance when switch is disabled 3.3 f = 1 MHz 85 MHz pF 1. Off isolation = 20 Log10 (VD/VS), VD = output. VS = input at off switch 9/21 Test circuit 5 STG4210 Test circuit Figure 3. ON resistance I DS V ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O V CC S1 D VS IN GND GND CS14072 10/21 STG4210 Test circuit Figure 4. OFF leakage 6 ## ) ) 3/&& $ 3 $/&& ! ! 6 33 6 $ ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ). 6 ## '.$ !-6 Figure 5. OFF isolation V CC S1 D VOUT 50 IN GND GND CS00372 11/21 Test circuit STG4210 Figure 6. Bandwidth V CC D S1 V OUT 50 Ω VS ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O VCC IN GND CS00067 Figure 7. Switch-to-switch crosstalk D1 SEL1 D2 SEL2 12/21 STG4210 Test circuit Figure 8. Test circuit ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 1. CL = 5/35 pF or equivalent (includes jig and probe capacitance) 2. RL = 50 Ω or equivalent 3. RT = ZOUT of pulse generator (typically 50 Ω) 13/21 Application diagram 6 STG4210 Application diagram Figure 9. Application diagram R Class-D output BB L ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O S1 D1 S2 D2 SEL1=HIGH 14/21 SEL2=HIGH STG4210 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 10. QFN10L (1.8 x 1.4 mm) package outline ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 7936408 Rev.D 15/21 Package mechanical data STG4210 Table 2. QFN10L(1.8 x 1.4 mm) mechanical data Symbol Millimeters Min Typ Max A 0.45 0.50 0.55 A1 0 0.02 0.05 A3 b 0.127 0.15 0.20 0.25 D 1.75 1.80 1.85 E 1.35 1.40 1.45 e L 0.40 0.35 0.40 0.45 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 16/21 STG4210 Package mechanical data Figure 11. QFN10L (1.8 x 1.4 mm) footprint recommendations ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Figure 12. QFN10L (1.8 x 1.4 mm) carrier tape 17/21 Package mechanical data STG4210 Figure 13. QFN10L (1.8 x 1.4 mm) reel information - front side ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 18/21 STG4210 Package mechanical data Figure 14. QFN10L(1.8 x 1.4 mm) reel information ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 19/21 Revision history 8 STG4210 Revision history Table 8. Document revision history Date Revision 26-Aug-2008 1 Changes Initial release. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 20/21 STG4210 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Please Read Carefully: Information in this document is provided solely in connection with ST products. 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