STGAP1S
gapDRIVE™: galvanically isolated single gate driver
Datasheet - production data
Applications
600/1200 V inverters
Inverters for EV\HEV
EV charging stations
Industrial drives
SO24W
UPS equipment
DC/DC converters
Features
Solar inverters
Qualified for automotive applications according
to AEC-Q100
Description
High voltage rail up to 1500 V
The STGAP1S gapDRIVE™ is a galvanically
isolated single gate driver for N-channel
MOSFETs and IGBTs with advanced protection,
configuration and diagnostic features. The
architecture of the STGAP1S isolates the channel
from the control and the low voltage interface
circuitry through true galvanic isolation.
The gate driver is characterized by 5 A capability,
making the device also suitable for high power
inverter applications such as motor drivers in
hybrid and electric vehicles and in industrial
drives. The output driver section provides a railto-rail output with the possibility to use a negative
gate driver supply.
The input to output propagation delay results
contained within 100 ns, providing high PWM
control accuracy.
Protection functions such as the Miller clamp,
desaturation detection, dedicated sense pin for
overcurrent detection, output 2-level turn-off, VCE
overvoltage protection, UVLO and OVLO are
included to easily design high reliability systems.
Open drain diagnostic outputs are present and
detailed device conditions can be monitored
through the SPI. Each function's parameter can
be programmed via the SPI, making the device
very flexible and allowing it to fit in a wide range of
applications. Separate sink and source outputs
provide high flexibility and bill of material
reduction for external components.
Driver current capability: 5 A sink/source
current at 25 °C
dV/dt transient immunity ± 50 V/ns in full
temperature range
Overall input/output propagation delay: 100 ns
Separate sink and source for easy gate driving
configuration
Negative gate drive ability
Active Miller clamp
Desaturation detection
SENSE input
VCE active clamping
Output 2-level turn-off
Diagnostic status output
UVLO and OVLO functions
Programmable input deglitch filter
Asynchronous stop command
Programmable deadtime, with violation error
SPI interface for parameters programming
Temperature warning and shutdown protection
Self-diagnostic routines for protection features
Full effective fault protection
May 2015
This is information on a product in full production.
DocID027190 Rev 3
1/67
www.st.com
Contents
STGAP1S
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Logic supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
2/67
6.1
Low voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2
High voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3
Power-up, power-down and “safe state” . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4
Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
Inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.2
Deadtime and interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3
Hardware RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.4
Power supply UVLO and OVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.5
Thermal warning and shutdown protection . . . . . . . . . . . . . . . . . . . . . . . 30
7.6
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.7
VCE active clamping protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.8
SENSE overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID027190 Rev 3
STGAP1S
Contents
7.9
Miller clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.10
2-level turn-off function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Always . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.10.2
Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.10.3
Never . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.11
Failure management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.12
Asynchronous stop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.13
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.14
Security check functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.15
8
7.10.1
7.14.1
GON to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.14.2
GOFF to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.14.3
SENSE comparator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.14.4
SENSE resistor check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.14.5
DESAT comparator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Register corruption protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CRC protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
Programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1
9.2
SPI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.1
StartConfig and StopConfig commands . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.2
WriteReg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1.3
ReadReg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.1.4
ResetStatus and GlobalReset commands . . . . . . . . . . . . . . . . . . . . . . . 49
9.1.5
Sleep command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.1.6
NOP command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers and flags description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.1
CFG1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.2
CFG2 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3
CFG3 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.4
CFG4 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.2.5
CFG5 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2.6
STATUS1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.2.7
STATUS2 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.8
STATUS3 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DocID027190 Rev 3
3/67
67
Contents
STGAP1S
9.2.9
TEST1 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.10
DIAG1 and DIAG2 registers (low voltage side) . . . . . . . . . . . . . . . . . . . 61
10
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SO24W package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4/67
DocID027190 Rev 3
STGAP1S
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) . . . . . . . . . . . . . . . . . . . . . . . . 13
DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) . . . . . . . . . . . . . . . . . . . . . . . . 14
Isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IEC 60747-5-2 isolation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Isolation voltage as per UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Inputs true table (device NOT in “safe state”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CRC byte examples (from host to device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CRC byte examples (from device to host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
StartConfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
StopConfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
WriteReg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ReadReg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ResetStatus command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GlobalReset command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Sleep command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
NOP command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CRC enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VDD supply voltage UVLO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SD pin FAULT management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
IN-/DIAG2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Input deglitch time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CFG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SENSE threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DESAT current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DESAT threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CFG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2LTOth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2-level turn-off time value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CFG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VH and VL supply voltages OVLO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
UVLO protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
VL negative supply voltage UVLO threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
VH positive supply voltage UVLO threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CFG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2LTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SENSE comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DESAT comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Miller clamp feature enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DocID027190 Rev 3
5/67
67
List of tables
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
6/67
STGAP1S
STATUS1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STATUS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
STATUS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STATUS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STATUS3 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
STATUS3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
TEST1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DIAG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DIAG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Relation between DIAG1/2 bits and failure conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SO24W package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DocID027190 Rev 3
STGAP1S
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Low voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
High voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
HW cross conduction prevention in half-bridge configuration with two single gate
drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transitions causing the DT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Synchronous control signal edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Control edges signal overlapped, example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Control edges signal overlapped, example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Control edges signal not overlapped and outside DT (direct control) . . . . . . . . . . . . . . . . . 28
DESAT protection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Example of VCE active clamping protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VCECLAMP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Example of short turn-on pulses when 2LTO occurs at each cycle . . . . . . . . . . . . . . . . . . 34
Example of short turn-off pulse when 2LTO occurs at each cycle . . . . . . . . . . . . . . . . . . . 34
Example of operation with 2LTO in “Fault” mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Gate paths check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SENSE comparator and resistor check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DESAT comparator check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SPI daisy chain connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI daisy chain connection example when bootstrap technique is used for high-side
drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Block diagram of the CRC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Typical application diagram in half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SO24W package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SO24W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
DocID027190 Rev 3
7/67
67
Block diagram
1
STGAP1S
Block diagram
Figure 1. Block diagram
VDD
3V3
Voltage Reg
VCECLAMP
VREG
IDESAT
SD
DESAT
+
VDESATth
IN+
IN-/DIAG2
Control
Logic
DIAG1
I
S
O
L
A
T
I
O
N
VH
UVLO
VH
GON
Floating
Section
Control
Logic
Level
Shifter
GOFF
CLAMP
VL
UVLO
VL
+
VREGISO
V2LTOth
GND
Floating ground
GNDISO
+
VDD
VCLAMPth
CK
SDI
SDO
8/67
SENSE
+
CS
VSENSEth
SPI
ASC
DocID027190 Rev 3
STGAP1S
2
Pin connection
Pin connection
Figure 2. Pin connection (top view)
GND
1
24
ASC
SDO
2
23
VL
SDI
3
22
CLAMP
CS
4
21
GOFF
CK
5
20
GON
VREG
6
19
VCECLAMP
VDD
7
18
DESAT
IN-/DIAG2
8
17
VH
IN+
9
16
SENSE
10
15
VREGISO
DIAG1
SD
11
14
VL
GND
12
13
GNDISO
Table 1. Pin description
Pin no.
Pin name
Type
7
VDD
Power supply
Internal 3.3 V regulator input supply pin
6
VREG
Power supply
Internal 3.3 V regulator output and supply pin
11
SD
Logic input
Shutdown input (active low)
9
IN+
Logic input
Gate command input
8
IN-/DIAG2
Logic input/open drain output
10
DIAG1
Open drain output
1, 12
GND
Ground
Low voltage section ground
4
CS
Logic input
SPI chip select (active low)
5
CK
Logic input
SPI clock
3
SDI
Logic input
SPI serial data input
2
SDO
Logic output
SPI serial data output
19
VCECLAMP
Analog input
VCE active clamping protection
18
DESAT
Analog input
Desaturation protection
15
VREGISO
Power supply
Internal regulator output pin for decoupling
17
VH
Power supply
Positive voltage supply
20
GON
Analog output
Gate source output
21
GOFF
Analog output
Gate sink output
22
CLAMP
Analog output
Miller clamp
DocID027190 Rev 3
Function
Gate command input /open drain diagnostic
output
Open drain diagnostic output
9/67
67
Pin connection
STGAP1S
Table 1. Pin description (continued)
10/67
Pin no.
Pin name
Type
14, 23
VL
Power supply
13
GNDISO
Ground
High voltage section (isolated) ground
16
SENSE
Analog input
Sense input for overcurrent protection
24
ASC
Analog input
Asynchronous stop command
DocID027190 Rev 3
Function
Negative supply voltage or ground
STGAP1S
Electrical data
3
Electrical data
3.1
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Test condition
Min.
Max.
Unit
50
V/ns
dVISO/dt
Common mode transient immunity
VDD
Integrated 3.3 V voltage regulator
input voltage vs. GND
-0.30
6.50
V
VREG
Integrated 3.3 V voltage regulator
output voltage vs. GND
-0.30
3.60
V
Isolated logic supply voltage vs.
GNDISO
-0.30
3.60
V
Logic pins voltage vs. GND
-0.30
VDD + 0.30
V
VHL
Differential supply voltage
(VH vs. VL)
-0.30
40
V
VH
Positive supply voltage
(VH vs. GNDISO)
-0.30
40
V
VL
Negative supply voltage
(VL vs. GNDISO)
-15
0.30
V
VL - 0.30
VH + 0.30
V
VREG_ISO
VLOGIC
VOUT
VCM = 1500 V
Voltage on gate driver outputs
(GON, GOFF, CLAMP vs. VL)
VDESAT
Voltage on DESAT pin vs. GNDISO
-0.30
VH + 0.30
V
VSENSE
Voltage on SENSE pin vs. GNDISO
-2
(VH + 0.30, 20)min
V
VL - 0.30
VH + 0.30
V
-0.30
VH + 0.30
V
20
mA
-0.30
6.50
V
VCECLAMP
Voltage on VCECLAMP pin vs. VL
VASC
Voltage on ASC pin vs. GNDISO
IDIAGx
Open drain DC output current
VDIAGx
Open drain output voltage
VDIAGx < 0.8 V
TJ
Junction temperature
-40
150
°C
TS
Storage temperature
-50
150
°C
TA
Ambient temperature
-40
125
°C
65
mW
(TJ,max - TA)/Rth(JA) - PDin
W
100
A/(m·s)
PDin
Power dissipation input chip
PDout
Power dissipation output chip
dH/dt
Magnetic field immunity
ESD
Human body model
fsw = 1 MHz
2
DocID027190 Rev 3
kV
11/67
67
Electrical data
3.2
STGAP1S
Thermal data
Table 3. Thermal data
Symbol
Parameter
Value
Unit
Rth(JA)
(1)
65
°C/W
Min.
Max.
Unit
Thermal resistance junction to ambient
1. The STGAP1S mounted on the EVALSTGAP1S rev 2.0 board (two-layer FR4 PCB).
3.3
Recommended operating conditions
Table 4. Recommended operating conditions
Parameter
Test
condition
Symbol
Pin
VH
17
Positive supply voltage
(VH vs. GNDISO)
4.50(1)
36
V
VL
14, 23
Negative supply voltage
(VL vs. GNDISO)
GNDISO - 10
GNDISO(2)
V
36
V
4.50
5.50
V
3
3.60
V
(VDD, 5)min
V
(VH, 15)min
V
VH - 1.50
V
1
MHz
Differential supply voltage
(VH vs. VL)
VHL
VDD
7
Integrated 3.3 V voltage regulator
input voltage vs. GND
VREG
6
Internal logic supply voltage vs. GND
VLOGIC
2, 3, 4, 5,
Logic pins voltage vs. GND
8, 9, 11
ASC
24
ASC pin voltage
VDESATth
18
Desaturation protection threshold
fSW
(3)
GNDISO
DESAT
enabled
Maximum switching frequency(4)
1. When UVLO is enabled this value is VHon,max.
2. When UVLO is enabled this value is VLon,min.
3. When VDD is connected to the VREG pin (refer to Section 6 on page 22).
4. Actual limit depends on power dissipation constraints.
12/67
DocID027190 Rev 3
STGAP1S
Electrical characteristics
4
Electrical characteristics
4.1
AC operation
Table 5. AC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO)
Symbol
Pin
tdeglitch
Parameter
Test condition
Input deglitch time
8, 9, 11
tINmin
Min. Typ. Max. Unit
INfilter = '11'
50
70
90
ns
INfilter = '01'
140
210
280
ns
INfilter = '10'
490
560
630
ns
20
ns
Minimum propagated input pulse
INfilter = '00' and (2LTO_EN = '0'
or 2LTOtime = 0x0)
tDon
8, 9, 11, 20
Input to output propagation
delay ON
Deglitch filter and 2LTO disabled
90
100
130
ns
tDoff
8, 9, 11, 21
Input to output propagation
delay OFF
Deglitch filter and 2LTO disabled
90
100
130
ns
tr
20
GON rise time
VL = 0 V;
CL = 2 nF, 10% ÷ 90%
25
ns
tf
21
GOFF rise time
VL = 0V
CL = 2 nF, 90% ÷ 10%
25
ns
PWD
8, 9, 11,
20, 21
4
10
ns
DT
8, 9, 20,
21
trelease
11
t > 100 ns
Pulse width distortion |tDon - tDoff| IN
Deglitch filter and 2LTO disabled
Deadtime
Minimum flag release time
DTset = '01'
205
250
295
DTset = '10'
650
800
945
DTset = '11'
985 1200 1415
SD = '0', SD_FLAG = '1'
DocID027190 Rev 3
105
ns
µs
13/67
67
Electrical characteristics
4.2
STGAP1S
DC operation
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.15
V
Logic inputs/output
SDO logic “0” output
voltage
I = 4 mA
Voh
SDO logic “1” output
voltage
I = 4 mA
IINh
INx logic “1” input bias
VIN = 5 V (pin 8 used as IN-)
current
Vol
2
8, 9
IINl
INx logic “0” input bias
VIN = 0 V(pin 8 used as IN-)
current
ISDh
SD logic “1” input bias
current
VSD = 5 V
SD logic “0” input bias
current
VSD = 0 V
11
ISDl
4.85
55
55
V
85
85
145
µA
0.10
µA
145
µA
0.10
µA
Rin_pd
8, 9, 11
Input pull-down
resistors
VIN = 5 V (pin 8 used as IN-)
35
60
85
k
Rin_pu
4
CS input pull-up
resistor
CS = GND
35
55
80
k
Vil
Vih
3, 4, 5, Low logic level voltage
8, 9, 11 High logic level voltage
0.29 · VDD 0.33 · VDD 0.37 · VDD
V
0.62 · VDD 0.66 · VDD 0.79 · VDD
V
Driver buffer section
IGON
IGOFF
20
21
Source short-circuit
current
Sink short-circuit
current
VIN < Vih, Tpulse < 5 s,
DC = 1%
Tj = 25 °C
Tj = -40 ÷ +125 °C
VIN < Vih, Tpulse < 5 s,
DC = 1%
Tj = 25 °C
Tj = -40 ÷ +125 °C
VGOFFL
21
GOFF output low level IGOFF = 0.1 A
voltage
IGOFF = 1 A
VGONH
20
GON output high level
voltage
SafeClp
14/67
20, 21,
GOFF active clamp
22
IGON = 0.1 A
IGON = 1 A
IGOFF = 0.2 A;
VH floating;
GON = GOFF = CLAMP
DocID027190 Rev 3
A
5
2.50
7
A
5
2.50
6
VL + 0.03
VL + 0.50
VL + 0.09
VL + 1
VL + 0.15
VL + 1.80
V
VH - 0.18
VH - 2.10
VH - 0.10
VH - 1.30
VH - 0.05
VH - 0.50
V
3
V
STGAP1S
Electrical characteristics
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
0.1 V < VREG < 3.0 V
60
120
VREG < 0.1 V
15
35
Unit
Supply voltage
IREG
6
VREG short-circuit
current (see
Section 7.3 on page
29)
mA
VDDon
VDD UVLO turn-on
threshold
3.95
4.10
4.30
V
VDDoff
VDD UVLO turn-off
threshold
3.65
3.80
4
V
VDD UVLO hysteresis
0.15
OVVDDon
VDD OVLO turn-on
threshold
5.30
5.50
5.90
V
OVVDDoff
VDD OVLO turn-off
threshold
5.40
5.70
6.10
V
OVVDDhys
VDD OVLO hysteresis
100
200
300
mV
VDD = 5 V;
SD = 5 V; INx = GND;
f = 0 Hz
5.20
6.50
7.50
mA
VDD = 5 V;
SD = 5 V;
fSW = fSW,max
7.50
8.50
9.50
mA
VHONth = '01'
9.40
10
10.50
VHONth = '10'
11.30
12
12.60
VHONth = '11'
13.15
14
14.70
VHONth = '01'
8.50
9
9.45
VHONth = '10'
10.35
11
11.55
VHONth = '11'
12.25
13
13.65
0.70
1
1.30
VLONth = '01'
-3.15
-3
-2.80
VLONth = '10'
-5.25
-5
-4.70
VLONth = '11'
-7.35
-7
-6.55
VLONth = '01'
-2.15
-2
-1.90
VLONth = '10'
-4.25
-4
-3.80
VLONth = '11'
-6.35
-6
-5.70
0.70
1
1.20
VDDhys
IQDD
7
7
VDD quiescent supply
current
VH UVLO turn-on
threshold
VHon
17
VH UVLO turn-off
threshold
VHoff
VH UVLO hysteresis
VHhyst
VL UVLO turn-on
threshold
VLon
14, 23
VLoff
VLhys
VL UVLO turn-off
threshold
VL UVLO hysteresis
DocID027190 Rev 3
V
V
V
V
V
V
V
15/67
67
Electrical characteristics
STGAP1S
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
VH OVLO turn-off
threshold
OVLO_EN = '1'
17.80
19
20
V
VH OVLO turn-on
threshold
OVLO_EN = '1'
16.90
18
18.90
V
OVVHhys
VH OVLO hysteresis
OVLO_EN = '1'
0.60
1
1.30
V
OVVLoff
VL OVLO turn-off
threshold
OVLO_EN = '1'
-10.50
-10
-9.40
V
OVVLon
14, 23 VL OVLO turn-on
threshold
OVLO_EN = '1'
-9.45
-9
-8.55
V
OVLO_EN = '1'
0.70
1
1.30
V
SD = 5 V;
IN+ = 5 V; IN- = GND
5
6.70
7.50
mA
SD = 5 V;
fSW = fSW,max;
No load
10
14
19
mA
VL = -5 V;
SD = 5 V;
IN+ = IN- = GND
300
420
550
A
DESATth = '000';
2.60
3
3.10
DESATth = '001'
3.60
4
4.20
DESATth = '010'
4.60
5
5.30
DESATth = '011'
5.50
6
6.30
DESATth = '100'
6.50
7
7.40
DESATth = '101'
7.40
8
8.40
DESATth = '110'
8.30
9
9.40
DESATth = '111'
9.30
10
10.50
DESATth = '100'(1)
10
20
30
DESATcur = '00';
VDESAT = 0 V
220
250
265
DESATcur = '01';
VDESAT = 0 V
440
500
525
DESATcur = '10';
VDESAT = 0 V
660
750
800
DESATcur = '11';
VDESAT = 0 V
885
1000
1050
VDESAT = 8 V
50
70
90
OVVHoff
OVVHon
17
VL OVLO hysteresis
OVVLhyst
IQH
IQL
17
14, 23
VH quiescent supply
current
VL quiescent supply
current
Desaturation protection
Desaturation threshold
VDESATth
tDESfilter
IDESAT
IDESoff
16/67
18
DESAT pin deglitch
filter
DESAT blanking
charge current
DESAT blanking
discharge current
DocID027190 Rev 3
V
ns
µA
mA
STGAP1S
Electrical characteristics
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
160
250
340
ns
VDESAT = VDESAth to
GOFF 90%
CLOAD = 10 nF
2LTO disabled
80
150
220
ns
SENSEth = '000'
88
100
112
SENSEth = '001'
110
125
140
SENSEth = '010'
135
150
165
SENSEth = '011'
158
175
192
SENSEth = '100'
185
200
215
SENSEth = '101'
235
250
268
SENSEth = '110'
285
300
315
SENSEth = '111'
380
400
420
95
120
DESAT protection fixed
blanking time
tBLK
18
tDESAT
DESAT protection
intervention time
SENSE overcurrent function
SENSE protection
threshold
VSENSEth
16
SENSE protection
intervention time
tSENSE
SENSEth = '111'
0 1 V step on VSENSE
to GOFF 90%;
CLOAD = 10 nF
2LTO disabled
mV
ns
2-level turn-off function
V2LTOth
21
2LTO threshold
2LTOth = '0000'
6.65
7.00
7.35
2LTOth = '0001'
7.12
7.50
7.88
2LTOth = '0010'
7.60
8.00
8.40
2LTOth = '0011'
8.07
8.50
8.93
2LTOth = '0100'
8.55
9.00
9.45
2LTOth = '0101'
9.02
9.50
9.98
2LTOth = '0110'
9.50
10.00
10.50
2LTOth = '0111'
9.97
10.50
11.03
2LTOth = '1000'
10.45
11.00
11.55
2LTOth = '1001'
10.92
11.50
12.08
2LTOth = '1010'
11.40
12.00
12.60
2LTOth = '1011'
11.87
12.50
13.13
2LTOth = '1100'
12.35
13.00
13.65
2LTOth = '1101'
12.82
13.50
14.18
2LTOth = '1110'
13.30
14.00
14.70
2LTOth = '1111'
13.77
14.50
15.23
DocID027190 Rev 3
V
17/67
67
Electrical characteristics
STGAP1S
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
t2LTOtime
Pin
21
Parameter
2LTO time
Test condition
Min.
Typ.
Max.
2LTOtime = '0001'
0.64
0.75
0.89
2LTOtime = '0010'
0.89
1.00
1.15
2LTOtime = '0011'
1.36
1.50
1.65
2LTOtime = '0100'
1.83
2.00
2.18
2LTOtime = '0101'
2.30
2.50
2.70
2LTOtime = '0110'
2.77
3.00
3.23
2LTOtime = '0111'
3.25
3.50
3.75
2LTOtime = '1000'
3.47
3.75
4.03
2LTOtime = '1001'
3.71
4.00
4.29
2LTOtime = '1010'
3.94
4.25
4.56
2LTOtime = '1011'
4.18
4.50
4.82
2LTOtime = '1100'
4.42
4.75
5.08
2LTOtime = '1101'
4.66
5.00
5.34
2LTOtime = '1110'
4.90
5.25
5.63
2LTOtime = '1111'
5.12
5.50
5.95
Unit
µs
Diagnostic outputs
Fault event to DIAGx Fault event to DIAGx
Low delay
90%
tDIAG1,2
5
µs
DIAG1 low level sink
current
VDIAG1 = 0.4 V
10
18
30
mA
IDIAG2
DIAG2 low level sink
current
VDIAG2 = 0.4 V
10
18
30
mA
RDIAG1,2
DIAGx pull-down
resistor
300
550
800
k
1.70
2
2.30
V
IDIAG1
8, 10
Clamp Miller function
VCLAMPth
ICLAMP
22
CLAMP voltage
threshold
CLAMP vs. GNDISO
Clamp short-circuit
current
VIN < Vih, Tpulse < 5 s,
DC = 1%
Tj = 25 °C
Tj = -40 ÷ +125 °C
Clamp low level output
ICLAMP = 1 A
voltage
VCLAMP_L
A
5
2.50
6
VL + 0.50
VL + 1
VL + 1.80
V
VCE clamping threshold
VL + 1.20
VL + 1.60
VL + 2
V
VCE clamping threshold
hysteresis
0.30
0.50
0.60
V
VCE active clamping protection
VVCECLth
VVCECLhyst
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DocID027190 Rev 3
STGAP1S
Electrical characteristics
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
Pin
tVCECLoff
Parameter
Test condition
VCE clamping time-out
19
tVCECL
Min.
Typ.
Max.
Unit
2
2.30
2.60
µs
VCE clamping
intervention time(1)
20
ns
ASC function
VASCl
Low logic level voltage
0.80
1.10
1.40
V
VASCh
High logic level voltage
1.80
2.20
2.40
V
IASCh
ASC logic “1” input bias
VASC = 5 V
current
55
100
145
µA
0.10
µA
70
k
250
ns
30
µs
0.84 x VH
V
15
µs
IASCl
24
ASC logic “0” input bias
VASC = 0 V
current
RASC
ASC pull-down
resistors
VASC = 5 V
35
tASC
ASC intervention time
VASC = 5 V
100
50
Functionality checks
Gate path check time
(GON/GOFF)(2)
tGchk
20, 21
VGchk
20
Gate path check
voltage (GON)
tRchk
16
SENSE resistor check
time
IGOFFchk
21
GOFF path check
current
ISENSERchk
16
tSENSEchk
tDESATchk
18
0.7 x VH
0.76 x VH
-420
-350
-280
µA
8
10
12
µA
SENSE comparator
check time
15
µs
DESAT comparator
check time
15
µs
SENSE resistor check
current
VSENSE < 1 V
Overtemperature protection
TWN
Warning temperature(1)
125
°C
TSD
Shutdown
temperature(1)
155
°C
Thys
Temperature
hysteresis(1)
20
°C
Standby
ISTBY_VDD
7
VDD standby current
VDD = 5 V
0.40
0.80
1
mA
tsleep
Standby time
SD = '0',
measured from CS rise
500
700
900
ns
tawake
Logic wake-up time(1)
SD = '1'
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5
µs
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Electrical characteristics
STGAP1S
Table 6. DC operation electrical characteristics
(Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued)
Symbol
SPI
Pin
Parameter
Test condition
Maximum SPI clock
frequency
tCKmax
trCK
tfCK
5
Typ.
Max.
Unit
SPI clock rise and fall
time
5
CL = 30 pF
MHz
25
ns
SPI clock high and low
time
75
ns
tsetCS
CS setup time
350
ns
tholCS
CS hold time
10
ns
Local register read
800
ns
Remote register read
30
Start configuration
22
Stop configuration
5
Reset status register
50
Reset remote register
25
Any other command
700
ns
SDI setup time
25
ns
SDI hold time
20
ns
thCK
tlCK
4
tdesCS
tsetSDI
tholSDI
CS deselect
3
tenSDO
tdisSDO
tvSDO
2
tholSDO
time(3)
µs
SDO enable time
38
ns
SDO disable time
47
ns
SDO valid time
57
ns
SDO hold time
37
ns
tSDLCSL
4,11
SD falling to CS falling
350
ns
tCSHSDH
4,11
CS rising to SD rising
350
ns
1. Characterization data, not tested in production.
2. The actual waiting time depends on the gate charge size.
3.
Min.
(1)
See Table 22 on page 50 and Section 9.1.3 on page 48.
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STGAP1S
5
Isolation
Isolation
Table 7. Isolation and safety-related specifications
Parameter
Symbol Value Unit
Conditions
Clearance
(minimum external air gap)
CLR
8
mm
Measured from input terminals to output terminals, shortest
distance through air
Creepage
(minimum external tracking)
CPG
8
mm
Measured from input terminals to output terminals, shortest
distance path along body
Comparative tracking index
(tracking resistance)
CTI
400
Isolation group
DIN IEC 112/VDE 0303 Part 1
II
Material group (DIN VDE 0110, 1/89, Table 1)
Table 8. IEC 60747-5-2 isolation characteristics
Parameter
Symbol
Test conditions
Characteristic
Installation classification (EN 60664-1,
Table 1 - see(1))
For rated mains voltage 150 V rms
For rated mains voltage 300 V rms
For rated mains voltage 600 V rms
Unit
I - IV
I - III
I - II
Pollution degree (EN 60664-1)
2
Maximum working isolation voltage
Input to output test voltage as
per IEC 60747-5-2
VIORM
VPR
1500
VPEAK
Method a, type test
VPR = VIORM × 1.6, tm = 10 s
Partial discharge < 5 pC
2400
VPEAK
Method b, 100 % production test
VPR = VIORM × 1.875, tm = 1 s
Partial discharge < 5 pC
2815
VPEAK
Transient overvoltage as per IEC 60747-5-2
(highest allowable overvoltage)
VIOTM
tini = 60 s type test
4000
VPEAK
Maximum surge isolation voltage
VIOSM
Type test
4000
VPEAK
VIO = 500 V at TS
>109
Isolation resistance
RIO
1. For three-phase systems the values in the table refer to the line-to-neutral voltage.
Table 9. Isolation voltage as per UL 1577
Description
Isolation withstand voltage, 1 min. (type test)
Isolation withstand test, 1 sec. (100% production)
Symbol
Characteristic
Unit
VISO
2500\3536
Vrms\VPEAK
VISOtest
3000\4245
Vrms\VPEAK
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Logic supply management
STGAP1S
6
Logic supply management
6.1
Low voltage section voltage regulator
The device integrates in the low voltage section a linear voltage regulator that can be used
to obtain the 3.3 V logic core supply voltage from an external 5 V supply voltage. If an
external 3.3 V supply voltage is available the VDD and VREG have to be shorted as shown
in Figure 3. The logic IOs are referred to the VDD voltage (see Table 6 on page 14 for
details).
Figure 3. Low voltage section 3.3 V voltage regulator
VDD from +5 V power supply
VDD from +3.3 V power supply
+5V
+3.3V
VDD
VDD
100 nF
LDO
Reg
LDO
Reg
VREG
4.7 µF
VREG
100 nF
4.7 µF
100 nF
Undervoltage protection is available on the VDD supply pin (disabled by default).
When the VDD voltage goes below the VDDoff threshold the device and its outputs goes in
“safe state” (see Section 6.3) and the UVLOD status flag is forced low. Once the protection
is triggered, the UVLOD flag is latched and the device remains in “safe state” until the
UVLOD flag is not released. See Section 7.11 on page 35 for indication on how the failure
flags can be released.
This protection can be enabled writing the UVLOD_EN bit of the CFG1 register (disabled by
default).
Overvoltage protection is available on the VDD supply pin.
When the VDD voltage goes over the OVVDDoff threshold the device and its outputs goes in
“safe state” and the OVLOD status flag is forced low. The device remains in “safe state” and
the OVLOD flag is latched, see Section 7.11 for indication on how the failure flags can be
released.
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STGAP1S
6.2
Logic supply management
High voltage section voltage regulator
The device integrates in the high voltage section a linear voltage regulator that generates
the 3.3 V logic core supply voltage from an external supply voltage connected to the VH pin.
Figure 4. High voltage section 3.3 V voltage regulator
VH
VH
100 nF
LDO
Reg
VREGISO
4.7 µF
100 nF
If the voltage at the VREGISO pin goes below the minimum operating threshold which
causes the logic reset, the REG_ERR bit in the STATUS1 register is set high.
6.3
Power-up, power-down and “safe state”
The following conditions define the device's “safe state”:
GOFF = ON state
GON = high impedance
CLAMP = ON state (if CLAMP < 'GNDISO + VCLAMPth')
DESAT = GNDISO (internal switch on and current generator off)
Such conditions are guaranteed at power-up of the isolated side (also for VH < VHon
and VL > VLon) and during the whole device power-down phase (also for VH < VHoff
and VL > VLoff), whatever the value of the input pins.
The device integrates a structure which clamps the driver output to a voltage smaller than
SafeClp when the VH voltage is not high enough to actively turn the Goff N-channel
MOSFET on.
If the VH positive supply pin is floating the GOFF pin is clamped to a voltage smaller than
SafeClp.
After power-up of the isolated side the REGERRR status flag is latched and the device is
forced in “safe state”. See Section 7.11 on page 35 for indication on how the failure flags
can be released.
After power-up of the low voltage side the REGERRL and UVLOD status flags are latched
and the device is forced in “safe state”. See Section 7.11 for indication on how the failure
flags can be released.
The UVLOH flag is also forced high at the power-up of the low voltage side, but its value is
set to zero as soon as the isolated side power-up is completed.
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Logic supply management
6.4
STGAP1S
Standby function
The device can be put in standby mode to reduce the power consumption on VDD via the
SPI command “Sleep” (refer to Section 9.1.5 on page 49).
The proper sequence is:
1.
Pull-down the SD pin: the driver section will be put in “safe state”
2.
Send a Sleep command
3.
After a tsleep time the device can be considered actually in the sleep mode.
To exit from the sleep mode it is necessary to set SD high for at least tawake while keeping
IN+ low.
After a tawake time the device can accept new commands and the REGERRR bit is set to
indicate that the device needs to be reprogrammed.
If the SD pin is raised while tsleep is still not expired, the device returns to the operation
mode within a tawake time.
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STGAP1S
Functional description
7
Functional description
7.1
Inputs and outputs
The device is controlled through following logic inputs:
SD: active low shutdown input
IN+: driver input
CS: active low chip select (SPI)
SDI: serial data input (SPI)
CK: serial clock (SPI)
And following logic outputs:
SDO: serial logic output (SPI)
DIAG1: diagnostic signal (open drain)
And following IO pin:
IN-/DIAG2: driver input or diagnostic open drain output.
Logic input thresholds and output ranges vary according to VDD voltage. In particular, the
device is designed to work with VDD supply voltages of 5 V or 3.3 V.
The operation of the driver IOs can be programmed through DIAG_EN bits as described in
Table 10.
Table 10. Inputs true table (device NOT in “safe state”)
Bit in CFG1 register
Input pins
Output pins
DIAG_EN
SD
IN+
IN-
GON
GOFF
X
0
X
X
OFF
ON
0
1
0
0
OFF
ON
0
1
0
1
OFF
ON
0
1
1
0
ON
OFF
0
1
1
1
OFF
ON
1
1
0
X(1)
OFF
ON
1
X(1)
ON
OFF
1
1
1. The IN-/DIAG2 pin is used as the open drain output for diagnostic signaling (refer to Section 7.11 on page
35).
A deglitch filter is applied to device inputs (SD, IN+, IN-). Each input pulse, positive and
negative, shorter than the programmed tdeglitch value is neglected by internal logic.
Deglitch time can be programmed as listed in Table 29 on page 52.
When the deglitch filter is disabled (INfilter = '00') and the 2-level turn-off function is disabled
(2LTOtime = 0x0) or enabled only after a fault event (2LTO_EN = '0'), a minimum input pulse
tINmin is required to change the device output status. The minimum input pulse timing filters
out both positive and negative pulses at IN+, IN- and SD pins.
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Functional description
7.2
STGAP1S
Deadtime and interlocking
When single gate drivers are used in half-bridge configuration, they usually do not allow
preventing cross conduction in case of wrong input signals coming from the controller
device. This limitation is due to the fact that each driver does not have the possibility to
know the status of the input signal of the other companion driver in the same leg. Thanks to
the availability of two input pins with opposite polarity the STGAP1S allows implementing an
hardware interlocking that prevents cross conduction even in case of wrong input signals
generated by the control unit. This functionality can be achieved by implementing the
connection shown in Figure 5 and by configuring the IN-/DIAG2 pin as input (which is its
default configuration).
Figure 5. HW cross conduction prevention in half-bridge configuration with two
single gate drivers
IN+
IN-
μC
gapDRIVE HS
HIN
LIN
IN+
IN-
gapDRIVE LS
When such configuration is used, it is also possible to enable the STGAP1S programmable
deadtime feature, which guarantees that at least a DT time passes between the turn-off of
one driver's output and the turn-on of the other driver. The deadtime value DT can be
programmed through the SPI interface as shown in Table 28 on page 51.
If the deadtime feature is enabled, a counter is started when the input status changes from <
IN- = '1' and IN+ = '0' > to a different combination, which means that the other driver in the
same leg is at the beginning of a turn-off (refer to Figure 6).
Once the counter is started it keeps counting regardless of any input variation until a DT
time has passed, and during this time the driver prevents the turn-on of its output even if the
controller tries to force the turn-on (inputs set to < IN- = '0' and IN+ = '1' >).
Once the programmed DT counter is expired, the driver immediately turns the output on as
soon as a turn-on command is present at the input pins, and no extra delay is added
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STGAP1S
Functional description
Figure 6. Transitions causing the DT generation
IN- = 1
IN+ = 0
IN- = 0
paired
Driver ON
IN- = 0
IN+ = 1
ALL OFF IN+ = 0
IN- = 1
IN+ = 1
this
Driver ON
ALL OFF
Transitions causing the DT generation
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Functional description
STGAP1S
Some examples of the device behavior when the deadtime feature is enabled are shown
from Figure 7 to Figure 10.
Figure 7. Synchronous control signal edges
INSYNCHRONOUS
CONTROL SIGNALS EDGES;
DEAD TIME
IN+
GON-GOFF
DT
DT
Figure 8. Control edges signal overlapped, example 1
INCONTROL SIGNALS EDGES
OVERLAPPED;
DEAD TIME
IN+
GATE
DT
DT
DT
Figure 9. Control edges signal overlapped, example 2
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
ININ+
GON-GOFF
DT
DT
Figure 10. Control edges signal not overlapped and outside DT (direct control)
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
ININ+
GON-GOFF
DT
DT
When the deadtime function is enabled the STGAP1S reports a “deadtime violation” fault in
case the control unit tries to turn on any of the drivers in one leg during the counting of the
programmed DT time. If such event occurs the DT_ERR flag is set high and latched.
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STGAP1S
7.3
Functional description
Hardware RESET
The device can be reset by forcing the VREG pin to ground through an external switch.
The internal regulator is designed to stand this condition.
The maximum current required to force the VREG pin to ground is indicated by the
parameter IREG.
7.4
Power supply UVLO and OVLO
Undervoltage protection is available on both VH and VL supply pins.
The turn-on threshold can be programmed through the SPI writing the CFG4 register.
A fixed 1 V hysteresis will set the respective turn-off threshold.
Both UVLO protections can be independently disabled by setting the proper value in the
CFG4 register.
When VH voltage goes below the VHoff threshold the output buffer goes in “safe state” and
the UVLOH status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low
(default), the UVLOH status flag is released when VH voltage reaches the VHon threshold
and the device returns to normal operation.
Otherwise the UVLOH flag is latched and the device remains in “safe state” until the VH
voltage reaches the VHon threshold and the flag is released. See Section 7.11 on page 35
for indication on how the failure flags can be released.
When VL voltage goes over the VLoff threshold the output buffer goes in “safe state” and the
UVLOL status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low
(default), the UVLOL status flag is released when VL voltage goes below the VLon threshold
and the device returns to normal operation.
Otherwise the UVLOL flag is latched and the device remains in “safe state” until the VL
voltage goes below the VLon threshold and the flag is released. See Section 7.11 for
indication on how the failure flags can be released.
Overvoltage protection is available on both VH and VL supply pins. Both OVLO protections
can be disabled by setting the proper value in the CFG4 register.
When the VH voltage goes over the OVVHoff threshold the output buffer goes in “safe state”
and the OVLOH status flag is forced high. The OVLOH flag is latched and the device
remains in “safe state” until VH voltage goes below the overvoltage threshold and the flag is
released. See Section 7.11 for indication on how the failure flags can be released.
When VL voltage goes over the OVVLoff threshold the output buffer goes in “safe state” and
the OVLOL status flag is forced high. The OVLOL flag is latched and the device remains in
“safe state” until VH voltage goes below the overvoltage threshold and the flag is released.
See Section 7.11 for indication on how the failure flags can be released.
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Functional description
7.5
STGAP1S
Thermal warning and shutdown protection
The device provides a thermal warning and a thermal shutdown protection.
When junction temperature reaches the TWN temperature threshold the TWN flag in the
STATUS1 register is forced high. The TWN flag is released as soon as the junction
temperature is lower than TWN - Thys.
When junction temperature reaches the TSD temperature threshold, the device is forced in
“safe state” and the TSD flag in the STATUS1 register is forced high. The device operation is
restored and the TSD flag is released as soon as the junction temperature is lower than
TSD - Thys.
7.6
Desaturation protection
This feature allows implementing an overload protection for the IGBT. The DESAT pin
monitors the VCE voltage of the IGBT while it is on, and if the protection threshold is
reached, the IGBT is turned off.
When the IGBT is off (GOFF output is activated) the DESAT pin is kept low internally and
the external blanking capacitor connected to the DESAT pin is discharged (the internal
current generator is fully switched off and the switch between DESAT and GNDISO pins is
turned on).
When the GON output is activated the switch between DESAT and GNDISO pins is turned
off and an internal programmable current generator (IDESAT) starts charging the external
blanking capacitor after a fixed blanking time tBLK.
If a desaturation event occurs the VCE voltage increases and the voltage at the DESAT pin
reaches the desaturation threshold VDESATth: the DESAT comparator output is set, the
device is forced in “safe state” and the DESAT flag is forced high and latched.
The DESAT comparator is not active when the external IGBT is off or after desaturation
detection (see Figure 11).
Both the VDESATth threshold and the IDESAT blanking current are programmable through the
SPI.
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STGAP1S
Functional description
Figure 11. DESAT protection timing diagram
IN+
Comparator Disabled
Comparator Enabled
Comparator Disabled
tDESAT
VH level
GON-GOFF
VL level
V
DESATth
DESAT
Blanking time
tBLK
tDIAGx
DiagX
A deglitch filter is applied to the DESAT pin. Each pulse exceeding the VDESATth for a time
shorter than tDESfilter value shall not trigger the protection.
7.7
VCE active clamping protection
This protection is used to actively clamp the drain/collector overvoltage spikes during the
MOSFET/IGBT turn-off. This feature allows using low turn-off resistor values leading lower
turn-off losses, thus increasing efficiency, while limiting the maximum turn-off spike on the
collector (or drain) within safe limits.
The direct feedback of the collector voltage to the device can for example be made via an
element with avalanche characteristics such as a TVS. If the VCE voltage exceeds the
breakdown voltage of the TVS, the VVCECLth threshold voltage on the VCECLAMP is
reached and the IC actively slows down the power switch turn-off to keep a safe condition.
The active limiting of the driver's turn-off current strongly reduces the current flowing
through the TVS, thus preventing it from operating in overstressing conditions.
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Functional description
STGAP1S
Figure 12. Example of VCE active clamping protection connection
VCECLAMP
VH
VL
VL
VL
GON
Floating
Section
Control
Logic
GOFF
Level
Shifter
CLAMP
VL
GNDISO
+
CLAMPth
When the VCECLAMP is activated during the turn-off phase a watchdog timer starts inside
the driver. This timer allows the VCECLAMP pin to act on the driver's output status for
a tVCECLoff time maximum. After that time has expired, the driver continues the normal turnoff ignoring the VCECLAMP pin status. This assures that the protection is only acting to
clamp inductive VCE spikes during the turn-off.
The timer is reset and the VCECLAMP protection is enabled again at the beginning of the
following turn-off sequence.
Figure 13. VCECLAMP timing diagram
GON\GOFF
VCECLAMP
VCEcounter
stopped
ready
counting
stopped
ready
tVCECLoff
The VCECLAMP pin is masked and has no effect on the driver's outputs status when the
external MOSFET/IGBT is on.
The VCE active clamping protection can be disabled connecting the VCECLAMP pin to VL.
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STGAP1S
7.8
Functional description
SENSE overcurrent protection
This function is suitable in applications in which it is possible to measure the load current
through the use of a shunt resistor, or in applications that use IGBTs with the current sense
pin available. The load current (or a fraction of it in case SenseFETs are used) is converted
to voltage by an external shunt resistor and is fed to the SENSE pin (comparator input).
When an overcurrent event occurs the sense voltage reaches the VSENSEth threshold, the
device is forced in “safe state” and the SENSE status flag is forced high and latched.
The VSENSEth threshold is programmable through the SPI (refer to Section 9.2.2 on page
52).
7.9
Miller clamp function
The Miller clamp function allows the control of the Miller current during the power stage
switching in half-bridge configurations. When the external power transistor is in the OFF
state, the driver operates to avoid the induced turn-on phenomenon that may occur when
the other switch in the same leg is being turned on, due to the Cgc capacitance.
During the turn-off period the gate of the external switch is monitored through the CLAMP
pin.
The CLAMP switch is activated when gate voltage goes below the voltage threshold
VCLAMPth, thus creating a low impedance path between the switch gate and the VL pin.
This function can be disabled setting low the CLAMP_EN bit in the CFG5 register (high by
default).
7.10
2-level turn-off function
If an overcurrent event happens, a large voltage overshoot exceeding VCE absolute ratings
may occur across the power switch during the turn-off, due to the parasitic stray
inductances.
The 2-level turn-off function (2LTO) allows the reduction of the stressing overvoltage
experienced by the power component in overcurrent condition by switching off the external
power in two phases.
In the first phase the GOFF voltage is actively forced to a programmable value V2LTOth; after
a programmable delay t2LTOtime the GOFF is forced to VL to complete the gate turn-off.
This allows to slow down the critical part of the turn-off transient, that may induce the
overvoltage spikes.
The voltage level V2LTOth and duration t2LTOtime of the intermediate off-level are
programmable through the SPI.
It is possible to program when this feature takes place, refer to the following paragraphs.
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Functional description
7.10.1
STGAP1S
Always
The 2LTO is performed at each turn-off transition (2LTO_EN = '1').
When 2LTO is used at each transition the minimum on or off pulse width is determined by
2LTO time. Some sample waveforms are given in Figure 14 and Figure 15, where INAND
represents the condition: < IN+ = 'H' and IN- = 'L' >.
If a turn-on pulse is shorter than t2LTOtime it shall be ignored; turn-on pulses longer than
t2LTOtime will determine a delay in the turn-on equal to t2LTOtime (see Figure 14).
Figure 14. Example of short turn-on pulses when 2LTO occurs at each cycle
ONtime
ONtime
IN AND
tDoff
tDoff
ONtime
t2LTOtime
t2LTOtime
t2LTOtime
ON-time < t2LTOtime
t2LTOtime
t2LTOtime
GON-GOFF
ON-time < t2LTOtime
ONtime
t2LTOtime
tDon
tDon
ON-time > t2LTOtime
ON-time > t2LTOtime
When a turn-off pulse is detected the turn-off procedure starts immediately by forcing the
V2LTOth voltage on the GOFF pin. If the duration of the turn-off pulse is shorter than t2LTOtime
the turn-off sequence is aborted by setting GOFF in high impedance and turning GON on
again (see Figure 15).
Figure 15. Example of short turn-off pulse when 2LTO occurs at each cycle
IN AND
tDoff
GON-GOFF
t2LTOtime
OFF-time > t2LTOtime
tDoff
tDon
t2LTOtime
OFF-time < t2LTOtime
tDoff
t2LTOtime
OFF-time > t2LTOtime
When the 2LTO is used at each cycle, any event that forces the device to enter in “safe
state” generates a driver switch off performing a 2LTO sequence.
7.10.2
Fault
The 2LTO is performed only after a desaturation or overcurrent event (2LTO_EN = '0'). In
such cases the device enters in “safe state” until the failure flag is released. See
Section 7.11 for indication on how the failure flags can be released.
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STGAP1S
Functional description
This configuration overrides some drawbacks of using the 2LTO at each turn-off, such as
the minimum pulse width equal to t2LTOtime and the turn-on delay needed to avoid duty cycle
distortion.
With this configuration the turn-off is only slowed down in case of desaturation or
overcurrent events.
Figure 16. Example of operation with 2LTO in “Fault” mode
IN AND
VDESATth
DESAT
GON-GOFF
tDoff
tDoff
7.10.3
tDon
tDon
tDESAT
t2LTOtime
Never
The 2LTO function is disabled (2LTOtime = 0x0). In this case a standard turn-off sequence is
used (directly lowering the gate voltage from VH to VL) also in case of desaturation or sense
overcurrent events.
7.11
Failure management
The device provides advanced diagnostic through open drain outputs (DIAG1/DIAG2) and
internal status registers. The DIAG2 output shares the same pin of the IN- input (see
Figure 1 on page 8); the diagnostic signal through the pin is enabled through the DIAG_EN
pin as described in Section 7.1 on page 25.
Status registers (STATUS1, STATUS2 and STATUS3) provide failures and status
information as listed in respective paragraphs.
DIAG1 and DIAG2 pins can be programmed through the dedicated registers (DIAG1 and
DIAG2) to signal one or more failure conditions. The output value is the result of the NOR of
the selected status bits: if one of the selected bits is high, the output is forced low.
Some of the failure conditions reported by the status registers are latched, i.e.: the flag is
kept high even if the triggering condition is expired. In this case the failure flag can be
released in following ways:
Using the ResetStatus command (all flags are released)
Forcing low the SD pin for at least trelease when the SD_FLAG configuration bit is set
high. All the flags are released at the SD rising edge.
Using HW reset (see Section 7.3 on page 29). In this case the device behaves as after
power-up sequence.
In any case, if the failure condition is still present, the respective flag is not released.
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Functional description
STGAP1S
Selected failures force the device in “safe state”; the device remains in this state until the
relative status flags are released. Refer to Table 48 on page 58, Table 50 on page 59 and
Table 52 on page 60 for details.
The possibility to clear status registers by setting the SD low allows operating the device
also without using the SPI interface. In order to avoid an unintended clear of fault conditions
it is recommended to disable this functionality by setting the SD_FLAG = '0'.
7.12
Asynchronous stop command
The ASC pin allows to turn-on the GON output acting directly on the isolated driver logic and
regardless of the status of the input pins IN+, IN- and SD. This pin is active high.
The status of this pin is mirrored in the ASC bit present in the STATUS2 register.
The power supply of the isolated section must be present (VH > VHon).
In case UVLO on VH is not enabled, ASC function works for VH values within the
recommended operating values.
This function works even if the VDD voltage is not available or is in UVLO condition.
The priority of such command is lower than that of DESAT and SENSE pins, so the ASC
command is ignored in case of a desaturation or overcurrent fault. After such events the
gate can be turned on again with a low-to-high transition of the ASC pin, or by clearing the
fault condition (see Section 7.11).
7.13
Watchdog
The isolated side provides a watchdog function in order to identify when it is no more able to
communicate with the LV side. In this case the driver is automatically forced in “safe state”
and the REGERRR flag is set.
When the LV side is in the standby mode, turned off or in hardware reset condition, the
isolated side watchdog is still operative and the REGERRR flag is set.
The low voltage side provides a watchdog function in order to identify when it is no more
able to communicate with the isolated side. In this case the REGERRL flag is set and the
device is forced in “safe state”.
7.14
Security check functions
The device allows verifying the gate and sense resistor connections and the functionality of
SENSE and DESAT. This can be achieved through the following security checks:
GON to gate path
GOFF to gate path
SENSE comparator
SENSE resistor
DESAT comparator
The check modes are enabled through a dedicated configuration register TEST1 (refer to
Section 9.2.9 on page 60) and thus require entering in configuration mode.
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STGAP1S
Functional description
Only one check mode at a time must be enabled. At the end of security check procedure,
the TEST1 register must be set to 0x00 before running the device in normal mode.
It is recommended to clear the status register with the ResetStatus command before and
after each check.
To prevent SD from clearing the STATUS flags, set SD_FLAG = '0' as described in
Section 7.11.
7.14.1
GON to gate path check
The purpose of this security check is to verify the path integrity including the driver's GON
output, the GON (turn-on) gate resistor, the power switch gate and the CLAMP pin (see
Figure 17).
To perform this test, the following procedure has to be followed:
Set SD = low
Send StartConfig command
Set GONCHK = '1'
Send StopConfig command
Wait tGchk
Read TSD flag
–
TSD = '0' → OK (VCLAMP > VGchk)
–
TSD = '1' → FAIL (VCLAMP < VGchk)
Please note that during all the time the check is enabled the gate will be forced high (GON
turned on) regardless the SD pin level. The user test routine has to take into account this
behavior.
In any case, when GONCHK = '1', the protections SENSE and DESAT, if enabled, will
continue to operate protecting the power switch regardless the SD pin.
7.14.2
GOFF to gate path check
The purpose of this security check is to verify the path integrity including the driver's GOFF
output, the GOFF (turn-off) gate resistor, the power switch gate and the CLAMP pin (see
Figure 17).
To perform this test, the following procedure has to be followed:
Set SD = low
Send StartConfig command
Set GOFFCHK = '1'
Send StopConfig command
Wait tGchk + tGATE_GOFFchk
Read DESAT flag
–
DESAT = '0' → OK (VCLAMP < VCLAMPth)
–
DESAT = '1' → FAIL (VCLAMP > VCLAMPth)
During the check a small current IGOFFchk will be sourced from the CLAMP pin while GOFF
is on keeping the gate low through the turn-off gate resistor.
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Functional description
STGAP1S
To ensure the check result, some applicative conditions have to be verified:
–
The bleeding resistor, sometimes present between the gate and source in the
power switch, shall be lower than 8.2 k.
–
During the test, the power switch gate shall have the time to be charged up to
VCLAMPth by IGOFFchk. In case no bleeding resistor is present, this time can be
roughly computed as:
tGATE_GOFFchk ≈ CGATE * (VCLAMPth - VL) / IGOFFchk
If a bleeding resistor is present or an additional push-pull circuit has been added,
the time has to be computed with the adequate corrective factors.
If the check fails due to the lack of the GOFF resistor, the power switch gate will gradually
rise up to VH with no protections of SENSE nor DESAT. The user test routine shall consider
this behavior.
Figure 17. Gate paths check circuitry
SD
VH
Control
Logic
I
S
O
L
A
T
I
O
N
GON
Floating
Section
Control
Logic
CLAMP
VL
+
VCLAMPth
CS
CK
SDI
SDO
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GOFF
Level
Shifter
VH
testcontrol
IGOFFchk
SPI
Floating ground
DocID027190 Rev 3
GNDISO
STGAP1S
7.14.3
Functional description
SENSE comparator check
The purpose of this security check is to verify the functionality of the sense comparator.
To enable this check, it is required to set SNSCHK = '1' and SENSE_EN = '1'.
When this check is enabled the switch in series to the SENSE pin is open (see Figure 18);
a SENSE fault (STATUS1 register) should be reported within tSENSEchk, otherwise the
SENSE comparator operation is compromised.
VSENSEcomp > VSENSEth → comparator OK → SENSE = '1'
VSENSEcomp < VSENSEth → comparator FAIL → SENSE = '0'
The SENSE fault generated by this test is latched and shall be cleared accordingly.
Figure 18. SENSE comparator and resistor check circuitry
VH
GON
SD
Control
Logic
I
S
O
L
A
T
I
O
N
Floating
Section
Control
Logic
CLAMP
VL
VH
ISENSERchk
testcontrol
+
SDI
SDO
SENSE
SENSEcomp
testcontrol
VSENSEth
CS
CK
GOFF
Level
Shifter
RSENSE
Rtest
SPI
Floating ground
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Functional description
7.14.4
STGAP1S
SENSE resistor check
The purpose of this security check is to verify the connection between the device and the
sense shunt resistor and to verify the optional sense resistor filter network is not open.
To perform this test, the following procedure has to be followed:
Set SD = low
Send StartConfig command
Set SENSE_EN = '1'
Set GOFFCHK = '1'
Send StopConfig command
Wait tRchk + tSENSERchk
Read SENSE flag
–
SENSE = '0' → OK (VSENSE < VSENSEth)
–
SENSE = '1' → FAIL (VSENSE > VSENSEth)
During the check a small current ISENSERchk is sourced from the SENSE pin (see
Figure 18). If the sense resistor is not present or floating, SENSE pin voltage will rise and
once VSENSEth is exceeded, a SENSE fault will be reported in the STATUS1 register within
tRchk.
To ensure the check result, the following condition has to be verified:
–
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The SENSE flag read has to be delayed of tSENSERchk, which is the time the
customer filtering network and/or the power switch gate takes to reach VSENSEth
by the ISENSERchk current.
DocID027190 Rev 3
STGAP1S
7.14.5
Functional description
DESAT comparator check
The purpose of this security check is to verify the functionality of the desaturation
comparator.
To perform this test, the following procedure has to be followed:
Set SD = low
Send StartConfig command
Set DESAT_EN = '1'
Set DESCHK = '1'
Send StopConfig command
Set SD = high
Wait 3 µs
Apply at the inputs a gate turn on pulse longer than 500 ns
Read DESAT flag
–
DESAT = '1' → OK (VDESATcomp > VDESATth)
–
DESAT = '0' → FAIL (VDESATcomp < VDESATth)
During this test GON is first turned on and then turned off as soon the test succeeds. In case
the test should fail, the output remains on as long as the input signal remains high.
At the end of the check the DESAT fault remains set (it is latched), and it has to be cleared.
Figure 19. DESAT comparator check circuitry
VH
SD
testcontrol
IDESAT
IN+
IN-
Control
Logic
CS
CK
SDI
SDO
I
S
O
L
A
T
I
O
N
+
DESAT
1k
testcontrol
Cblank
VDESATth
VH
GON
Floating
Section
Control
Logic
GOFF
Level
Shifter
CLAMP
VL
SPI
Floating ground
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Functional description
7.15
STGAP1S
Register corruption protection
All the configuration registers are protected against content corruption.
If the value of a local register is changed without a proper command is received (WriteReg,
ResetStatus or GlobalReset), the REGERRL flag is set low and the device is forced in “safe
state”.
If the value of a remote register is changed without a proper command is received
(WriteReg or GlobalReset), the REGERRR flag is set low and the device is forced in “safe
state”.
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STGAP1S
8
SPI interface
SPI interface
The IC communicates with an external MCU through a 16-bit SPI. This interface is used to
set the device parameters and for advanced diagnostic.
The SPI I/O pins are:
CS: chip select (active low)
CK: serial clock
SDI: serial data input (MOSI)
SDO: serial data output (MISO).
The interface is compliant with the SPI standard CPHA = 1 and CPOL = 0 (serial data is
sampled on CK falling edge and it is updated on CK rising edge, at CS falling edge the CK
signal must be low) as shown in Figure 20.
Figure 20. SPI timings
SD
(Not required for
NOP and read
operations)
tSDLCSL
tCSHSDH
CS
tdesCS
tsetCS
tfCK
tlCK trCK thCK
CK
tenSDO
tsetSDI
tholCS
tholSDI
N-1
MSB
SDI
HiZ
MSB
LSB
tvSDO
tholSDO
SDO
N-2
tdisSDO
N-1
N-2
LSB
MSB
The SPI interface can work up to 5 Mbps and provides the daisy chain feature.
In order to guarantee a safe operation and robustness to electrical noise, the number of
rising edges within a CS negative pulse must be multiple of 16, otherwise the
communication cycle is ignored and a communication failure is indicated forcing high the
SPI_ERR flag.
Any number of the STGAP1S can be connected in daisy chain, and only 4 lines for the SPI
and one for the SD are required in order to guarantee access to status and configuration
registers of each device. An example of daisy chain configuration is shown in Figure 21.
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SPI interface
STGAP1S
Figure 21. SPI daisy chain connection example
Device 2
Device 1
SD
SD
I
S
O
L
A
T
I
O
N
CS
CK
SDI
SDO
CS
CK
SDI
SDO
Device N
SD
I
S
O
L
A
T
I
O
N
I
S
O
L
A
T
I
O
N
CS
CK
SDI
SDO
SD
MOSI
μC
CS
CK
MISO
In case a bootstrap capacitor and a diode are used to generate the VH supply voltage for
the high-side drivers, it is recommended to have one dedicated SD line for all of the highside drivers and another dedicated SD line for all of the low-side drivers. An example of
such topology is shown in Figure 22.
Figure 22. SPI daisy chain connection example when bootstrap technique is used for high-side
drivers
VH_HS2
VH_HS1
VH
VH
SD
CS
CK
SDI
SDO
SD
SD_HS
MOSI
μC
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CS
CS
CK
MISO
SD_LS
CK
SDI
SDO
I
S
O
L
A
T
I
O
N
I
S
O
L
A
T
I
O
N
SD
Cboot_HS1
CS
CK
VL
GNDISO
SDI
SDO
I
S
O
L
A
T
I
O
N
Cboot_HS2
VL
GNDISO
VH_LS
VH_LS
VH
VH
SD
CS
CK
VL
GNDISO GNDiso
DocID027190 Rev 3
SDI
SDO
I
S
O
L
A
T
I
O
N
VL
GNDISO GNDiso
STGAP1S
SPI interface
CRC protection
All the command and data bytes have to be followed by a CRC code. If the CRC_SPI bit is
set high, this code is used to check the data byte is correct, otherwise the CRC byte is
ignored. In this case the CRC byte must be transmitted by the host, but its value is
unimportant.
A failure on the CRC check causes the respective data byte is ignored and the SPI_ERR
flag is set high.
The polynomial generator of the CRC code is X8 + X2 + X + 1 corresponding to the block
diagram in Figure 23.
Figure 23. Block diagram of the CRC generator
Message
(from MSb to LSb)
X7
X6
X5
X4
X3
X2
X1
X0
The host must transmit to the device the inverted CRC code computed using the following
procedure:
Initialize CRC to all 1
Start the calculation from the most significant bit of the message
Invert the CRC result
In case of a WriteReg command, the CRC of the data byte (i.e.: the new register value) must
be calculated initializing the computation system to the CRC of the command byte (i.e.: the
CRC is calculated on a 16-bit message composed by the command + data byte). This way
a data byte cannot be accepted as a command byte and vice-versa. Some examples are
listed in Table 11.
The device always transmits a response byte followed by a CRC computed using the same
polynomial generator (X8 + X2 + X + 1). The CRC byte transmitted by the device is not
inverted.
If no response is required, the word returned by the device has no meaning and it should be
discarded. Some examples are listed in Table 12.
Table 11. CRC byte examples (from host to device)
Command
Command byte
Command CRC
Data byte
Data CRC
StopConfig
0x3A
0xAA
N.A.
N.A.
WriteReg(CFG1, 0x20)
0x8C
0xA1
0x20
0x82
WriteReg(CFG5, 0x06)
0x99
0xCA
0x06
0x66
ResetStatus
0xD0
0x32
N.A.
N.A.
ReadReg(CFG3)
0xBE
0x3F
N.A.
N.A.
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SPI interface
STGAP1S
Table 12. CRC byte examples (from device to host)
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Data byte
Data CRC
0x00
0xF3
0xEA
0x6B
0xF5
0x36
0x2A
0x25
DocID027190 Rev 3
STGAP1S
Programming manual
9
Programming manual
9.1
SPI commands
The commands summary is given in Table 13.
Table 13. SPI commands
Command mnemonic
Command value
Action
Notes
StartConfig
0
0
1
0 1 0
1
0
Device configuration start
Enter CFG mode
SD low only
StopConfig
0
0
1
1 1 0
1
0
Device configuration/check
completed
Leave CFG mode
SD low only
NOP
0
0
0
0 0 0
0
0
No operation
WriteReg
1
0
0
A A A A
A
Write AAAAA register
ReadReg
1
0
1
A A A A
A
Read AAAAA register
ResetStatus
1
1
0
1 0 0
0
0
Reset all the status registers
SD low only
GlobalReset
1
1
1
0 1 0
1
0
Global reset
CFG mode only
Sleep
1
1
1
1 0 1
0
1
Device enters in standby mode
SD low only
9.1.1
CFG mode only
StartConfig and StopConfig commands
Table 14. StartConfig command synopsis
Byte
1
2
To device
0010 1010
1101 1010(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
Table 15. StopConfig command synopsis
Byte
1
2
To device
0011 1010
1010 1010(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
To configure the device it must be switched to the configuration mode.
To switch the device to the configuration mode the StartConfig command must be sent. This
command is accepted when the SD line is low only. If the command has been correctly
received and interpreted, the IC registers writing is enabled.
The SD pin must be kept low during the configuration. If the SD pin is raised during the
configuration procedure the device immediately quits the configuration mode causing a fault
error indicated by the REGERRL and REGERRR bits. In this case all the changes operated
on device configuration are undone and the previous configuration is restored.
At the end of the device setup the StopConfig command has to be sent in order to quit the
configuration mode and make all changes effective.
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Programming manual
9.1.2
STGAP1S
WriteReg command
Table 16. WriteReg command synopsis
Byte
1
2
3
4
To device
100A AAAA(1)
CCCC CCCC(2)
DDDD DDDD(3)
KKKK KKKK(4)
1. The command byte where AAAAA is the address of the target register.
2. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
3. Data to be written into the target register.
4. The CRC byte of the command and data, if the CRC check is disabled this byte is ignored.
The device register can be written through the WriteReg command when the device is set in
the configuration mode only (refer to Section 9.1.1), otherwise the write command is ignored
and the SPI_ERR flag is forced low.
The WriteReg command is followed by the data to be written into the target register. The
CRC code following the data is based on both command and data bytes. In this way, in case
of communication error, a data byte cannot be decoded as a command and vice-versa (refer
to Section : CRC protection on page 45).
9.1.3
ReadReg command
Table 17. ReadReg command synopsis
Byte
1
2
3(1)
4
To device
101A AAAA(2)
CCCC CCCC(3)
0000 0000
CCCC CCCC(4)
From device
0000 0000
0000 0000
DDDD DDDD(5)
KKKK KKKK(6)
1. Proper time have to be waited in order to allow the device to prepare the data.
2. The command byte where AAAAA is the address of the target register.
3. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
4. The CRC byte of the NOP command.
5. Data read from the target register.
6. The CRC byte of the data.
The registers of the device can be read anytime through the ReadReg command. After the
command is received and decoded by the device, the register value and the respective CRC
code is prepared for the transmission. The CRC polynomial used by the device during the
transmission is different from the one used by the host, but the CRC code is not inverted
before transmission (refer to Section : CRC protection).
The time required to obtain the reading result changes according to the side where the
register is located. The reading of a local register (low voltage side) is available in 800 ns.
The reading of a remote register (isolated side), if no communication error occurs between
the two sides of the device, is available in 30 µs.
After the read result is ready, the host microcontroller must send another command in order
to receive it. The time required to make the read result available depends on the register
type: remote registers need longer time because of the isolated interface communication.
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STGAP1S
9.1.4
Programming manual
ResetStatus and GlobalReset commands
Table 18. ResetStatus command synopsis
Byte
1
2
To device
1101 0000
0011 0010(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
The ResetStatus command is a specific reset command which acts on all status registers
releasing all the latched flags. The command is executed only when the SD input is low,
otherwise the SPI_ERR flag is forced low.
Table 19. GlobalReset command synopsis
Byte
1
2
To device
1110 1010
1001 0100(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
The GlobalReset command reset all the registers to the default and releases all the failure
flag (if latched). It can be sent when the device is in the configuration mode only, otherwise
the command is ignored and the SPI_ERR flag is forced low.
9.1.5
Sleep command
Table 20. Sleep command synopsis
Byte
1
2
To device
1111 0101
1100 1001(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
The command forces the device to switch in standby mode within a tsleep period. The
command is executed only when the SD pin in low, if the SD pin is high the command is
ignored and the SPI_ERR flag is forced low.
Refer to Section 6.4 on page 24 for the description of the standby mode.
9.1.6
NOP command
Table 21. NOP command synopsis
Byte
1
2
To device
0000 0000
0000 1100(1)
1. The CRC byte of the command, if the CRC check is disabled this byte is ignored.
The command does not modify the device status and does not generate any answer.
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Programming manual
9.2
STGAP1S
Registers and flags description
All device features can be configured through a set of 8-bit long registers.
There are three different types of registers:
Local registers are located on the low voltage side
Remote registers are located on the isolated side
Shared registers are located both on the low voltage and isolated side and the value of
the two copies is kept synchronized.
A map of the user registers is shown in Table 22.
Table 22. Registers map
Name
Add- Side
ress (1)
Structure
[7]
CFG1
0x0C
L
CFG2
0x1D
R
CFG3
0x1E
R
CFG4
0x1F
R
CFG5
0x19
R
STATUS1 0x02
L
STATUS2 0x01
L
STATUS3 0x0A
L
[6]
[5]
[4]
[3]
[1]
[0]
DTset
CRC_SPI UVLOD_EN SD_FLAG DIAG_EN
SENSEth
[2]
INfilter
DESATcur
DESATth
2LTOth
2LTOtime
OVLO_EN UVLOlatch
VLONth
VHONth
2LTO_EN CLAMP_EN DESAT_EN SENSE_EN
OVLOH
OVLOL
DESAT
SENSE
DT_ERR
UVLOH
SPI_ERR
GOFFCHK GONCHK
UVLOL
TSD
TWN
REGERRR
ASC
GATE
REGERRL
OVLOD
UVLOD
DESCHK
SNSCHK
RCHK
TEST1
0x11
R
DIAG1
0x05
L
DIAG1_7
DIAG1_6
DIAG1_5
DIAG1_4
DIAG1_3
DIAG1_2
DIAG1_1
DIAG1_0
DIAG2
0x06
L
DIAG2_7
DIAG2_6
DIAG2_5
DIAG2_4
DIAG2_3
DIAG2_2
DIAG2_1
DIAG2_0
1. R: remote (isolated side), L: local (low voltage side).
9.2.1
CFG1 register (low voltage side)
The CFG1 register has the structure of Table 23.
Table 23. CFG1 register
Default/reset
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Bit 7
Bit 6
Bit 5
Bit 4
CRC_SPI
UVLOD_EN
SD_FLAG
DIAG_EN
DTset
INfilter
0
0
1
0
00
00
DocID027190 Rev 3
Bit 3
Bit 2
Bit 1
Bit 0
STGAP1S
Programming manual
The CRC_SPI bit enables the CRC check on the SPI communication protocol.
Table 24. CRC enable
CRC_SPI
SPI communication protocol CRC enable
0
Disabled
1
Enabled
The UVLOD_EN bit enables the UVLO protection on VDD supply voltage.
Table 25. VDD supply voltage UVLO enable
UVLOD_EN
Supply voltage UVLOD enable
0
Disabled
1
Enabled
The SD_FLAG bit sets the SD pin functionality according to Table 26. When the reset of the
failure flags through the SD pin is enabled, keeping low the SD pin for at least trelease
causes all the latched flags of the status registers to be released at next SD rising edge.
Table 26. SD pin FAULT management
SD_FLAG
SD pin functionality
0
SD pin do not reset STATUS registers
1
SD pin reset STATUS registers
The DIAG_EN bit sets if the IN-/DIAG2 pin works as the input or open drain output
according to Table 27. Refer to Section 7.1 on page 25 for details.
Table 27. IN-/DIAG2 pin functionality
DIAG_EN
IN-/DIAG2 pin functionality
0
The IN-/DIAG2 pin work as input
1
The IN-/DIAG2 pin work as open drain output
The DTset bits set the deadtime value.
Table 28. Deadtime
DTset [1 ... 0]
Deadtime value [ns]
0
0
Disabled
0
1
250
1
0
800
1
1
1200
The INfilter bits set the input deglitch time tdeglitch for SD, IN- and IN+ pins.
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Table 29. Input deglitch time
INfilter [1 ... 0]
9.2.2
Input deglitch time value [ns]
0
0
Disabled
0
1
210
1
0
560
1
1
70
CFG2 register (isolated side)
The CFG2 register has the structure of Table 30.
.
Table 30. CFG2 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SENSEth
DESATcur
DESATth
000
00
100
Default/reset
Bit 0
The SENSEth bits set the SENSE comparator threshold according to Table 31. Refer to
Section 7.8 on page 33 for details.
Table 31. SENSE threshold
SENSEth [2 ... 0]
SENSE threshold value [mV]
0
0
0
100
0
0
1
125
0
1
0
150
0
1
1
175
1
0
0
200
1
0
1
250
1
1
0
300
1
1
1
400
The DESATcurr parameter sets the current sourced by the DESAT pin according to Table 32
and the DESATth parameter sets the DESAT comparator threshold according to Table 33.
Refer to Section 7.6 on page 30 for details.
Table 32. DESAT current
DESATcur [1 ... 0]
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DESAT current value [µA]
0
0
250
0
1
500
1
0
750
1
1
1000
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Table 33. DESAT threshold
DESATth [2 ... 0]
9.2.3
DESAT threshold value [V]
0
0
0
3
0
0
1
4
0
1
0
5
0
1
1
6
1
0
0
7
1
0
1
8
1
1
0
9
1
1
1
10
CFG3 register (isolated side)
The CFG3 register has the structure of Table 34.
Table 34. CFG3 register
Bit 7
Default/reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
2LTOth
2LTOtime
0000
0000
Bit 0
The 2LTOth parameter sets the voltage value which is actively forced during the 2-level turnoff sequence (refer to Section 7.10 on page 33 for details).
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Table 35. 2LTOth
2LTOth [3 ... 0]
2LTO threshold value [V]
0
0
0
0
7.00
0
0
0
1
7.50
0
0
1
0
8.00
0
0
1
1
8.50
0
1
0
0
9.00
0
1
0
1
9.50
0
1
1
0
10.00
0
1
1
1
10.50
1
0
0
0
11.00
1
0
0
1
11.50
1
0
1
0
12.00
1
0
1
1
12.50
1
1
0
0
13.00
1
1
0
1
13.50
1
1
1
0
14.00
1
1
1
1
14.50
The 2LTOtime parameter sets the duration of the 2-level turn-off sequence (refer to
Section 7.10 on page 33 for details). If the 2LTOtime is set to zero, the 2-level turn-off
feature is disabled.
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Table 36. 2-level turn-off time value
2LTOtime [3 ... 0]
9.2.4
2-level turn-off time value [µs]
0
0
0
0
Disabled
0
0
0
1
0.75
0
0
1
0
1.00
0
0
1
1
1.50
0
1
0
0
2.00
0
1
0
1
2.50
0
1
1
0
3.00
0
1
1
1
3.50
1
0
0
0
3.75
1
0
0
1
4.00
1
0
1
0
4.25
1
0
1
1
4.50
1
1
0
0
4.75
1
1
0
1
5.00
1
1
1
0
5.25
1
1
1
1
5.50
CFG4 register (isolated side)
The CFG4 register has the structure of Table 37.
Table 37. CFG4 register
Bit 7
Default/reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OVLO_EN
UVLOlatch
VLONth
VHONth
0
0
00
00
The OVLO_EN bit enables the OVLO protection on the VH and VL power supply according
to Table 38.
Table 38. VH and VL supply voltages OVLO enable
OVLO_EN
OVLO supply voltage enable
0
Disabled
1
Enabled
The UVLOlatch bit sets if the UVLO is latched or not (refer to Section 7.4 on page 29 for
details).
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Table 39. UVLO protection management
UVLOlatch
UVLO protection management
0
UVLO protection is not latched
1
UVLO protection is latched
The VLONth bits set the UVLO threshold on the negative power supply according to
Table 40.
Setting the parameter to zero disables the UVLO protection of the VL supply.
Table 40. VL negative supply voltage UVLO threshold
VLONth [1 ... 0]
Negative supply voltage UVLO threshold [V]
0
0
Disabled
0
1
-3
1
0
-5
1
1
-7
The VHONth bits set the UVLO threshold on the positive power supply according to
Table 41.
Setting the parameter to zero disables the UVLO protection of the VH supply.
Table 41. VH positive supply voltage UVLO threshold
VHONth [1 ... 0]
9.2.5
Positive supply voltage UVLO threshold [V]
0
0
Disabled
0
1
10
1
0
12
1
1
14
CFG5 register (isolated side)
The CFG4 register has the structure of Table 42.
Table 42. CFG5 register
Bit 7
Default/reset
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Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2LTO_EN
CLAMP_EN
DESAT_EN
SENSE_EN
0
1
1
0
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Programming manual
The 2LTO_EN bit sets when the feature takes place according to Table 43. Refer to
Section 7.10 on page 33 for details.
Table 43. 2LTO mode
2LTO_EN
2LTO mode
0
2LTO always active
1
2LTO active only after a fault event
The 2LTOth bit sets the 2-level turn-off threshold according to Table 35 on page 54 and the
2-level turn-off time according to Table 36.
The SENSE_EN bit sets if the sense overcurrent function is enabled or not (refer to
Section 7.8 on page 33 for details).
Table 44. SENSE comparator enabling
SENSE_EN
SENSE comparator status
0
SENSE comparator disabled
1
SENSE comparator enabled
The DESAT_EN bit sets if the desaturation protection is enabled or not (refer to Section 7.6
on page 30 for details).
Table 45. DESAT comparator enabling
DESAT_EN
DESAT comparator status
0
DESAT comparator disabled
1
DESAT comparator enabled
Set the CLAMP_EN bit to enable the Miller clamp feature (refer to Section 7.9 on page 33
for details).
Table 46. Miller clamp feature enabling
CLAMP_EN
Miller clamp feature status
0
Miller clamp feature disabled
1
Miller clamp feature enabled
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9.2.6
STGAP1S
STATUS1 register (low voltage side)
The STATUS1 is a read only register that reports some device failure flags.
All flags are active high (the high value indicates a failure condition). The STATUS1 register
has the structure of Table 47.
Table 47. STATUS1 register
Default
(1)
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OVLOH
OVLOL
DESAT
SENSE
UVLOH
UVLOL
TSD
TWN
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1. Default value of the local copy of the register. The value will be updated according to the actual information from the
isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no
failures).
A description of the STATUS1 register bits is provided in Table 48.
Table 48. STATUS1 register description
Name
Bit
Fault
Latched
Force
“safe state”
OVLOH
7
VH overvoltage flag.
It is forced high when VH is over
OVVHoff threshold.
Always
Yes
OVLOL
6
VL overvoltage flag.
It is forced high when VH is over
OVVLoff threshold.
Always
Yes
DESAT
5
Desaturation flag.
It is forced high when DESAT pin
voltage reach VDESATth threshold.
Always
Yes
SENSE
4
Sense flag.
It is forced high when SENSE pin
voltage reach VSENSEth threshold.
Always
Yes
UVLOH
3
VH undervoltage flag.
It is forced high when VH is below
VHoff threshold.
When
UVLOlatch is
high only
Yes
If not latched (UVLOlatch low)
returns high when VH is over
VHon threshold.
UVLOL
2
VL undervoltage flag.
When
It is forced high when VL is over VLoff UVLOlatch is
threshold.
high only
Yes
If not latched (UVLOlatch low)
returns high when VL is below
VLon threshold.
1
Thermal shutdown protection flag.
It is forced high when
overtemperature shutdown threshold
is reached.
No
(hysteresis)
Yes
0
Thermal warning flag.
It is forced high when
overtemperature shutdown threshold
is reached.
No
(hysteresis)
No
TSD
TWN
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9.2.7
Programming manual
STATUS2 register (low voltage side)
The STATUS2 is a read only register. The STATUS2 register has the structure of Table 49.
Table 49. STATUS2 register
Bit 7
Default
(1)
Reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REGERRR
ASC
GATE
x
x
x
x
x
1
0
0
x
x
x
x
x
0
0
0
1. Default value of the local copy of the register. The value will be updated according to the actual information from the
isolated side. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no
failures).
A description of the STATUS2 register bits is provided in Table 50.
Table 50. STATUS2 register description
Name
Force
“safe state”
Note
Always
Yes
This flag is
released when
a programming
procedure is
correctly
performed also.
ASC pin status.
When ASC pin is high the flag reports '1', otherwise
is '0'.
No
No
See details in
Section 7.12 on
page 36
Gate status flag.
When GON is active the flag is '1', when GOFF is
active it is '0'.
No
No
Bit
Fault
REGERRR
2
Register or communication error on isolated side.
It is forced high when:
– Programming procedure is not correctly
performed.
– Isolated interface communication fails.
– An unexpected register value change occurs in
one of the remote registers.
It is also latched at power-up/reset and from Sleep
state.
ASC
1
GATE
0
9.2.8
Latched
STATUS3 register (low voltage side)
The STATUS3 is a read only register. The STATUS3 register has the structure of Table 51.
Table 51. STATUS3 register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT_ERR
SPI_ERR
REGERRL
OVLOD
UVLOD
Default(1)
x
x
x
0
0
1
0
1
Reset
x
x
x
0
0
0
0
0
1. The default is forced at the device power-up, when the registers are reset all the flags are forced low (no failures).
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A description of the STATUS2 register bits is provided in Table 52.
Table 52. STATUS3 register description
Latched
Force
“safe state”
Note
Deadtime error flag.
This bit is forced high when a violation of
internal DT is detected.
Always
No
See details in Section 7.2
on page 26
3
SPI communication error flag.
It is forced high when the SPI
communication fails cause:
– Wrong CRC check.
– Wrong number of CK rising edges.
– Attempt to execute a not-allowed
command.
Attempt to read, write or reset at a notavailable address.
Always
No
REGERRL
2
Register or communication error on low
voltage side.
It is forced high when: – Programming procedure is not correctly
performed.
– Isolated interface communication fails.
– An unexpected register value change
occurs in one of the remote registers.
It is latched at power-up/reset also.
Always
Yes
OVLOD
1
VDD overvoltage flag.
It is forced high when VDD is over
OVVDDoff threshold.
Always
Yes
0
VDD undervoltage flag.
It is forced high when VDD is below VDDon
threshold. It is latched at power-up/reset
also.
Always
Yes
Name
Bit
DT_ERR
4
SPI_ERR
UVLOD
9.2.9
Fault
This flag is released
when a programming
procedure is correctly
performed also.
TEST1 register (isolated side)
The TEST1 register has the structure of Table 53.
Table 53. TEST1 register
Bit 7
Default/reset
x
Bit 6
x
Bit 5
x
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GOFFCHK
GONCHK
DESCHK
SNSCHK
RCHK
0
0
0
0
0
Setting an one check bit of the register enables the respective check mode.
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Table 54. Check mode
9.2.10
Bit
Check mode
RCHK
SENSE resistor
SNSCHK
SENSE comparator
DESCHK
DESAT comparator
GONCHK
GON to gate path
GOFFCHK
GOFF to gate path
DIAG1 and DIAG2 registers (low voltage side)
The DIAG1 register has the structure of Table 55.
Table 55. DIAG1 register
Default/reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIAG1_7
DIAG1_6
DIAG1_5
DIAG1_4
DIAG1_3
DIAG1_2
DIAG1_1
DIAG1_0
1
1
0
1
1
0
1
0
The DIAG2 register has the structure of Table 56.
Table 56. DIAG2 register
Default/reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIAG2_7
DIAG2_6
DIAG2_5
DIAG2_4
DIAG2_3
DIAG2_2
DIAG2_1
DIAG2_0
0
0
0
0
0
0
0
0
If a bit in the DIAG1 register is high, the corresponding fault events turn on the open drain
connected to the DIAG1 pin forcing the output low.
If a bit in the DIAG2 register is high and the DIAG_EN bit is high, the corresponding fault
events turn on the open drain connected to the DIAG2 pin forcing the output low.
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The relation between the DIAG1 and DIAG2 register bits and failure events is described in
Table 57.
Table 57. Relation between DIAG1/2 bits and failure conditions
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DIAG1/2 bit
Failure
Status registers bit
0
Thermal warning
TWN
1
Thermal shutdown
TSD
2
ASC feedback
ASC, DT_ERR
3
Desaturation and sense detection
DESAT, SENSE
4
Overvoltage failure
OVLOH, OVLOL
5
Undervoltage failure
UVLOH, UVLOL
6
VDD power supply failure
UVLOD, OVLOD
7
SPI communication error or register failure
SPI_ERR, REGERRL, REGERRR
DocID027190 Rev 3
P5V
μC
DocID027190 Rev 3
P5V
P5V
P5V
P5V
VDD
SDI
SDO
CK
CS
GND
GND
SD
IN+
IN-/DIAG2
DIAG1
VREG
P5V
SDI
SDO
CK
CS
GND
GND
SD
IN+
IN-/DIAG2
DIAG1
SPI
Control
Logic
3V3
Voltage Reg
SPI
Control
Logic
3V3
Voltage Reg
I
S
O
L
A
T
I
O
N
I
S
O
L
A
T
I
O
N
UVLO
VL
Floating
Section
Control
Logic
UVLO
VL
Floating
Section
Control
Logic
Floating ground
UVLO
VH
Floating ground
UVLO
VH
Level
Shifter
Level
Shifter
+
+
+
+
+
+
+
+
SENSEth
CLAMPth
2LVTOth
DESATth
DESATcurr
SENSEth
CLAMPth
2LVTOth
DESATth
DESATcurr
SENSE
GNDISO
VL
CLAMP
GOFF
GON
VH
VREGISO
DESAT
SENSE
GNDISO
VL
CLAMP
GOFF
GON
VH
VREGISO
DESAT
VL_LS
1k
VL_HS
1k
GND_LS
VH_LS
GND_HS
VH_HS
GND_PWR
Load_Phase
HV_BUS
10
VREG
VDD
P5V
STGAP1S
Typical application diagram
Typical application diagram
Figure 24. Typical application diagram in half-bridge configuration
Refer to Figure 12 on page 32 in the dedicated Section 7.7 on page 31 for the connection of
the VCECLAMP pin.
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Package information
11
STGAP1S
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
SO24W package information
Figure 25. SO24W package outline
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Package information
Table 58. SO24W package mechanical data
Dimensions (mm)
Symbol
Notes
Min.
Typ.
Max.
A
2.35
2.65
A1
0.10
0.30
B
0.33
0.51
C
0.23
0.32
D
15.20
15.60
E
7.40
7.60
e
(1)
1.27
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
K
0
8
ddd
Degrees
0.10
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
Figure 26. SO24W suggested land pattern
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Ordering information
12
STGAP1S
Ordering information
Table 59. Device summary
13
Order code
Package
Packing
STGAP1S
SO24W
Tube
STGAP1STR
SO24W
Tape and reel
Revision history
Table 60. Document revision history
Date
Revision
19-Nov-2014
1
Initial release.
2
Updated Figure 2 on page 9, Figure 3 on page 22, and
Figure 20 on page 43 (replaced by new figures).
Updated Table 2 on page 11, Table 4 on page 12,
Table 6 on page 14 (added SPI parameters), Table 7 on
page 21, and Table 13 on page 47 (updated SPI
commands list).
Minor modifications throughout document.
3
AEC-Q100 automotive grade qualified:
– Updated Section : Features on page 1 (added
“Qualified for automotive applications according to
AEC-Q100”).
– Updated Section : Applications on page 1 (added
“Inverters for EV\HEV and EV charging stations”).
– Updated Section : Description on page 1 (added
“motor drivers in hybrid and electric vehicles”).
21-May-2015
27-May-2015
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Changes
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STGAP1S
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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