STGAP2DMTR

STGAP2D Datasheet Galvanically isolated 4 A half-bridge gate driver Features SO-16 Product status link STGAP2D • • • • • • • • • • • • 1700 V dual channel gate driver Driver current capability: 4 A sink / source at 25 °C dV/dt transient immunity ±100 V/ns Overall input-output propagation delay: 75 ns UVLO function Configurable interlocking function Dedicated SD and BRAKE pins Gate driving voltage up to 26 V 3.3 V, 5 V TTL/CMOS inputs with hysteresis Temperature shutdown protection Standby function UL 1577 recognized Applications Product label • • • • • • • • • Motor driver for industrial drives, factory automation, home appliances and fans 600/1200 V inverters Battery chargers Induction heating Welding UPS Power supply units DC-DC converters Power Factor Correction Description The STGAP2D is a half-bridge gate driver which isolates the gate driving channels from the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for high power inverter applications such as motor drivers in industrial applications. The device integrates protection functions: dedicated SD and BRAKE pins are available, UVLO and thermal shutdown are included to easily design high reliability systems, and an interlocking function prevents outputs from being high at the same time. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption. DS12746 - Rev 3 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com STGAP2D Block diagram 1 Block diagram Figure 1. Block diagram VH_A VDD UVLO VH INA Floating Section Control Logic Level Shifter GOUT_ A INB Control Logic SD BRAKE VDD I S O L A T I O N GNDISO_ A Floating rgoundA VH_B UVLO VH Floating Section Control Logic Level Shifter GOUT_B iLOCK GND GNDISO_B Floating ground B DS12746 - Rev 3 page 2/22 STGAP2D Pin description and connection diagram 2 Pin description and connection diagram Figure 2. Pin connection (top view) VDD 1 16 GNDISO_A INA 2 15 GOUT_A INB 3 14 VH_A SD 4 13 N.C. BRAKE 5 12 N.C. iLOCK 6 11 GNDISO_B GND 7 10 GOUT_B N.C. 8 9 VH_B Table 1. Pin description DS12746 - Rev 3 Pin # Pin name Type Function 1 VDD Power supply 2 INA Logic input Control logic input for Channel A, active high. 3 INB Logic input Control logic input for Channel B, active high. 4 SD Logic input Shutdown input, active low. 5 BRAKE Logic input Control logic input, active low. 6 iLOCK Analog input Interlocking enable/disable. 7 GND Power supply Control logic ground. 9 VH_B Power supply Channel B gate driving positive supply. 10 GOUT_B Analog output Channel B Sink/Source output. 11 GNDISO_B Power supply Channel B gate driving isolated ground. 14 VH_A Power supply Channel A gate driving positive supply. 15 GOUT_A Analog output Channel A Sink/Source output. 16 GNDISO_A Power supply Channel A gate driving isolated ground. Others - - Control logic supply voltage. Not connected. page 3/22 STGAP2D Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings 3.2 Symbol Parameter Test condition VDD Logic supply voltage vs. GND VLOGIC Logic pins voltage vs. GND iLOCK Interlocking enable vs. GND VH_x Positive supply voltage (VH_x vs. GNDISO_x) VOUT Voltage on gate driver outputs (GOUT_x vs. GNDISO_x) VISO-OP Input to output isolation voltage (GND vs. GNDISO_x) TJ Junction temperature TS Storage temperature PDin Power Dissipation input chip PDout Power Dissipation output chip ESD HBM- (human body model) Min. Max. Unit - -0.3 6.5 V - -0.3 6.5 V -0.3 VDD + 0.3 V - -0.3 28 V - -0.3 VH_x + 0.3 V -1700 +1700 V - -40 150 °C - -50 150 °C TA = 25 °C - 40 mW TA = 25 °C - 1.16 W DC or peak - 2 kV Thermal data Table 3. Thermal data Symbol Rth(JA) 3.3 Parameter Package Value Unit SO-16 90 °C/W Thermal resistance junction to ambient Recommended operating conditions Table 4. Recommended operating conditions Symbol Test conditions Min. Max. Unit Logic supply voltage vs. GND - 3.1 5.5 V VLOGIC Logic pins voltage vs. GND - 0 5.5 V iLOCK Interlocking enable vs. GND 0 VDD V VH_x Positive supply voltage (VH_x vs. GNDISO-x) - - 26 V DC or peak -1500 +1500 V VDD GNDISOA-B (1) Parameter Floating grounds differential voltage (GNDISO_A - GNDISO_B) FSW Maximum switching frequency(2) - - 1 MHz tOUT Pulse width - 100 - ns Operating Junction Temperature - -40 125 °C TJ 1. Characterization data, 1200 V max. tested in production. 2. Actual limit depends on power dissipation and TJ DS12746 - Rev 3 page 4/22 STGAP2D Electrical characteristics 4 Electrical characteristics Table 5. Electrical characteristics (TJ = 25 °C, VH_x = 15 V, VDD = 5 V unless otherwise specified) Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics tDon INA, INB, SD, BRAKE Input to output propagation delay ON See Figure 8 50 75 90 ns tDoff INA, INB, SD, BRAKE Input to output propagation delay OFF See Figure 8 50 75 90 ns tr - Rise time 30 - ns - Fall time CL = 4.7 nF, See Figure 8 - tf - 30 - ns - - - 20 ns - - 20 40 ns 100 - - V/ns PWD - tdeglitch INA, INB, SD, BRAKE CMTI(2) - Pulse width distortion(1) Inputs deglitch filter Common-mode transient immunity, | dVISO/dt| VCM = 1500 V, see Figure 9 Supply voltage VHon - VH_x UVLO turn-on threshold - 8.6 9.1 9.6 V VHoff - VH_x UVLO turn-off threshold - 7.9 8.4 8.9 V VHhyst - VH_x UVLO hysteresis - 0.6 0.75 0.95 V - VH_x undervoltage quiescent supply current VH_x = 7 V - 1.3 1.8 mA - VH_x quiescent supply current - - 1.3 1.8 mA - Standby VH_x quiescent supply current - - 400 550 µA SafeClp - GOUT active clamp - 2 2.3 V IQDD - VDD quiescent supply current - - 1.8 2.4 mA IQDDSBY - Stand-by VDD quiescent supply current Standby mode - 40 80 µA IQHU_A, IQHU_B IQH_A, IQH_B IQHSBY_A, IQHSBY_B IGOUT = 0.2 A; VH floating Logic inputs Vil INA, INB, SD, BRAKE Low-level logic threshold voltage - 0.29·VDD 0.33·VDD 0.37·VDD V Vih INA, INB, SD, BRAKE High-level logic threshold voltage - 0.62·VDD 0.66·VDD 0.7·VDD V Ilogic_h INA, INB, SD, BRAKE Logic inputs high-level input bias current Vlogic = 5 V 33 50 70 µA Ilogic_l INA, INB, SD, BRAKE Logic inputs low-level input bias current Vlogic = 0 V - - 1 µA Rpd INA, INB, SD, BRAKE Logic inputs pull-down resistor - 70 100 150 kΩ Interlocking DS12746 - Rev 3 iLOCKen iLOCK Interlocking enable voltage 0.7·VDD V iLOCK_l iLOCK iLOCK low-level bias current iLOCK = GND iLOCK_h iLOCK iLOCK high-level bias current iLOCK = VDD iLOCK_pu iLOCK iLOCK pull-up resistor 35 66 V 55 90 75 μA 1 μA 142 kΩ page 5/22 STGAP2D Electrical characteristics Symbol Pin Parameter Test conditions Min. Typ. Max. TJ = 25 °C - 4 - TJ = -40 to +125 °C (2) 3 - 5 TJ = 25 °C - 4 - TJ = -40 to +125 °C (2) 3 - 5.5 Unit Driver buffer section IGON GOUT Source short-circuit current IGOFF GOUT Sink short-circuit current VGONH GOUT GON output high-level voltage IGON = 100 mA VH - 0.15 VH - 0.125 - V VGOFFL GOUT GOFF output low-level voltage IGOFF = 100 mA - 110 120 mV RGON GOUT Source RDS_ON IGON = 100 mA - 1.25 1.5 Ω GOUT Sink RDS_ON IGOFF = 100 mA - 1.1 1.2 Ω RGOFF A A Overtemperature protection TSD Shutdown temperature - 170 - - °C Thys Temperature hysteresis - - 20 - °C 200 280 500 µs 10 20 35 µs 90 140 200 µs 200 280 800 ns Standby tSTBY - Standby time tWUP - Wake-up time tawake - Wake-up delay tstbyfilt - Standby filter See Section 5.6 1. PWD = max (|tDon(A) - tDon(B)|, |tDoff(A) - tDoff(B)|, |tDoff(A) - tDon(B)|, |tDoff(B) - tDon(A)|). 2. Characterization data, not tested in production. Table 6. Isolation related specifications Parameter Clearance (Minimum External Air Gap ) Creepage (*) (Minimum External Tracking) Comparative Tracking Index (Tracking Resistance) Isolation Group DS12746 - Rev 3 Symbol Value Unit CLR 4 mm Measured from input terminals to output terminals, shortest distance through air CPG 4 mm Measured from input terminals to output terminals, shortest distance path along body CTI ≥ 400 V II Conditions DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) page 6/22 STGAP2D Electrical characteristics Table 7. Isolation characteristics Parameter Symbol Test Conditions Characteristic Unit 2720 VPEAK 3200 VPEAK 4800 VPEAK Method a, Type test VPR = 2720, tm = 10 s Input to Output test voltage In accordance with VDE 0884-11 VPR Partial discharge < 5 pC Method b1, 100% Production test VPR = 3200, tm = 1 s Partial discharge < 5 pC Transient Overvoltage (Highest Allowable Overvoltage) Maximum Surge Test Voltage Isolation Resistance VIOTM tini = 60 s Type test VIOSM Type test 4800 VPEAK RIO VIO = 500 V, Type test >109 Ω Table 8. UL 1577 isolation voltage ratings Description Isolation Withstand Voltage, 1 min (Type test) Isolation Test Voltage, 1 sec (100% production) Symbol Characteristic Unit VISO 2828/4000 Vrms/ PEAK VISOtest 3394/4800 Vrms/ PEAK Recognized under the UL 1577 Component Recognition Program - file number E362869 DS12746 - Rev 3 page 7/22 STGAP2D Functional description 5 Functional description 5.1 Gate driving power supply and UVLO The STGAP2D is a flexible and compact gate driver with 4 A output current and rail-to-rail outputs. The device allows implementing either unipolar or bipolar gate driving. Figure 3. Power supply configuration for unipolar and bipolar gate driving Unipolar gate driving VDD Bipolar gate driving VDD VDD 1uF VDD 1uF 100nF VH_x INx GND I S O L A T I O N 100nF VH_x + 100nF 1uF VH GOUT_x GNDISO_x INx GND I S O L A T I O N 100nF + 1uF VH 1uF VL GOUT_x + GNDISO_x Undervoltage protection is available on VH_x supply pin. A fixed hysteresis sets the turn-off threshold, thus avoiding intermittent operation. When VH_x voltage goes below the VHoff threshold, the output buffer enters 'safe state'. When VH_x voltage reaches the VHon threshold, the device returns to normal operation and sets the output according to actual input pins status. The VDD and VH_x supply pins must be properly filtered with local bypass capacitors. The use of capacitors with different values in parallel provides both local storage for impulsive current supply and high-frequency filtering. We recommend using low-ESR SMT ceramic capacitors for the best filtering performance. A 100 nF ceramic capacitor must be placed as close as possible to each supply pin, and a second bypass capacitor with value between 1 μF and 10 μF should be placed close to it. 5.2 Power-up, power-down and safe state The following conditions define the safe state: • • GOUT n-channel = ON state GOUT p-channel = high impedance Such conditions are maintained at power-up of the isolated side (VH_x < VHon) and during whole device powerdown phase (VH < VHoff), regardless of the value of the input pins. The device integrates a structure that clamps the driver output to a voltage not higher than SafeClp when VH voltage is not high enough to actively turn the internal GOUT n-channel on. If VH_x positive supply pin is floating or not supplied, the GOUT pin is therefore clamped to a voltage smaller than SafeClp. If the supply voltage VDD of the control section of the device is not supplied, the output is put in safe state and remains in this condition until the VDD voltage returns to operative conditions. After power-up of both isolated and low voltage side, the device output state depends on the status of the input pins. DS12746 - Rev 3 page 8/22 STGAP2D Control Inputs 5.3 Control Inputs The device is controlled through the following logic inputs: • • • • SD: active low shutdown input; BRAKE: active low brake input; INA, INB: active high logic inputs for channel A and channel B driver outputs; iLOCK: used to enable or disable the interlocking protection The operation of the driver IOs is described in Table 9. Table 9. Inputs truth table (applicable when device is not in UVLO or "safe state") Input pins(1) iLOCK Interlocking SD Output pins BRAKE INA INB GOUT_A GOUT_B X L X X X Low Low X H L X X Low HIGH X H H L L Low Low X H H H L HIGH Low X H H L H Low HIGH VDD H H H H Low Low GND H H H H HIGH HIGH 1. X: Don’t care. A deglitch filter allows input signals with duration shorter than tdeglitch to be ignored, thereby preventing any noise spikes in the application from generating unwanted commutations. 5.4 Watchdog The isolated HV side has a watchdog function to identify when it is not able to communicate with the LV side; for example, because the VDD of the LV side is not supplied. In this case, the output of the driver is forced into 'safe state' until the communication link is properly established again. 5.5 Thermal shutdown protection The device provides a thermal shutdown protection. When junction temperature reaches the TSD temperature threshold, the device is forced into 'safe state'. Device operation is restored as soon as the junction temperature falls below TSD - Thys. 5.6 Standby function The device can be put in standby mode to reduce the power consumption of both the control interface and gate driving sides. In standby mode, the quiescent current from VDD and VH_x supply pins is reduced to IQDDS and IQHS_x, respectively, and the output remains in ‘safe state’ (the output is actively forced low). To enter standby, keep the SD low while keeping the other input pins (INA, INB and BRAKE) high ('standby' value) for a time longer than tSTBY. During standby, the inputs can change from the 'standby' value. To exit standby, inputs must be put in any combination different from the 'standby' value for a time longer than tstbyfilt , and then in the “standby” value for a time t such that tWUP< t < tSTBY. When the input configuration is changed from the 'standby' value, the output is enabled and set according to inputs state after a time tawake. DS12746 - Rev 3 page 9/22 STGAP2D Interlocking function Figure 4. Standby state sequences Sequence to enter stand-by mode “stand-by”: t = tSTBY t < tSTBY duration too short INA, INB, SD, BRAKE { INA = INB = BRAKE = HIGH SD = LOW is any different combination “stand-by” “stand-by” Device status ACTIVE STAND-BY Output ACTIVE SAFE-STATE Sequence to exit stand-by mode t = tSTBY INA, INB, SD, BRAKE 5.7 “stand-by” t > tstbyfilt t < tWUP t > tSTBY duration too short duration too long “stand-by” “stand-by” tWUP < t < tSTBY t = tawake “stand-by” Device status ACTIVE STAND-BY ACTIVE Output ACTIVE SAFE-STATE ACTIVE Interlocking function The interlocking function prevents outputs GOUT_A and GOUT_B from being high at the same time, regardless of the status of the input pins INA and INB. In half-bridge topologies this protection avoids shoot-through in case that wrong input signals are generated by the controller device. In case the status of INA and INB is such to require both channels to be ON at the same time, the driver turns both channels off. In some topologies it is required to allow both channels to be ON at the same time: this can be achieved by disabling the interlocking function trough the iLOCK pin. The iLOCK pin shall be either connected to VDD, which enables the interlocking function, or to GND, which disables the interlocking function and allows parallel operation of Channel_A and Channel_B. Refer to Section 5.3 for complete logic inputs truth table. DS12746 - Rev 3 page 10/22 STGAP2D Typical application diagrams 6 Typical application diagrams Figure 5. Half-bridge configuration HV_BUS VDD 1uF 100nF VDD 100nF HIN UVLO VH INA Rfilt Cfilt LIN MCU VH_HS VH_A VDD Floating Section Control Logic Level Shifter 1uF GOUT_A INB Rfilt Cfilt SD Control Logic SD Rfilt Cfilt BRAKE BRAKE I S O L A T I O N GNDISO_A Floating rgoundA Floating Section Control Logic Level Shifter Load_Phase VH_LS 100nF UVLO VH VDD VDD or GND GND_HS VH_B 1uF GOUT_B iLOCK GNDISO_B GND Floating rgound B GND_LS GND_PWR Figure 6. Half-bridge configuration with negative gate driving HV_BUS VDD VH_A VDD 1uF 100nF VDD 1uF 100nF HIN UVLO VH INA Rfilt Cfilt LIN MCU VH_HS Floating Section Control Logic Level Shifter GOUT_A INB Rfilt Cfilt SD Control Logic SD Rfilt Cfilt BRAKE BRAKE VDD VDD or GND iLOCK I S O L A T I O N GNDISO_A Floating rgoundA 1uF GND_HS VH_B Load_Phase VH_LS 100nF UVLO VH Floating Section Control Logic Level Shifter 1uF GOUT_B 1uF GNDISO_B GND Floating rgound B GND_LS GND_PWR DS12746 - Rev 3 page 11/22 STGAP2D Layout 7 Layout 7.1 Layout guidelines and considerations In order to optimize the PCB layout, the following considerations should be taken into account: • SMD ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to each supply rail pin. A 100 nF capacitor must be placed between VDD and GND and between VH_x and GNDISO_x, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF should also be placed close to the supply pins. – • • • 7.2 As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (INA, INB, BRAKE, SD), in particular for fast switching or noisy applications. The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop area and inductance that might bring about noise or ringing. To avoid degradation of the isolation between the primary and secondary side of the driver, there should not be any trace or conductive area below the driver. If the system has multiple layers, it is recommended to connect the VH_x and GNDISO_x pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity. Layout example An example of STGAP2D suggested half-bridge with negative gate driving PCB layout is shown in Figure 7; the main signals have been highlighted by different colors. It is recommended to follow this example for proper positioning and connection of filtering capacitors. Figure 7. Suggested PCB layout for half-bridge configuration with negative driving voltage GHS CG SHS RON GLS ROFF RBOOT CG CVH_B RON CVH_A DHS DBOOT CVDD CIN CIN CIN CIN CVH_A RIN RIN RPU RIN RPU CVH_B RIN CVH_A DOFF CVDD DOFF ROFF DLS CVH_B SLS DS12746 - Rev 3 page 12/22 STGAP2D Testing and characterization information 8 Testing and characterization information Figure 8. Timings definition INA 50% 50% INB 50% 50% tr tf 90% GOUT_A 90% 10% 10% t Doff t Don tr tf 90% GOUT_B 90% 10% 10% t Doff t Don Figure 9. CMTI test circuit VDD + VDD + S1 VH_x INx - I S O L A T I O N GND + GOUT_x Output Vout moni toring node VH GNDISO_x G1 DS12746 - Rev 3 page 13/22 STGAP2D Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 SO-16 narrow package information Table 10. SO-16 narrow package dimensions Dim. mm NOTES Min. Typ. Max. A 1.35 - 1.75 A1 0.10 - 0.25 (1) - b 0.35 - 0.49 c 0.19 - 0.25 (2) D 9.80 - 10.00 E 5.80 - 6.20 - 4.00 (2) E1 3.80 e 1.27BSC - L 0.40 - 1.25 - h 0.25 - 0.50 - ϴ 0 - 7 degrees 1. Dimension "b" and "E1" does not include dam bar protrusion (allowable dam bar protrusion shall be 0.127 mm total). 2. Dimension "D" and "E1" do not include mold protrusions (maximum 0.15 mm per side). DS12746 - Rev 3 page 14/22 STGAP2D SO-16 narrow package information Figure 10. SO-16 package outline DS12746 - Rev 3 page 15/22 STGAP2D Suggested land pattern 10 Suggested land pattern Figure 11. SO-16 suggested land pattern 3.21 1.27 0.55 4.1 6.6 DS12746 - Rev 3 page 16/22 STGAP2D Ordering information 11 Ordering information Table 11. Device summary DS12746 - Rev 3 Order code Output configuration Package Package marking Packaging STGAP2DM GOUT SO-16 GAP2DM Tube STGAP2DMTR GOUT SO-16 GAP2DM Tape and Reel page 17/22 STGAP2D Revision history Table 12. Document revision history Date Version 24-Aug-2018 1 Changes Initial release. Added iLOCK pin for interlocking function disable. 26-Jan-2022 2 Added Table 6, Table 7, and Table 8. Updated Table 2, Table 4, and Table 5. Updated Figure 3. 25-Jul-2022 DS12746 - Rev 3 3 Updated Table 2, added UL file certification page 18/22 STGAP2D Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Gate driving power supply and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Power-up, power-down and safe state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.5 Thermal shutdown protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.6 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.7 Interlocking function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical application diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 7 Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 7.1 Layout guidelines and considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Testing and characterization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 9.1 SO-16 narrow package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10 Suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 DS12746 - Rev 3 page 19/22 STGAP2D List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics (TJ = 25 °C, VH_x = 15 V, VDD = 5 V unless otherwise specified) Isolation related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isolation characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UL 1577 isolation voltage ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs truth table (applicable when device is not in UVLO or "safe state") . . . . . . . . . . . . SO-16 narrow package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12746 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 4 . 4 . 5 . 6 . 7 . 7 . 9 14 17 18 page 20/22 STGAP2D List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. DS12746 - Rev 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power supply configuration for unipolar and bipolar gate driving . . . . . . . . . . . . Standby state sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Half-bridge configuration with negative gate driving . . . . . . . . . . . . . . . . . . . . . Suggested PCB layout for half-bridge configuration with negative driving voltage Timings definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMTI test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-16 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 8 10 11 11 12 13 13 15 16 page 21/22 STGAP2D IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS12746 - Rev 3 page 22/22