SiHS90N65E
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Vishay Siliconix
E Series Power MOSFET
FEATURES
• Low figure-of-merit (FOM) Ron x Qg
• Low input capacitance (Ciss)
D
SUPER-247
• Reduced switching and conduction losses
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
S
G
D
G
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
S
• Server and telecom power supplies
N-Channel MOSFET
• Switch mode power supplies (SMPS)
• Power factor correction power supplies (PFC)
PRODUCT SUMMARY
• Lighting
VDS (V) at TJ max.
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
700
RDS(on) (Ω) typ. at 25 °C
VGS = 10 V
0.025
Qg (nC) max.
591
Qgs (nC)
84
Qgd (nC)
160
Configuration
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
Single
ORDERING INFORMATION
Package
Super-247
Lead (Pb)-free
SiHS90N65E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
650
Gate-source voltage
VGS
± 30
Continuous drain current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
UNIT
V
87
55
A
IDM
323
5
W/°C
Single pulse avalanche energy b
EAS
1930
mJ
Maximum power dissipation
PD
625
W
TJ, Tstg
-55 to +150
°C
Linear derating factor
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dV/dt
TJ = 125 °C
d
Soldering recommendations (peak temperature) c
for 10 s
dV/dt
41
4.1
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 11.7 A
c. 1.6 mm from case
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91585
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SiHS90N65E
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
0.2
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate threshold voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.83
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
VGS = ± 30 V
VDS = 650 V, VGS = 0 V
-
-
± 100
±1
1
nA
μA
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
25
Gate-source leakage
IGSS
Zero gate voltage drain current
IDSS
μA
-
0.025
0.029
Ω
gfs
VDS = 30 V, ID = 45 A
-
32
-
S
Input capacitance
Ciss
11 826
-
Coss
-
528
-
Reverse transfer capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 300 kHz
-
Output capacitance
-
9
-
Effective output capacitance, energy
related a
Co(er)
-
384
-
Effective output capacitance, time
related b
Co(tr)
-
1502
-
-
394
591
-
84
-
-
160
-
Drain-source on-state resistance
Forward transconductance a
RDS(on)
VGS = 10 V
ID = 45 A
Dynamic
pF
VGS = 0 V, VDS = 0 V to 520 V
Total gate charge
Qg
Gate-source charge
Qgs
Gate-drain charge
Qgd
Turn-on delay time
td(on)
-
85
128
tr
-
152
228
-
323
485
Rise time
Turn-off delay time
td(off)
Fall time
tf
Gate input resistance
Rg
VGS = 10 V
ID = 45 A, VDS = 520 V
VDD = 520 V, ID = 45 A,
VGS = 10 V, Rg = 9.1 Ω
f = 1 MHz, open drain
-
267
401
0.6
1.2
2.4
-
-
87
-
-
323
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current
ISM
Diode forward voltage
VSD
Reverse recovery time
trr
Reverse recovery charge
Qrr
Reverse recovery current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 45 A, VGS = 0 V
TJ = 25 °C, IF = IS = 45 A,
dI/dt = 100 A/μs, VR = 25 V
-
0.9
1.2
V
-
971
1942
ns
-
26
52
μC
-
42
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91585
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHS90N65E
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
300
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
200
ID = 45 A
RDS(on), Drain-to-Source On-Resistance
(Normalized)
150
100
50
0
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
20
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
100 000
150
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
120
90
TJ = 150 °C
Ciss
10 000
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
2.5
60
1000
VGS = 0 V, f = 300 kHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
Crss
10
30
1
0
0
5
10
15
VDS, Drain-to-Source Voltage (V)
0
20
100
200
300
400
500
VDS, Drain-to-Source Voltage (V)
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
350
70
5000
60
50
210
Coss (pF)
ID, Drain-to-Source Current (A)
TJ = 25 °C
280
TJ = 150 °C
140
Eoss
40
Coss
500
30
Eoss (μJ)
ID, Drain-to-Source Current (A)
250
3.0
TJ = 25 °C
20
70
10
VDS = 14.6 V
50
0
0
5
10
15
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0019-Rev. B, 18-Jan-2021
20
0
0
100
200
300
VDS
400
500
600
Fig. 6 - COSS and EOSS vs. VDS
Document Number: 91585
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiHS90N65E
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Vishay Siliconix
100
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
80
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
60
40
20
4
0
0
0
200
400
600
Qg, Total Gate Charge (nC)
800
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
25
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
VDS, Drain-to-Source Breakdown Voltage (V)
850
ISD, Reverse Drain Current (A)
100
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
VSD, Source-Drain Voltage (V)
1.4
1.6
Fig. 8 - Typical Source-Drain Diode Forward Voltage
1000
Operation in this Area
Limited by RDS(on)
825
800
775
750
725
700
675
ID = 250 μA
650
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM Limited
ID, Drain Current (A)
100
Limited by RDS(on)*
10
1
100 μs
1 ms
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.1
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91585
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHS90N65E
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Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
V DS
V DS
tp
V GS
V DD
D.U.T.
RG
+
- V DD
V DS
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
V DS
QG
10 V
90 %
QGS
QGD
VG
10 %
V GS
td(on)
td(off)
tr
tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
Vary t p to obtain
required IAS
VDS
50 kΩ
D.U.T.
RG
+
-
I AS
12 V
0.2 μF
0.3 μF
V DD
+
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91585
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiHS90N65E
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Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91585.
S21-0019-Rev. B, 18-Jan-2021
Document Number: 91585
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For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-274AA (High Voltage)
VERSION 1: FACILITY CODE = Y
B
A
E
E4
A
D2
E1
A1
R
D1
D
L1
L
Detail “A”
C
b
e
A2
0.10 (0.25) M B A M
10°
b4
b2
Lead Tip
5°
Detail “A”
Scale: 2:1
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
4.70
5.30
0.185
0.209
D1
15.50
16.10
0.610
0.634
A1
1.50
2.50
0.059
0.098
D2
0.70
1.30
0.028
0.051
A2
2.25
2.65
0.089
0.104
E
15.10
16.10
0.594
0.634
13.30
13.90
0.524
0.547
b
1.30
1.60
0.051
0.063
E1
b2
1.80
2.20
0.071
0.087
e
5.45 BSC
MAX.
0.215 BSC
b4
3.00
3.25
0.118
0.128
L
13.70
14.70
0.539
0.579
c (1)
0.38
0.89
0.015
0.035
L1
1.00
1.60
0.039
0.063
D
19.80
20.80
0.780
0.819
R
2.00
3.00
0.079
0.118
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outer extremes of the plastic body
• Outline conforms to JEDEC® outline to TO-274AA
(1) Dimension measured at tip of lead
Revision: 19-Oct-2020
Document Number: 91365
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
VERSION 2: FACILITY CODE = N
A
E
A
E3
B
D
D1
D2
E2
Q
A2
L1
F
F
H
H
C
G
L
G
A1
e
b
3x
0.25 M B A M
b1
C
b3
E4
E1
b’, b2, b4
C
C’
Base metal
b, b1, b3
Plating
SECTION "F-F", "G-G" AND "H-H"
SCALE: NONE
MILLIMETERS
MILLIMETERS
DIM.
MIN.
MAX.
DIM.
MIN.
MAX.
A
4.83
5.21
D1
16.25
17.65
A1
2.29
2.54
D2
0.50
0.80
A2
1.91
2.16
E
15.75
16.13
b’
1.07
1.28
E1
13.10
14.15
b
1.07
1.33
E2
3.68
5.10
b1
1.91
2.41
E3
1.00
1.90
b2
1.91
2.16
E4
12.38
13.43
b3
2.87
3.38
e
b4
2.87
3.13
N
c’
0.55
0.65
L
19.81
c
0.55
0.68
L1
3.70
4.00
D
20.80
21.10
Q
5.49
6.00
5.44 BSC
3
20.32
ECN: E20-0538-Rev. C, 19-Oct-2020
DWG: 5975
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Outline conforms to JEDEC® outline to TO-274AD
• Dimensions are measured in mm, angles are in degree
• Metal surfaces are tin plated, except area of cut
Revision: 19-Oct-2020
Document Number: 91365
2
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
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Product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited
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