SIP12108ADMP-T1GE4

SiP12108, SiP12108A www.vishay.com Vishay Siliconix 2.8 V to 5.5 V Input 5 A Synchronous Buck Regulator FEATURES • • • • • • • • DESCRIPTION 2.8 V to 5.5 V input voltage Adjustable output voltage down to 0.6 V 5 A continuous output current Programmable switching frequency up to 4 MHz 95 % peak efficiency Stable with any capacitor. No external ESR network required. Ultrafast transient response Selectable power saving (PSM) mode or forced continuous mode ± 1 % accuracy of VOUT setting Pulse-by-pulse current limit Scalable with SiP12107 - 3 A SiP12108 is fully protected with OTP, SCP, UVP, OVP SiP12108A is fully protected with OTP, SCP, OVP The SiP12108 is a high frequency current-mode constant on-time (CM-COT) synchronous buck regulator with integrated high-side and low-side power MOSFETs. Its power stage is capable of supplying 5 A continuous current at 4 MHz switching frequency. This regulator produces an adjustable output voltage down to 0.6 V from 2.8 V to 5.5 V input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. • • • • • SiP12108’s CM-COT architecture delivers ultra-fast transient response with minimum output capacitance and tight ripple regulation at very light load. The part is stable with any capacitor type and no ESR network is required for loop stability. The device also incorporates a power saving scheme that significantly increases light load efficiency. • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 • PGOOD indicator • PowerCAD Simulation software available at vishay.transim.com/login.aspx APPLICATIONS • Point of load regulation for low-power processors, network processors, DSPs, FPGAs, and ASICs • Low voltage, distributed power architectures with 3.3 V or 5 V rails • Computing, broadband, networking, LAN/WAN, optical, test and measurement • A/V, high density cards, storage, DSL, STB, DVR, DTV, Industrial PC The SiP12108 integrates a full protection feature set, including output overvoltage protection (OVP), output under voltage protection (UVP) and thermal shutdown (OTP). The “A” version of the device, SiP12108A, does not have the UVP feature. They also incorporate UVLO for the input rail and an internal soft-start ramp. The SiP12108 is available in lead (Pb)-free power enhanced 3 mm x 3 mm QFN16-33G package. TYPICAL APPLICATION CIRCUIT POWER SAVE MODE ENABLE POWER GOOD INPUT = 2.8 V to 5.5 V PGOOD EN AUTO VIN VOUT LX VOUT VFB AVIN PGND GMO AGND RON Fig. 1 - Typical Application Circuit for SiP12108 S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 1 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix ABSOLUTE MAXIMUM RATINGS ELECTRICAL PARAMETER CONDITIONS LIMIT VIN Reference to PGND -0.3 to 6 AVIN Reference to AGND -0.3 to 6 LX Reference to PGND UNIT V -0.3 to 6 AGND to PGND -0.3 to 0.3 All logic inputs Reference to AGND -0.3 to AVIN + 0.3 TEMPERATURE Max. operating junction temperature 150 Storage temperature °C -65 to +150 POWER DISSIPATION Junction to ambient thermal impedance (RthJA) Maximum power dissipation 36.3 Ambient temperature = 25 °C 3.4 Ambient temperature = 100 °C 1.3 HBM 4 °C/W W ESD PROTECTION Electrostatic discharge protection kV Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM VIN 2.8 - 5.5 AVIN 2.8 - 5.5 LX -1 - 5.5 VOUT 0.6 - 0.85 x VIN Ambient temperature S20-0484-Rev. C, 29-Jun-2020 -40 to +85 UNIT V °C Document Number: 62699 2 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS PARAMETER SYMBOL TEST CONDITION UNLESS OTHERWISE SPECIFIED VIN = AVIN = 3.3 V, TA = -40 °C to +85 °C LIMITS MIN. TYP. MAX. VIN 2.8 - 5.5 AVIN 2.8 - 5.5 UNIT POWER SUPPLY Power input voltage range Bias input voltage range V IIN_NOLOAD Non- switching, IO = 0 A, Ron = 100 k, AUTO = Low - 1200 - IIN_SHDN EN = 0 V - 6 9.5 AVIN UVLO threshold AVIN_UVLO AVIN rising 2.3 2.55 2.8 V AVIN UVLO hysteresis AVIN_UVLO_HYS - 300 - mV TA = 0 °C to +70 °C 0.594 0.600 0.606 TA = -40 °C to +85 °C 0.591 0.600 0.609 2 200 nA mS Input current Shutdown current μA PWM CONTROLLER Feedback reference VFB VFB input bias current IFB - Transconductance GMO source current GMO sink current Switching frequency range gm - 1 - IGMO_SOURCE - 50 - IGMO_SINK - 50 - fSW Guaranteed by design 0.2 - 4 Minimum on-time tON_MIN Guaranteed by design - 50 - Minimum off-time tOFF_MIN VOUT = 1.2 V, RON = 100 k - 125 - - 1.5 - - 35 51 - 23 35 Soft start time tSS V μA MHz ns ms INTEGRATED MOSFETs High-side on resistance RON_HS Low-side on resistance RON_LS VIN = AVIN = 5 V m FAULT PROTECTIONS Over current limit IOCP - 7.5 - - 21 - - -25 - Rising temperature - 160 - Hysteresis - 30 - VFB_RISING_VTH_OV VFB rising above 0.6 V reference - 21 - VFB_FALLING_VTH_UV VFB falling below 0.6 V reference - -12.5 - Output OVP threshold VFB_OVP Output UVP threshold VFB_UVP Over temperature protection Inductor valley current VFB with respect to 0.6 V reference A % °C POWER GOOD Power good output threshold % Power good on resistance RON_PGOOD - 30 60  Power good delay time tDLY_PGOOD - 4 - μs Logic high Level VEN_H 1.5 - - Logic low Level VEN_L - - 0.4 ENABLE THRESHOLD S20-0484-Rev. C, 29-Jun-2020 V Document Number: 62699 3 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM 2 7 6 AVIN GMO AGND PGOOD 5 AUTO 3 1,16 EN VIN 8 OTP VIN 0.6 V REFERENCE UVLO SOFT START VIN + + OTA 9 + ON-TIME GENERATOR VFB CONTROL LOGIC SECTION LX ANTI-XCOND CONTROL 11,12,13 VIN PWM COMPARATOR I-V Converter Isense ZCD PGND RON 4 14,15 - OCP + VOUT UV Comparator (SiP12108 only) 0.45 V 10 Current Mirror + VFB 0.72 V PAD - OV Comparator Isense Fig. 2 - SiP12108 Functional Block Diagram ORDERING INFORMATION PART NUMBER MARKING (LINE 2: P/N) PACKAGE SiP12108DMP-T1GE4 QFN16 3 x 3 2108 SiP12108ADMP-T1GE4 (1) QFN16 3 x 3 108A SiP12108DB N/A SiP12108ADB (1) Note Output undervoltage protection (UVP) disabled (1) P/N FYWLL Format: Line 1: dot Line 2: P/N Line 3: Siliconix logo + ESD symbol Line 4: factory code + year code + work week code + LOT code S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 4 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix PGND LX VIN 16 PGND PIN CONFIGURATION 15 14 13 VIN 1 12 LX AVIN 2 11 LX 5 6 7 8 AGND 9 VFB GMO RON 4 PGOOD 10 VOUT AUTO EN 3 QFN16 3x3 Fig. 3 - SiP12108 Pin Configuration (Top View) PIN CONFIGURATION PIN NUMBER NAME 1, 16 VIN FUNCTION 2 AVIN 3 EN Enable pin. Pull enable above 1.5 V to enable the part and below 0.4 V to disable. Do not float this pin 4 RON An external resistor between RON and GND sets the switching on time 5 AUTO Input supply voltage for power MOS. VIN = 2.8 V to 5.5 V Input supply voltage for internal circuitry. AVIN = 2.8 V to 5.5 V Sets switching mode. Connect AUTO to AVIN for forced continuous mode and AUTO to GND for power save mode. Do not float 6 PGOOD Power good output. Open drain 7 GMO Connect to an external RC network for loop compensation and droop function 8 AGND Analog ground 9 VFB 10 VOUT 11, 12, 13 LX 14, 15 PGND EP S20-0484-Rev. C, 29-Jun-2020 Feedback voltage. 0.6 V (typ.). Use a resistor divider between VOUT and AGND to set the output voltage VOUT, output voltage sense connection Switching output, inductor connection point Power ground Exposed paddle (bottom). Connect to a good PCB thermal ground plane Document Number: 62699 5 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise) 100 100 90 90 VO - 1.8 V VO - 1.8 V 80 Efficiency (%) Efficiency (%) 80 VO - 1.2 V 70 60 50 70 60 50 40 40 30 30 20 0.01 0.1 1 IOUT (A) VO - 1.2 V 20 0.01 10 0.1 0.12 0.1 0.1 0.08 0.08 Load Regulation (%) Load Regulation (%) 0.12 VO - 1.8 V 0.04 VO - 1.2 V 0.02 10 Fig. 7 - Efficiency - PSM Mode Fig. 4 - Efficiency - PWM Mode 0.06 1 IOUT (A) 0 VO - 1.2 V 0.06 VO - 1.8 V 0.04 0.02 0 -0.02 -0.02 -0.04 0.01 0.1 1 IOUT (A) 10 -0.04 0.01 0.1 1 IOUT (A) 10 Fig. 8 - Load Regulation - PSM Mode Fig. 5 - Load Regulation - PWM Mode 1.2 1.2 VO - 1.2 V 1 1 VO - 1.2 V 0.8 fsw (MHz) fsw (MHz) 0.8 VO - 1.8 V 0.6 0.6 0.4 0.4 0.2 0.2 0 0.01 0.1 IOUT (A) 1 Fig. 6 - FSW Variation - PWM Mode S20-0484-Rev. C, 29-Jun-2020 10 0 0.01 VO - 1.8 V 0.1 IOUT (A) 1 10 Fig. 9 - FSW Variation - PSM Mode Document Number: 62699 6 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise) CH1 CH1 CH2 CH2 Fig. 10 - PWM Mode- Steady - State Ripple and LX, 5 A Load CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div Fig. 13 - PWM Mode- Steady - State Ripple and LX, 0 A Load CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div CH1 CH1 CH2 CH2 Fig. 11 - PSM Mode- Steady - State Ripple and LX, 0 A Load CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 10 ms/div Fig. 14 - PSM Mode- Steady - State Ripple and LX, 0 A Load CH1 = VOUT , 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div CH1 CH1 CH2 CH2 CH4 CH4 Fig. 12 - Load Step 0 A to 5 A to 0 A CH1 = Iload, CH2 = VOUT, 500 mV/div, CH4 = Icoil, 5 A/div, Time = 100 μs/div S20-0484-Rev. C, 29-Jun-2020 Fig. 15 - Load Step 0 A to 5 A, Rising Edge CH1 = Iload, CH2 = VOUT, 200 mV/div, CH4 = Icoil, 5 A/div, Time = 20 μs/div Document Number: 62699 7 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise) CH1 CH2 CH3 CH2 CH1 CH4 CH4 Fig. 16 - Load Step 0 A to 5 A, Falling Edge CH1 = Iload, CH2 = VOUT, 200 mV/div, CH4 = Icoil, 5 A/div, Time = 20 μs/div Fig. 19 - Turn-On Time PSM Mode, 0 A Load CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD, 5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div CH2 CH2 CH3 CH3 CH1 CH1 CH4 CH4 Fig. 17 - Turn-Off Time PSM Mode, 0 A Load CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD, 5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div Fig. 20 - Turn-On Time PWM Mode, 5 A Load CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD, 5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div CH2 CH3 CH1 CH4 Fig. 18 - Turn-Off Time PWM Mode, 5 A Load CH1 = VOUT , 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD, 5 V/div, CH4 = Icoil, 2 A/div, Time = 500 μs/div S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 8 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix OPERATIONAL DESCRIPTION Device Overview Power Stage SiP12108 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 5 A continuous current. The device has programmable switching frequency up to 4 MHz. The control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimizes external components. Thanks to the internal current ramp information, no high-ESR output bulk or virtual ESR network is required for the loop stability. This device also incorporates a power saving feature by enabling diode emulation mode and frequency foldback as load decreases. SiP12108 integrated synchronous MOSFETs . The MOSFETs are optimized to achieve 95 % efficiency at 2 MHz switching frequency. The power input voltage (VIN) can go up to 5.5 V and as low as 2.8 V for power conversion. The logic bias voltage (AVIN) ranges from 2.8 V to 5.5 V. PWM Control Mechanism SiP12108 employs a state-of-the-art current-mode COT control mechanism. During steady-state operation, output voltage is compared with internal reference (0.6 V typ.) and the amplified error signal (VCOMP) is generated on the COMP pin. In the meantime, inductor valley current is sensed, and its slope (Isense) is converted into a voltage signal (Vcurrent) to be compared with VCOMP. Once Vcurrent is lower than VCOMP, a single shot on-time is generated for a fixed time programmed by the external RON. Fig. 4 illustrates the basic block diagram for CM-COT architecture and Fig. 5 demonstrates the basic operational principle:   SiP12108 has a full set of protection and monitoring features: - Over current protection in pulse-by-pulse mode - Output over voltage protection - Output under voltage protection with device latch - Over temperature protection with hysteresis - Dedicated enable pin for easy power sequencing - Power good open drain output This device is available in QFN16 3 x 3 package to deliver high power density and minimize PCB area. RON Bandgap VOUT VOUT Vref HG + R1 OTA VIN - VIN R2 V comp HG ON-TIME Generator Control Logic & MOSFET Driver LG + - + Current Mirror Isense I-AMP - V current PWM COMPARATOR LS FET LG Fig. 21 - CM-COT Block Diagram S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 9 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix Vcurrent Vcomp Fixed ON-time PWM Fig. 22 - CM-COT Operational Principle The following equation illustrates the relationship between on-time, VIN, VOUT and RON value: TON = RON x K x Once on-time is set, the pseudo constant frequency is then determined by the following equation: VOUT D VIN 1 ࢌ sw = = = RON x K VOUT TON x RON x K VIN VOUT , where K = 10.45 x 10-12 a constant set internally VIN   Loop Stability and Compensator Design Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and AGND for loop stability and transient response purposes. The general concept of this loop design is to introduce a single zero through the compensator to determine the crossover frequency of overall close loop system. The overall loop can be broken down into following segments. Output feedback divider transfer function Hfb: R fb2 H fb = -----------------------------R fb1 x R fb2 Voltage compensator transfer function GCOMP (s): R O x  1 + sC COMP R COMP  G COMP (s) = ------------------------------------------------------------------------- gm  1 + sR O C COMP  Modulator transfer function Hmod (s): R load x  1 + sC O R ESR  1 H mod (s) = ----------------------------------- x -------------------------------------------------------------AV 1 x R DS(on)  1 + sC O R load  The complete loop transfer function is given by: R fb2 R O x  1 + sC COMP R COMP  R load x  1 + sC O R ESR  1 H mod (s) = ------------------------------ x -------------------------------------------------------------------------gm x ----------------------------------- x -------------------------------------------------------------R fb1 x R fb2  1 + sR O C COMP  AV 1 x R DS(on)  1 + sC O R load  When: CCOMP = compensation capacitor RDS(on) = LS switch resistance RCOMP = compensation resistor Rfb1 = feedback resistor connect to LX gm = error amplifier transconductance Rfb2 = feedback resistor connect to ground Rload = load resistance RO = output impedance of error amplifier = 20 M CO = output capacitor AV1 = voltage to current gain = 3 S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 10 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix Power Save Mode using AUTO Pin To further improve efficiency at light loads, SiP12108 provides a set of innovative implementations to eliminate LS recirculating current and switching losses. The internal zero crossing detector (ZCD) monitors LX node voltage to determine when inductor current starts to flow negatively. In power saving mode (PSM), as soon as inductor valley current crosses zero, the device first deploys diode emulation mode by turning off LS FET. If load further decreases, switching frequency is further reduced proportional to load condition to save switching losses. The switching frequency is set by the controller to maintain regulation. At zero load this frequency can go as low as hundreds of Hz. Whenever fixed frequency PWM operation is required over the entire load span, the power saving mode feature can be disabled by connecting AUTO pin to VIN or AVIN. OUTPUT MONITORING AND PROTECTION FEATURES Output Over-Current Protection (OCP) SiP12108 has pulse-by-pulse over-current limit control. The inductor valley current is monitored during LS FET turn-on period through RDS(on) sensing. After a pre-defined time, the valley current is compared with internal threshold (7.5 A typ.) to determine the threshold for OCP. If monitored current is higher than threshold, HS turn-on pulse is skipped and LS FET is kept on until the valley current returns below OCP limit. In the severe over-current condition, pulse-by-pulse current limit eventually triggers output under-voltage protection (UVP), which latches the device off to prevent catastrophic thermal-related failure. UVP is described in the next section. OCP is enabled immediately after AVIN passes UVLO level. Figure 6 illustrates the OCP operation. OCP threshold Iload Iinductor GH Skipped GH pulse Fig. 23 - Over-Current Protection Illustration Output Under-Voltage Protection (UVP) Over-Temperature Protection (OTP) UVP is implemented by monitoring output through VFB pin. Once the voltage level at VFB is below 0.45 V for more than 20 μs, then UVP event is recognized and both HS and LS MOSFETs are turned off. UVP latches the device off until either AVIN or EN is recycled. SiP12108 has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 160 °C (typ.). A hysteresis of 30 °C is implemented, so when junction temperature drops below 130 °C, the device restarts by initiating the soft-start sequence again. UVP is only active after the completion of soft-start sequence. This function only exists on SiP12108. On the “A” version of the device, SiP12108A, this feature is disabled. Soft Startup Output Over-Voltage Protection (OVP) For OVP implementation, output is monitored through VFB pin. After soft-start, if the voltage level at VFB is above 21 % (typ.), OVP is triggered with HS FET turning off and LS FET turning on immediately to discharge the output. Normal operation is resumed once VFB drops back to 0.6 V. OVP is active immediately after AVIN passes UVLO level.  S20-0484-Rev. C, 29-Jun-2020 SiP12108 deploys an internally regulated soft-start sequence to realize a monotonic startup ramp without any output overshoot. Once AVIN is above UVLO level (2.55 V typ.). Both the reference and VOUT will ramp up slowly to regulation in 1 ms (typ.) with the reference going from 0 V to 0.6 V and VOUT rising monotonically to the programmed output voltage. During soft-start period, OCP is activated. OVP and short-circuit protection are not active until soft-start is complete.  Document Number: 62699 11 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix Pre-bias Startup Power Good (PGOOD) In case of pre-bias startup, output is monitored through VFB pin. If the sensed voltage on VFB is higher than the internal reference ramp value, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. SiP12108’s Power Good is an open-drain output. Pull PGOOD pin high up to 5 V through a 10K resistor to use this signal. Power Good window is shown in the below diagram. If voltage level on VFB pin is out of this window, PGOOD signal is de-asserted by pulling down to GND. VFB_Rising_Vth_OV (typ. = 0.725 V ) VFB_Falling_Vth_OV (typ. = 0.675 V) Vref (0.6 V) VFB_Falling_Vth_UV (typ. = 0.525 V) V FB VFB_Rising_Vth_UV (typ. = 0.575 V) Pull -high PGOOD Pull -low Fig. 24 - PGOOD Window and Timing Diagram DESIGN PROCEDURE The design process of the SiP12108 is quite straight forward. Only few passive components such as output capacitors, inductor and Ron resistor need to be selected. Setting the Output Voltage The output voltage is set by using a resistor divider on the feedback (VFB) pin. The VFB pin is the negative input of the internal error amplifier. The following paragraph describes the selection procedure for these peripheral components for a given operating conditions. When in regulation the VFB voltage is 0.6 V. The output voltage VO is set based on the following formula. In the next example the following definitions apply: VO = VFB (1 + R1/R2) VINmax.: the highest specified input voltage where R1 and R2 are shown in Fig. 21. VINmin.: the minimum effective input voltage subject to voltage drops due to connectors, fuses, switches, and PCB traces Setting Switching Frequency Continuous load current relates to thermal stress considerations which drive the selection of the inductor and input capacitors. Selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. The desired switching frequency, 1 MHz was chosen based on optimizing efficiency while maintaining a small footprint and minimizing component cost. Peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. In order to set the design for 1 MHz switching frequency, (RON) resistor which determines the on-time (indirectly setting the frequency) needs to be calculated using the following equation. There are two values of load current to evaluate - continuous load current and peak load current. The following specifications are used in this design: • VIN = 3.3 V ± 10 % 1 1 R ON = ---------------------- = --------------------------------------------------------------  105 k 6 -12 F SW x K 1 x 10 x 10,45 x 10 • VOUT = 1.2 V ± 1 % • fSW = 1 MHz • Load = 5 A maximum S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 12 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix INDUCTOR SELECTION STABILITY CONSIDERATIONS In order to determine the inductance, the ripple current must first be defined. Cost, PCB size, output ripple, and efficiency are all used in the selection process. Low inductor values result in smaller size and allow faster transient performance but create higher ripple current which can reduce efficiency. Higher inductor values will reduce the ripple current while compromising the efficiency (higher DCR) and transient response. Using the output capacitance as a starting point for compensation values. Then, taking Bode plots and transient response measurements we can fine tune the compensation values. The ripple current will also set the boundary for power-save operation. The switcher will typically enter power-save mode when the load current decreases to 1/2 of the ripple current. For example, if ripple current is 1 A then power-save operation will typically start at loads approaching 0.5 A. Alternatively, if ripple current is set at 40 % of maximum load current, then power-save will start for loads less than ~ 20 % of maximum current. Inductor selection for the SiP12108 should be designed where the ripple current is ~ 50 % in all situations with VIN 3.6 V and less. For example 3.3 VIN to 1.2 VOUT at 1 MHz. dI = V/L x dt = ((3.3 - 1.2)/0.33) x 0.36 = 2.3 A, %dI = 2.3/5 = 46 %. For higher VIN > 3.6 V ripple current should be set to less then 40 %. For 5 VIN to 1.2 VOUT at 1 MHz dI = ((5 - 1.2)/0.68) x 0.36) = 2 A, %dI = 2/5 = 40 %. Output Capacitance Calculation The output capacitance is usually chosen to meet transient requirements. A worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes from maximum to zero in < 1/fSW μs), the output capacitor must absorb all the inductor’s stored energy. This will approximately cause a peak voltage on the capacitor according to the following equation. 2 1 L x  I OUT + --- x I RIPPLEmax.   2 C OUTmin. = -----------------------------------------------------------------------2 2  V peak  -  V OUT  Assuming a peak voltage VPEAK of 1.3 V (100 mV rise upon load release), and a 5 A load release, the required capacitance is shown by the next equation. COUTmin. = 1 μH x (5 A + 0.5 x (0.81 A))2 = 116.8 μF (1.3 V)2 - (1.2 V)2 Setting the crossover frequency to 1/5 of the switching frequency:  f0 = fsw/5 = 1 MHz/5 = 200 kHz Setting the compensation zero at 1/5 to 1/10 the crossover frequency for the phase boost: FZ = F 1 = 0 2π x RC x CC 5 Setting CC = 0.47 nF and solve for RC RC = 5 2π x CC x F0 = 5 = 8.469K 2π x 0.47 nF x 200K SWITCHING FREQUENCY VARIATIONS The switching frequency variation in COT can be mainly attributed to the increase in conduction losses as the load increases. The on time is “ideally constant” so the controller must account for losses by reducing the off time which increases the overall duty cycle. Hence the FSW will tend to increase with load. In power save mode (PSM) the IC will run in pulse skip mode at light loads. As the load increases the FSW will increase until it reaches the nominal set FSW. This transition occurs approximately when the load reaches to 20 % of the full load current. DESIGN CONSIDERATION For VOUT higher then UVLO (2.55 V typ.) and/or very slow VIN slew rates. The IC may have difficulty in starting-up because VIN level is limiting how fast VOUT can rise. In these situations a divider for EN pin threshold (~1.15 V) derived from VIN can be used. Allowing a higher VIN level before switching begins and a smooth start-up. For example Rtop = 60K and Rbot = 25K when VIN=4 V, EN level will be 1.18 V. THERMAL DESIGN The 16 pin package includes a thermal pad for much better thermal performance when incorporated in the PCB footprint. As shown in the PCB layout at the end of this document. There are four vias evenly placed on the pad that help transfer the heat to other layers. Tying the paddle to the bottom layer through vias will provide the best thermal performance. If the load release is relatively slow, the output capacitance can be reduced. Using MLCC ceramic capacitors we will use 5 x 22 μF or 110 μF as the total output capacitance.   S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 13 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix J1 VIN J4 VIN_GND 1 1 VIN C4 22 μF C5 0.1 μF R8 1 J7 EN 1 C6 0.1 μF R2 100K R3 100K R4 100K R1 100K J5 MODE 1 17 VIN1 R5 6K04 C7 470 pF 8 AUTO VIN2 PGOOD U1 SiP12107/8 COMP 7 AVIN PGOOD 6 EN RON MODE 5 1 3 4 J6 PGOOD 1 AVIN 2 RON COMP AGND PGND2 PGND1 LX1 16 15 14 13 AGND-PAD LX2 LX3 VO FB 12 11 10 9FB VO LX C8 (1) 0.1 μF L1 0.47 μH R6 5K11 R7 2K55 C1 0.1 μF C2 22 μF VOGND Note This capacitor is optional (1) C3 22 μF 1 1 J2 VO J3 VO_GND Fig. 25 - Reference Board Schematic S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 14 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix BILL OF MATERIALS ITEM QTY. REFERENCE VALUE VOLTAGE PCB FOOTPRINT PART NUMBER MANUFACTURE R 1 2 C1, C5 0.1 μF 50 V C0402-TDK VJ0402Y104MXQCW1BC Vishay 2 2 C2, C3, C4 22 μF 10 V C0805-TDK LMK212BJ226MG-T Murata 4 1 C6 0.1 μF 10 V C0603-TDK GRM188R71C104KA01D Murata 5 1 C7 470 pF 50 V C0402-TDK VJ0402A471JXACW1BC TDK 6 1 C8 (1) DNP - C0603-TDK - - 7 1 J1 VIN - TP30 5002K-ND Keystone 8 1 J2 VO - TP30 5002K-ND Keystone 9 1 J3 VO_GND - TP30 5002K-ND Keystone 10 1 J4 VIN_GND - TP30 5002K-ND Keystone 11 1 J5 MODE - TP30 5002K-ND Keystone 12 1 J6 PGOOD - TP30 5002K-ND Keystone 13 1 J7 EN - TP30 5002K-ND Keystone 14 1 L1 0.47 μH - IHLP1616 IHLP1616BZERR47M11 Vishay 15 4 R1, R2, R3, R4 100K 50 V R0402-Vishay CRCW0402100KFKED Vishay 16 1 R5 6K04 50 V R0402-Vishay TNPW04026K04BETD  Vishay 17 1 R6 5K11 50 V R0402-Vishay CRCW04025K11FKED Vishay 18 1 R7 2K55 50 V R0402-Vishay TNPW04022K55BETD  Vishay 19 1 R8 1 50 V R0402-Vishay RC0402FR-071RL Yageo U1 SiP12107, SiP12108 - MLP16-33 SiP1210x Vishay 20 1 PCB LAYOUT OF REFERENCE BOARD Fig. 26 - Top Layer S20-0484-Rev. C, 29-Jun-2020 Fig. 27 - Bottom Layer Document Number: 62699 15 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiP12108, SiP12108A www.vishay.com Vishay Siliconix PRODUCT SUMMARY Part number SiP12108 SiP12108A Description 5 A, 2.8 V to 5.5 V input, 4 MHz synchronous buck regulator with UVP 5 A, 2.8 V to 5.5 V, 4 MHz synchronous buck regulator with output UVP disabled Input voltage min. (V) 2.8 2.8 Input voltage max. (V) 5.5 5.5 Output voltage min. (V) 0.6 0.6 Output voltage max. (V) 5.5 5.5 Continuous current (A) 5 5 Switch frequency min. (kHz) 200 200 Switch frequency max. (kHz) 4000 4000 Pre-bias operation (yes / no) Yes Yes Internal bias reg. (yes / no) Yes Yes External External Compensation Enable (yes / no) Yes Yes PGOOD (yes / no) Yes Yes Overcurrent protection Protection Light load mode Peak efficiency (%) Package type Package size (W, L, H) (mm) Fixed Fixed OVP, OCP, UVP/SCP, OTP, UVLO OVP, OCP, OTP, SCP, UVLO Powersave Powersave 95 95 QFN16-33G QFN16-33G 3.0 x 3.0 x 0.8 3.0 x 3.0 x 0.8 Status code 2 2 Product type microBUCK (step down regulator) microBUCK (step down regulator) Applications Computing, consumer, networking, industrial, Computing, consumer, networking, industrial, healthcare healthcare                                  Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62699. S20-0484-Rev. C, 29-Jun-2020 Document Number: 62699 16 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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ALL RIGHTS RESERVED Revision: 01-Jan-2023 1 Document Number: 91000