TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Features
Ultra-low Distortion: 0.0001% at 1 kHz
Low Noise: 17 nV/√Hz
High Slew Rate: 6.5 V/μs
Wide Bandwidth: 10 MHz
Low Supply Current: 1.2mA per Amplifier
Wide Supply Range: 2.7 V to 36 V,
or Dual-Supply ±1.35 V to ±18 V
Low Input Offset Voltage: 0.5 mV Typical
Low VOS TC: 2.0 µV/°C
Low Input Bias Current: 0.04 pA Typical
Rail-to-Rail Output Voltage Range
Unity Gain Stable for 220pF Capacitive Load
Drive 600 Ω Load
–40°C to 125°C Operation Range
Green, Popular Type Package
Description
The TP2604/2608 are ultra-low distortion, high-voltage
CMOS op-amps featuring THD+N of 0.0001% at 1kHz.
This feature along with its low noise, very high PSRR
makes TP260x ideal choices for professional audio
equipments.
The TP2604/2608 are unity gain stable with 220pF
capacitive load with a wide 10MHz bandwidth, 6.5V/μs
high slew rate, which makes the device appropriate for
current-to-voltage converters.
The TP2604/2608 can operate from a single-supply
voltage of +2.7V to +36.0V or a dual-supply voltage of
±1.35V to ±18.0V. Rail-to-rail output characteristics
allow the full power-supply voltage to be used for signal
range.
The TP2604 is dual channel version available in 8-pin
SOIC and MSOP package. The TP2608 is quad
channel version available in 14-pin SOIC and TSSOP
package.
3PEAK and the 3PEAK logo are registered trademarks of
Applications
Professional Audio Equipments
Line Drivers or Line Receivers
Pre-amplification and Filtering
PCM DAC I/V Converter
Transducer Amplifier
Data Acquisition
Pin Configuration (Top View)
3PEAK INCORPORATED. All other trademarks are the property of
their respective owners.
Related 36V RRO Op-amps
Supply Voltage
Single 2.7V to 36V or Dual ±1.35V to ±18V
Supply Current
125 μA
GBWP
Slew Rate
350 μA
1.2 mA
1.5 MHz
3 MHz
10 MHz
0.8 V/μs
3 V/μs
6.5 V/μs
Dual
TP2614
TP2634
TP2604
Quad
TP2618
TP2638
TP2608
LEFT
DAC
TP2604
RIGHT
DAC
Figure 1. TP2604 in Audio Equipment
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Order Information
Model Name
TP2604
TP2608
Order Number
Package
Marking
Information
Transport Media, Quantity
TP2604-SR
8-Pin SOIC
Tape and Reel, 4,000
2604S
TP2604-VR
8-Pin MSOP
Tape and Reel, 3,000
2604V
TP2608-SR
14-Pin SOIC
Tape and Reel, 2,500
2608S
TP2608-TR
14-Pin TSSOP
Tape and Reel, 3,000
2608T
Note (1): ‘YW’ is date coding scheme. 'Y' stands for calendar year, and 'W' stands for single workweek coding scheme.
Absolute Maximum Ratings Note 1
Supply Voltage: V+ – V–....................................48.0V
–
+
Input Voltage............................. V – 0.3 to V + 0.3
Current at Supply Pins……………............... ±60mA
Operating Temperature Range........–40°C to 125°C
±20mA
Maximum Junction Temperature................... 150°C
Output Current: OUT.................................... ±25mA
Storage Temperature Range........... –65°C to 150°C
Input Current: +IN, –IN
Note 2..........................
Output Short-Circuit Duration
Note 3….........
Indefinite
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input
current should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many
amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces
connected to the leads.
ESD, Electrostatic Discharge Protection
2
Symbol
Parameter
Condition
HBM
Human Body Model ESD
MIL-STD-883H Method 3015.8
3
kV
CDM
Charged Device Model ESD
JEDEC-EIA/JESD22-C101E
2
kV
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Electrical Characteristics
The specifications are at TA = 27°C. VSUPPLY = ±15V, VCM = VOUT =0V, RL = 100kΩ, CL =100pF.
SYMBOL
VOS
VOS TC
IB
PARAMETER
UNITS
-4.0
+4.0
mV
Input Offset Voltage Drift
-40°C to 125°C
TA = 27 °C
0.04
pA
TA = 85 °C
100
pA
TA = 125 °C
5.7
nA
0.001
pA
f = 0.1Hz to 10Hz
3.2
μVRMS
f = 20Hz to 20kHz
2.0
μVRMS
f = 1kHz
Differential
Common Mode
VCM = -14.6V to 13V
17
nV/√Hz
Input Bias Current
Input Voltage Noise
Input Voltage Noise Density
Input Capacitance
PSRR
Common Mode Rejection Ratio
Common-mode Input Voltage
Range
Power Supply Rejection Ratio
AVOL
Open-Loop Large Signal Gain
VOL, VOH
Output Swing from Supply Rail
RLOAD = 100kΩ
ROUT
Closed-Loop Output Impedance
RO
VCM
MAX
±0.5
2.0
VN
CMRR
TYP
VCM = VDD/2
Input Offset Current
CIN
MIN
Input Offset Voltage
IOS
eN
CONDITIONS
μV/°C
2.9
5
126
V–
pF
dB
V+-2.0
V
130
dB
VOUT = 0V, RLOAD = 100kΩ
110
130
dB
VOUT = -14.9V to 14.9V, RLOAD = 100kΩ
110
130
dB
50
mV
G = 1, f = 1kHz, IOUT = 0
0.01
Ω
Open-Loop Output Impedance
f = 1kHz, IOUT = 0
125
Ω
ISC
Output Short-Circuit Current
Sink or source current
25
mA
VDD
Supply Voltage
IQ
Quiescent Current per Amplifier
PM
Phase Margin
GM
GBWP
SR
FPBW
tS
THD+N
Xtalk
2.7
36
V
1.2
mA
RLOAD = 100kΩ, CLOAD = 100pF
56
°
Gain Margin
RLOAD = 100kΩ, CLOAD = 100pF
8
dB
Gain-Bandwidth Product
f = 1kHz
AV = 1, VOUT = 0V to 10V, CLOAD = 100pF,
RLOAD = 100kΩ
10
MHz
6.5
V/μs
70
1.5
1.6
kHz
0.0001
%
110
dB
Slew Rate
Full Power Bandwidth Note 1
Settling Time, 0.1%
Settling Time, 0.01%
Total Harmonic Distortion and
Noise
Channel Separation
AV = –1, 10V Step
f = 1kHz, AV =1, RL = 1kΩ, VOUT = 3.5VRMS
f = 1kHz, RL = 1kΩ
μs
Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Typical Performance Characteristics
Total Harmonic Distortion + Noise vs. Frequency
Total Harmonic Distortion + Noise vs. Output Voltage
0.01
0.1
V DD=30V
RL=1kΩ
Vo=3.5Vrms
0.001
THD+N (%)
THD+N (%)
0.01
VDD=30V
RL=1kΩ
f=1kHz
G=10V/V
0.001
0.0001
0.0001
G=1V/V
0.00001
0.00001
10
100
1k
10k
Frequency (Hz)
0.1
100k
1
10
100
Output Voltage (Vp-p)
Open-Loop Gain and Phase
Input Voltage Noise Spectral Density
1k
180
V DD=30V
RL=1kΩ
Noise (nV/√Hz)
Gain(dB) & Phase
130
Phase
80
30
1
1
10
100
1k 10k 100k
Frequency (Hz)
1M
0.1
10M 100M
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Input Bias Current vs. Temperature
Input Bias Current vs. Input Common Mode Voltage
1E-08
1E-08
1E-10
Input Bias Current (A)
Input Bias Current (A)
10
Open Loop Gain
-20
1E-12
1E-14
1E-16
1E-10
1E-12
1E-14
1E-18
-50
0
50
Temperature (C)
-15
100
-10
-5
0
5
10
Common Mode Voltage (V)
15
4
100
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Common Mode Rejection Ratio
Unity Gain Bandwidth vs. Temperature
12
Unity Gain Bandwidth (MHz)
CMRR(dB)
150
100
11.5
11
50
-15
-10
-5
0
5
10
Common Mode Voltage (V)
-50
15
0
50
100
Temperature (C)
Quiescent Current vs. Temperature
Short Circuit Current vs. Temperature
Short Circuit Current (mA)
31
30
29
Sinking Current
28
27
26
25
Sourcing Current
24
-50
0
50
Temperature (C)
100
Power-Supply Rejection Ratio
Quiescent Current vs. Supply Voltage
150
PSRR+
PSRR(dB)
PSRR100
50
0
1
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Pin Functions
-IN: Inverting Input of the Amplifier. Voltage range of this pin can go from V– to (V+ - 2.0V).
+IN: Non-Inverting Input of Amplifier. This pin has the same voltage range as –IN.
OUT: Amplifier Output. The voltage range extends to within milli-volts of each supply rail.
V+ or +VS: Positive Power Supply. Typically the voltage is from 2.7V to 36V. Split supplies are possible as long as the
voltage between V+ and V– is between 2.7V and 36V. A bypass capacitor of 0.1μF as close to the part as possible
should be used between power supply pins or between supply pins and ground.
V– or –VS: Negative Power Supply. It is normally tied to ground. It can also be tied to a voltage other than ground as
long as the voltage between V+ and V– is from 2.7V to 36V. If it is not connected to ground, bypass it with a capacitor of
0.1μF as close to the part as possible.
Operation
The TP2604 and TP2608 have input signal range from V– to (V+ – 2.0V). The output can extend all the way to the
supply rails. The input stage is comprised of a PMOS differential amplifier for best noise and THD performance. The
Class-AB control buffer and output bias stage uses a proprietary compensation technique to take full advantage of the
process technology to drive very high capacitive loads. This is evident from the transient over shoot measurement
plots in the Typical Performance Characteristics.
Applications Information
Wide Supply Voltage
The TP2604/2608 operational amplifiers can operate with power supply voltages from 2.7V to 36V. Each amplifier
draws 1.2mA quiescent current at 30V supply voltage. The TP2604/2608 is optimized for wide bandwidth low power
applications. They have an industry leading high GBW to power ratio and the GBW remains nearly constant over
specified temperature range.
Low Input Referred Noise
The TP2604/2608 provides a low input referred noise density of 17nV/√Hz at 1kHz. The voltage noise will grow
slowly with the frequency in wideband range, and the input voltage noise is typically 2.0μVRMS at the frequency of 20Hz
to 20kHz.
Ultra Low Distortion
The TP2604/2608 has an ultra low distortion of less than 0.0001% at 1kHz. Along with its low voltage noise,
TP2604/2608 is ideal for high-fidelity audio signal amplification or filtering.
Low Input Bias Current
The TP2604/2608 is a CMOS OPA family and features very low input bias current in pA range. The low input bias
current allows the amplifiers to be used in applications with high resistance sources. Care must be taken to minimize
PCB Surface Leakage. See below section on “PCB Surface Leakage” for more details.
PCB Surface Leakage
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be
considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow,
which is greater than the TP2604/2608 OPA’s input bias current at +27°C (±1pA, typical). It is recommended to use
multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface.
The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is
biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 2 for Inverting
Gain application.
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
1. For Non-Inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface.
b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage.
2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors):
a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the
op-amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface.
Figure 2 The Layout of Guard Ring
Ground Sensing and Rail to Rail Output
The TP2604/2608 family has excellent output drive capability. It drives 600 load directly with good THD performance.
The output stage is a rail-to-rail topology that is capable of swinging to within 50mV of either rail.
The maximum output current is a function of total supply voltage. As the supply voltage to the amplifier increases, the
output current capability also increases. Attention must be paid to keep the junction temperature of the IC below 150°C
when the output is in continuous short-circuit. The output of the amplifier has reverse-biased ESD diodes connected to
each supply. The output should not be forced more than 0.3V beyond either supply, otherwise current will flow through
these diodes.
Driving Large Capacitive Load
The TP2604/2608 op-amp family is designed to drive large capacitive loads. As always, larger load capacitance
decreases overall phase margin in a feedback system where internal frequency compensation is utilized. As the load
capacitance increases, the feedback loop’s phase margin decreases, and the closed-loop bandwidth is reduced. This
produces gain peaking in the frequency response, with overshoot and ringing in output step response. The unity-gain
buffer (G = +1V/V) is the most sensitive to large capacitive loads.
When driving large capacitive loads with the TP2604/2608 op-amp family (e.g., > 1,000 pF), different compensation
schemes (Figure 3) improve the feedback loop’s phase margin and stability.
CC 120 1012 CL RC
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R2
4CL 1010 1
CC
CL 103
RC
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
CC
50
R2
CL
RC
R2
2CL 1010 1 R2 R1
CC
CL 103
RC
RC
NOTE
R2
10
2CL 10 1 R2 R1
CC
CL 103
R2
RC
10
RC
2CL 10 1 R2 R1
CC
CL 103
RC
: Design equations and component values are approximate, User adjustment is required for optimum performance.
Figure 3 Driving Large Capacitive Loads
Power Supply Layout and Bypass
The TP2604/2608 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01μF to
0.1μF) within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger) within
100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts.
Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs
and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external
components as close to the op amps’ pins as possible.
Proper Board Layout
To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid
leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances due to
output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected
as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the
amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling.
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple
effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers
and types of components, where possible to match the number and type of thermocouple junctions. For example,
dummy components such as zero value resistors can be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads
are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from
amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a
constant temperature across the circuit board.
fp 20kHz
Figure 4 Three-Pole Low-Pass Filter
DAC I/V Amplifier and Low-Pass Filter
Low pass
2 pole Butterworth
C1*
COUT
2 R1fc
f-3dB 20KHz
R1 Feedback resistance 2k
fc Crossover frequency 8MHz
Figure 5 DAC I/V Amplifier and Low-Pass Filter
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Package Outline Dimensions
SO-8 (SOIC-8)
A2
C
θ
L1
A1
e
E
D
Symbol
E1
10
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Dimensions In
In Millimeters
Inches
Min
Max
Min
Max
A1
0.100
0.250
0.004
0.010
A2
1.350
1.550
0.053
0.061
b
0.330
0.510
0.013
0.020
C
0.190
0.250
0.007
0.010
D
4.780
5.000
0.188
0.197
E
3.800
4.000
0.150
0.157
E1
5.800
6.300
0.228
0.248
e
b
Dimensions
1.270 TYP
0.050 TYP
L1
0.400
1.270
0.016
0.050
θ
0°
8°
0°
8°
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Package Outline Dimensions
MSOP-8
Dimensions
Dimensions In
In Millimeters
Inches
Min
Max
Min
Max
A
0.800
1.200
0.031
0.047
A1
0.000
0.200
0.000
0.008
A2
0.760
0.970
0.030
0.038
b
0.30 TYP
0.012 TYP
C
0.15 TYP
0.006 TYP
D
2.900
e
0.65 TYP
E
2.900
3.100
0.114
0.122
E1
4.700
5.100
0.185
0.201
L1
0.410
0.650
0.016
0.026
θ
0°
6°
0°
6°
Symbol
E
E1
e
b
D
3.100
0.114
0.122
0.026
A1
R1
R
θ
L1
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L
L2
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Package Outline Dimensions
SO-14 (SOIC-14)
Dimensions
In Millimeters
Symbol
MIN
TYP
MAX
A
1.35
1.60
1.75
A1
0.10
0.15
0.25
A2
1.25
1.45
1.65
b
0.36
D
8.53
8.63
8.73
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
L
0.49
1.27 BSC
0.45
0.60
L1
1.04 REF
L2
0.25 BSC
θ
0°
0.80
8°
12
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TP2604 / TP2608
Dual/Quad, Ultra‐low Distortion, 36V RRO Op‐amps
Package Outline Dimensions
TSSOP-14
Dimensions
E1
E
e
A
A2
c
D
Symbol
In Millimeters
MIN
TYP
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.90
1.00
1.05
b
0.20
-
0.28
c
0.10
-
0.19
D
4.86
4.96
5.06
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
e
L
A1
R1
R
0.65 BSC
0.45
0.60
0.75
L1
1.00 REF
L2
0.25 BSC
R
0.09
-
-
θ
0°
-
8°
θ
L1
L
L2
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