3PEAK
TP07
Precision RRO Operational Amplifier
Features
Description
Low Offset Voltage: 100μV Maximum
Low Drift: ±0.9μV/°C
High EMIRR: 84dB at 900MHz
Low Noise: 19 nV/√Hz(f= 1kHz)
Wide Input Voltage Range: 0 to ±14V
Wide Supply Range: ±1.35V to ±18V
Low Input Bias Current: 40pA Typical
Below-Ground (V-) Input Capability to -0.3V
Rail-to-Rail Output Voltage Range
Unit Gain Stable
–40°C to 125°C Operation Range
Robust 3kV – HBM and 2kV – CDM ESD Rating
Direct or Update Replacement for OP07C,OP07D
and OP37
Applications
Wireless Base Station Control Circuits
Optical network Control Circuits
I/V Converter
Temperature Measurements
Strain Gage Amplifier
Medical Instrumentation
The TP07 has very low input offset voltage (100μV
maximum) that is obtained by trimming at the wafer
stage. The low offset voltages generally eliminate any
need for external nulling. The TP07 also features low
input bias current (±40 pA) and high open-loop gain
(118 dB). The low offset and high open-loop gain make
the TP07 particularly useful for high gain
instrumentation applications.
The wide input voltage range of ± 14 V minimum
combined with a high CMRR of 126 dB and high input
impedance provide high accuracy in the non-inverting
circuit configuration. Excellent linearity and gain
accuracy can be maintained even at high closed-loop
gains. Stability of offsets and gain with time or
variations in temperature is excellent. The accuracy
and stability of the TP07, even at high gain, made the
TP07 an industry standard for instrumentation
applications.
The TP07 is single channel available in 8-pin SOIC
package.
3PEAK and the 3PEAK logo are registered trademarks of
3PEAK INCORPORATED. All other trademarks are the property of
their respective owners.
Pin Configuration (Top View)
TP07
8-Pin SOIC
(-S Suffix)
NC
1
8
NC
﹣In
2
7
﹢Vs
﹢In
3
6
Out
﹣Vs
4
5
NC
TP07
Order Information
Model Name
TP07
www.3peakic.com
Order Number
TP07-SR
Package
8-Pin SOIC
Transport Media, Quantity
Marking
Information
Tape and Reel, 4,000
D41S
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TP07
Precision RRO Operational Amplifier
Absolute Maximum Ratings Note 1
Supply Voltage: V+ – V– Note 2............................40.0V
–
+
Input Voltage............................. V – 0.3 to V + 0.3
Input Current: +IN, –IN
Note 3..........................
Current at Supply Pins……………............... ±60mA
Operating Temperature Range........–40°C to 125°C
±20mA
Maximum Junction Temperature................... 150°C
Output Current: OUT.................................... ±35mA
Storage Temperature Range.......... –65°C to 150°C
Output Short-Circuit Duration
Note 4….........
Indefinite
Lead Temperature (Soldering, 10 sec) ......... 260°C
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The op amp supplies must be established simultaneously, with, or before, the application of any input signals.
Note 3: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input
current should be limited to less than 10mA.
Note 4: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many
amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces
connected to the leads.
ESD, Electrostatic Discharge Protection
Symbol
Parameter
Condition
Minimum Level
Unit
HBM
Human Body Model ESD
MIL-STD-883H Method 3015.8
3
kV
CDM
Charged Device Model ESD
JEDEC-EIA/JESD22-C101E
2
kV
Thermal Resistance
2
Package Type
θJA
θJC
Unit
8-Pin SOIC
158
43
° C/W
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TP07
Precision RRO Operational Amplifier
Electrical Characteristics
The specifications are at TA = 27° C, VSUPPLY = ±15V, VCM = VOUT =0V, RL = 2kΩ, CL =100pF. Unless otherwise noted.
SYMBOL
VOS
VOS TC
IB
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
-100
+100
μV
Input Offset Voltage
VCM = VDD/2
Input Offset Voltage Drift
-40° C to 125° C
± 50
0.9
TA = 27 ° C
40
pA
TA = 85 ° C
550
pA
TA = 125 ° C
7.7
nA
0.001
pA
Input Bias Current
μV/° C
IOS
Input Offset Current
Vn
Input Voltage Noise
f = 0.1Hz to 10Hz
2.35
μVRMS
en
Input Voltage Noise Density
19
nV/√Hz
CIN
Input Capacitance
f = 1kHz
Differential
Common Mode
VCM = -5.6V to 4V
CMRR
PSRR
Common Mode Rejection Ratio
Common-mode Input Voltage
Range
Power Supply Rejection Ratio
AVOL
Open-Loop Large Signal Gain
RLOAD = 2kΩ
VOL, VOH
Output Swing from Supply Rail
RLOAD = 100kΩ
ROUT
Closed-Loop Output Impedance
RO
VCM
4
2.5
120
V– -0.3
pF
dB
V+-2.0
V
130
dB
118
dB
50
mV
G = 1, f =1kHz, IOUT = 0
0.01
Ω
Open-Loop Output Impedance
f = 1kHz, IOUT = 0
125
Ω
ISC
Output Short-Circuit Current
Sink or source current
35
mA
VDD
Supply Voltage
IQ
Quiescent Current per Amplifier
PM
Phase Margin
GM
GBWP
SR
FPBW
tS
Xtalk
100
2.7
36
V
2.2
mA
RLOAD = 2kΩ, CLOAD = 100pF
55
°
Gain Margin
RLOAD = 2kΩ, CLOAD = 100pF
8
dB
Gain-Bandwidth Product
f = 1kHz
AV = 1, VOUT = 0V to 10V, CLOAD = 100pF,
RLOAD = 2kΩ
1
MHz
6
V/μs
210
1
1
110
kHz
Slew Rate
Full Power Bandwidth Note 1
Settling Time, 0.1%
Settling Time, 0.01%
Channel Separation
AV = –1, 10V Step
f = 1kHz, RL = 2kΩ
μs
dB
Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P
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TP07
Precision RRO Operational Amplifier
Typical Performance Characteristics
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
Offset Voltage Production Distribution
Offset Voltage vs. Temperature
18
120
16
100
14
80
Offset Voltage (μV)
Population
12
10
8
6
60
40
20
4
0
2
-20
0
-40
-60
-40
-20
0
20
Offset Voltage(μV)
Input Voltage Noise Spectral Density
80
100
120
140
1E-08
Input Bias Current (A)
VDD=30V
RL=1kΩ
Noise (nV/√Hz)
60
Input Bias Current vs. Temperature
1k
100
10
1
0.1
1
10
100
1k
10k
100k
1M
1E-10
1E-12
1E-14
1E-16
1E-18
-50
Frequency (Hz)
0
50
Temperature (C)
100
Quiescent Current vs. Temperature
Supply Current (mA)
Common Mode Rejection Ratio
150
CMRR(dB)
40
Temperature (℃）
100
1.4
1.2
1
0.8
0.6
0.4
0.2
50
0
-15 -12
4
-9
-6 -3
0
3
6
9
Common Mode Voltage (V)
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12
15
-50
0
50
100
150
Temperatu
℃)
re (
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TP07
Typical Performance Characteristics
Precision RRO Operational Amplifier
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
Power-Supply Rejection Ratio vs. Temperature
CMRR vs. Temperature
122
CMRR(dB)
PSRR (dB)
124
120
118
116
-50
0
50
Temperature (C)
132
130
128
126
124
122
120
118
116
114
112
110
-50
100
50
Temperature (C)
100
CMRR vs. Frequency
3
140
2.5
120
100
CMRR(dB)
noise(uV/√Hz)
Voltage Noise Spectral Density vs. Frequency
0
2
1.5
1
80
60
40
0.5
20
0
0.1
10
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1k
100k
Frequency(Hz)
10M
0
0.1
10
1k
100k
10M
Frequency (Hz)
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TP07
Precision RRO Operational Amplifier
Pin Functions
V– or –VS: Negative Power Supply. It is normally tied to
ground. It can also be tied to a voltage other than
ground as long as the voltage between V+ and V– is from
2.7V to 36V. If it is not connected to ground, bypass it
with a capacitor of 0.1μF as close to the part as
possible.
-IN: Inverting Input of the Amplifier. Voltage range of this
pin can go from V– to (V+ - 2.0V).
+IN: Non-Inverting Input of Amplifier. This pin has the
same voltage range as –IN.
V+ or +VS: Positive Power Supply. Typically the voltage
is from 2.7V to 36V. Split supplies are possible as long
as the voltage between V+ and V– is between 2.7V and
36V. A bypass capacitor of 0.1μF as close to the part as
possible should be used between power supply pins or
between supply pins and ground.
OUT: Amplifier Output. The voltage range extends to
within milli-volts of each supply rail.
N/C: No connection.
Operation
The TP07 has input signal range from V– to (V+ – 2.0V). The output can extend all the way to the supply rails. The input
stage is comprised of a PMOS differential amplifier. The Class-AB control buffer and output bias stage uses a
proprietary compensation technique to take full advantage of the process technology to drive very high capacitive
loads. This is evident from the transient over shoot measurement plots in the Typical Performance Characteristics.
Applications Information
Driving Large Capacitive Load
The TP07 provides stable operation with load capacitance of up to 100 pF and ±10 V swings; larger capacitances
should be decoupled with a 50Ω decoupling resistor.
Stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals can degrade drift
performance. Therefore, best operation is obtained when both input contacts are maintained at the same temperature,
preferably close to the package temperature.
Cc
TP07
ei
820pF
Rc
750Ω
eo
TP07
eo
CL
5000pF
Cc
0.47µF
ei
R2
Rc
2 kΩ
10Ω
CL
5000pF
Driving Large Capacitive Loads
PCB Surface Leakage
In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be
considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity
conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow,
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TP07
Precision RRO Operational Amplifier
which is greater than the TP07 OPA’s input bias current at +27°C (±40pA, typical). It is recommended to use
multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface.
The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is
biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 2 for Inverting
Gain application.
1. For Non-Inverting Gain and Unity-Gain Buffer:
a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface.
b) Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the Common Mode input voltage.
2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors):
a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the
op-amp (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface.
Guard Ring
VIN+
VIN-
+VS
Figure 2 The Layout of Guard Ring
Ground Sensing and Rail to Rail Output
The TP07 family has excellent output drive capability. It drives 2k load directly with good THD performance. The
output stage is a rail-to-rail topology that is capable of swinging to within 50mV of either rail.
The maximum output current is a function of total supply voltage. As the supply voltage to the amplifier increases, the
output current capability also increases. Attention must be paid to keep the junction temperature of the IC below 150°C
when the output is in continuous short-circuit. The output of the amplifier has reverse-biased ESD diodes connected to
each supply. The output should not be forced more than 0.3V beyond either supply, otherwise current will flow through
these diodes.
Power Supply Layout and Bypass
The TP07 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01μF to 0.1μF)
within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger) within 100mm to
provide large, slow currents. This bulk capacitor can be shared with other analog parts.
Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs
and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external
components as close to the op amps’ pins as possible.
Proper Board Layout
To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid
leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances due to
output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected
as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the
amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling.
A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple
effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers
and types of components, where possible to match the number and type of thermocouple junctions. For example,
dummy components such as zero value resistors can be used to match real resistors in the opposite input path.
Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads
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TP07
Precision RRO Operational Amplifier
are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from
amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a
constant temperature across the circuit board.
R4
22kΩ
R1
R2
R3
2.7kΩ
22kΩ
10kΩ
VIN
C1
3000pF
C3
100pF
TP07
VO
C2
2000pF
fp 20kHz
Three-Pole Low-Pass Filter
8
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TP07
Precision RRO Operational Amplifier
Package Outline Dimensions
SO-8 (SOIC-8)
A2
C
θ
L1
A1
e
E
D
Symbol
E1
b
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Dimensions
Dimensions In
In Millimeters
Inches
Min
Max
Min
Max
A1
0.100
0.250
0.004
0.010
A2
1.350
1.550
0.053
0.061
b
0.330
0.510
0.013
0.020
C
0.190
0.250
0.007
0.010
D
4.780
5.000
0.188
0.197
E
3.800
4.000
0.150
0.157
E1
5.800
6.300
0.228
0.248
e
1.270 TYP
0.050 TYP
L1
0.400
1.270
0.016
0.050
θ
0°
8°
0°
8°
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