CLC5612IMX

CLC5612 Dual, High Output, Programmable Gain Buffer General Description The CLC5612 is a dual, low cost, high speed (90MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5612 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1.5mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear phase response up to one half of the −3dB frequency. The CLC5612 offers 0.1dB gain flatness to 18MHz and differential gain and phase errors of 0.15% and 0.02˚. These features are ideal for professional and consumer video applications. The CLC5612 offers superior dynamic performance with a 90MHz small signal bandwidth, 290V/µs slew rate and 6.2ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high speed performance make the CLC5612 well suited for many battery powered personal communication/computing systems. The ability to drive low impedance, highly capacitive loads, makes the CLC5612 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5612 will drive a 100Ω load with only −74/−86dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -70/-67dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high resolution A/D converters, the CLC5612 provides excellent −87/−93dBc second/third harmonic distortion (AV = +2, VOUT, f = 1MHz, RL = 1kΩ) and fast settling time. n n n n n n n n 0.15%, 0.02˚ differential gain, phase 1.5mA/ch supply current 90MHz bandwidth (AV = +2) −87/−93dBc HD2/HD3 (1MHz) 17ns settling to 0.05% 290V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V to ± 5V supplies Applications n n n n n n n Video line driver Coaxial cable driver Twisted pair driver Transformer/coil driver High capacitive load driver Portable/battery powered applications A/D driver Maximum Output Voltage vs. RL DS015001-1 Features n 130mA output current Connection Diagram DS015001-3 Pinout DIP & SOIC © 2001 National Semiconductor Corporation DS015001 www.national.com CLC5612 Dual, High Output, Programmable Gain Buffer January 2001 CLC5612 Typical Application DS015001-2 Differential Line Driver with Load Impedance Conversion Ordering Information Package Temperature Range Industrial 8-pin plastic DIP −40˚C to +85˚C CLC5612IN CLC5612IN N08E 8-pin plastic SOIC −40˚C to +85˚C CLC5612IM CLC5612IM M08A CLC5612IMX CLC5612IM www.national.com Part Number 2 Package Marking NSC Drawing Output Current (see (Note 4)) Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. ± 7V +14V Supply Voltage (VCC) Supply Voltage (VCC - VEE) 140mA VEE to VCC +150˚C −65˚C to +150˚C +300˚C +5 Electrical Characteristics (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE + (VS/2), RL tied to Vcm, unless specified) Symbol Parameter Ambient Temperature Conditions CLC5612IN/IM Typ Min/Max Ratings (Note 2) Units +25˚C +25˚C 0 to 70˚C −40 to 85˚C VO = 0.5VPP 75 50 50 50 MHz Frequency Domain Response -3dB Bandwidth VO = 2.0VPP 62 57 54 52 MHz −0.1dB Bandwidth VO = 0.5VPP 18 13 11 11 MHz Gain Peaking < 200MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP 0 0.5 0.9 1.2 dB 0.2 0.9 1.0 1.0 dB Gain Rolloff Linear Phase Deviation 0.1 0.4 0.5 0.5 deg Differential Gain NTSC, RL = 150Ω to −1V 0.09 – – – % Differential Phase NTSC, RL = 150Ω to −1V 0.14 – – – deg 2V Step 5.5 9.0 9.7 10.5 ns Settling Time to 0.05% 1V Step 20 28 45 70 ns Overshoot 2V Step 3 6.5 14 14 % Slew Rate 2V Step 185 150 130 120 V/µs dBc Time Domain Response Rise and Fall Time Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2VPP,1MHz −74 −70 −67 −67 2VPP,1MHz; RL = 1KΩ −79 −77 −72 −72 dBc 2VPP,5MHz −65 −58 −58 −58 dBc dBc 2VPP,1MHz −86 −82 −79 −79 2VPP,1MHz; RL = 1kΩ −81 −79 −76 −76 dBc 2VPP,5MHz −60 −55 −53 −53 dBc Voltage (eni) > 1MHz 3.4 4.4 4.9 4.9 nV/ Non-Inverting Current (ibn) > 1MHz 6.3 8.2 9.0 9.0 pA/ Inverting Current (ibi) > 1MHz 8.7 11.3 12.4 12.4 pA/ > 10MHz, 1VPP −80 - - - Equivalent Input Noise Crosstalk (Input Referred) dB Static, DC Performance Input Offset Voltage (Note 3) Average Drift Input Bias Current (Non-Inverting)(Note 3) Average Drift Gain Accuracy (Note 3) Internal Resistors (Rf, Rg) Power Supply Rejection Ratio DC 3 8 30 35 35 mV 80 - - - µV/˚C 3 14 18 18 µA 25 - - - nA/˚C ± 0.3 ± 1.5 ± 20% ± 2.0 ± 26% ± 2.0 ± 30% % 1000 48 45 43 43 dB Ω www.national.com CLC5612 Absolute Maximum Ratings (Note 1) CLC5612 +5 Electrical Characteristics (Continued) (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE + (VS/2), RL tied to Vcm, unless specified) Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Static, DC Performance Common Mode Rejection Ratio 47 45 43 43 dB 1.5 1.7 1.8 1.8 mA Input Resistance (Non-Inverting) 0.41 0.29 0.26 0.26 MΩ Input Capacitance (Non-Inverting) 2.2 3.3 3.3 3.3 pF Input Voltage Range, High 4.2 4.1 4.0 4.0 V Input Voltage Range, Low 0.8 0.9 1.0 1.0 V Supply Current (Per Amplifier) (Note 3) DC RL = ∞ Miscellaneous Performance Output Voltage Range, High RL = 100Ω 4.0 3.9 3.8 3.8 V Output Voltage Range, Low RL = 100Ω 1.0 1.1 1.2 1.2 V Output Voltage Range, High RL = ∞ 4.1 4.0 4.0 3.9 V Output Voltage Range, Low RL = ∞ 0.9 1.0 1.0 1.1 V Output Current Output Resistance, Closed loop DC 100 80 65 40 mA 400 600 600 600 mΩ Typ Min/Max Ratings (Note 2) ± 5V Electrical Characteristics (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Symbol Parameter Ambient Temperature Conditions CLC5612IN/IM Units +25˚C +25˚C 0 to 70˚C −40 to 85˚C VO = 1.0VPP 90 75 65 65 MHz VO = 4.0VPP 49 43 40 38 MHz −0.1dB Bandwidth VO = 1.0VPP 17 12 10 10 MHz Gain Peaking 0 0.5 0.9 1.0 dB 0.2 0.5 0.7 0.7 dB Linear Phase Deviation < 200MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP 0.2 0.4 0.5 0.5 deg Differential Gain NTSC, RL = 150Ω 0.15 0.4 – – % Differential Phase NTSC, RL =150Ω 0.02 0.06 – – deg Rise and Fall Time 2V Step 6.2 6.9 7.3 7.7 ns Settling Time to 0.05% 2V Step 17 19 35 55 ns Overshoot 2V Step 10 16 18 18 % Slew Rate 2V Step 290 250 220 200 V/µs 2VPP,1MHz −74 −70 −67 −67 dBc Frequency Domain Response -3dB Bandwidth Gain Rolloff Time Domain Response Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2VPP,1MHz; RL = 1KΩ −87 −80 −77 −77 dBc 2VPP,5MHz −67 −61 −59 −59 dBc 2VPP,1MHz −86 −82 −79 −79 dBc 2VPP,1MHz; RL = 1KΩ −93 −88 −85 −85 dBc 2VPP,5MHz −63 −59 −56 −56 dBc Equivalent Input Noise www.national.com 4 CLC5612 ± 5V Electrical Characteristics (Continued) (AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Symbol Parameter Conditions Typ Min/Max Ratings (Note 2) Units Distortion And Noise Response Voltage (eni) > 1MHz 3.4 4.4 4.9 4.9 nV/ Non-Inverting Current (ibn) > 1MHz 6.3 8.2 9.0 9.0 pA/ Inverting Current (ibi) > 1MHz 8.7 11.3 12.4 12.4 pA/ 10MHz, 1VPP −80 - - - dB 3 30 35 35 mV µV/˚C Crosstalk (Input Referred) Static, DC Performance Output Offset Voltage Average Drift Input Bias Current (Non-Inverting) Average Drift 80 - - - 5 12 16 17 µA 40 - - - nA/˚C ± 0.3 ± 2.0 ± 26% ± 2.0 ± 30% % 1000 ± 1.5 ± 20% Power Supply Rejection Ratio DC 48 45 43 43 dB Common Mode Rejection Ratio DC 48 46 44 44 dB Supply Current (Per Amplifier) RL = ∞ 1.6 1.9 2.0 2.0 mA Input Resistance (Non-Inverting) 0.52 0.38 0.34 0.34 MΩ Input Capacitance (Non-Inverting) 1.9 2.85 2.85 2.85 pF ± 4.2 ± 3.8 ± 4.0 ± 4.1 ± 3.6 ± 3.8 ± 4.1 ± 3.6 ± 3.8 ± 4.0 ± 3.5 ± 3.7 V 130 100 80 50 mA 400 600 600 600 mΩ Gain Accuracy Internal Resistors (Rf, Rg) Ω Miscellaneous Performance Common Mode Input Range Output Voltage Range RL = 100Ω Output Voltage Range RL = ∞ Output Current (Note 4) Output Resistance, Closed Loop DC V V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: The short circuit current can exceed the maximum safe output current Note 5: VS = VCC − VEE Typical Performance Characteristics (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) Frequency Response vs. RL Av = +1 Phase Av = -1 Vo = 0.5Vpp Magnitude (1dB/div) Gain 0 -90 Av = +2 -180 -270 RL = 1kΩ Gain Phase 0 -90 RL = 25Ω -180 RL = 100Ω -270 -360 -360 -450 1M 10M Phase (deg) Vo = 0.5Vpp Phase (deg) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response -450 100M 1M Frequency (Hz) 10M 100M Frequency (Hz) DS015001-5 DS015001-4 5 www.national.com (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) Gain Flatness & Linear Phase Frequency Response vs. Vo (AV = 2) 0.4 Gain 0.1 Phase 0 Vo = 0.1Vpp Magnitude (1dB/div) 0.2 Phase (deg) Magnitude (0.1dB/div) 0.3 -0.1 Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp -0.2 -0.3 10 0 20 1M 30 10M 100M Frequency (Hz) Frequency (MHz) DS015001-7 DS015001-6 Frequency Response vs. Vo (AV = −1) Frequency Response vs. Vo (Av = 1) Vo = 0.1Vpp Vo = 1Vpp Magnitude (1dB/div) Magnitude (1dB/div) Vo = 0.1Vpp Vo = 2Vpp Vo = 2.5Vpp 1M 10M 100M Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp 1M Frequency (Hz) 10M 100M Frequency (Hz) DS015001-8 PSRR & CMRR DS015001-9 Equivalent Input Noise 3.6 15 CMRR 50 PSRR 40 30 20 3.5 Inverting Current 10.8pA/√Hz 3.4 11 3.3 Non-Inverting Current 7.6pA/√Hz 3.2 7 Voltage 3.1nV/√Hz 3.1 Noise Current (pA/√Hz) Noise Voltage (nV/√Hz) 60 PSRR & CMRR (dB) CLC5612 Typical Performance Characteristics 10 3.0 3 10k 0 1k 10k 100k 1M 10M 100M 1M 10M Frequency (Hz) Frequency (Hz) DS015001-11 DS015001-10 www.national.com 100k 6 (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) 2nd & 3rd Harmonic Distortion 2nd & 3rd Harmonic Distortion, RL = 25Ω -50 Vo = 2Vpp -30 3rd RL = 1kΩ -40 Distortion (dBc) Distortion (dBc) -60 -70 2nd RL = 1kΩ -80 2nd RL = 100Ω -90 -50 2nd, 10MHz -60 3rd, 1MHz -70 3rd RL = 100Ω -100 3rd, 10MHz 2nd, 1MHz 1M -80 10M 0 Frequency (Hz) 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) DS015001-12 DS015001-13 2nd & 3rd Harmonic Distortion, RL = 100Ω 2nd & 3rd Harmonic Distortion, RL = 1kΩ -40 -50 Distortion (dBc) Distortion (dBc) 3rd, 10MHz -50 -60 2nd, 10MHz -70 2nd, 1MHz -80 -60 3rd, 10MHz -70 2nd, 10MHz -80 2nd, 1MHz -90 3rd, 1MHz 3rd, 1MHz -90 -100 0 0.5 1 1.5 2 2.5 0 Output Amplitude (Vpp) 0.5 1 1.5 2 DS015001-14 Large & Small Signal Pulse Response DS015001-15 Closed Loop Output Resistance 100 Large Signal VCC = ±5V Output Resistance (Ω) Output Voltage (0.02V/div) 2.5 Output Amplitude (Vpp) Small Signal Time (10ns/div) 10 1 0.1 0.01 DS015001-16 10k 100k 1M 10M 100M Frequency (Hz) DS015001-17 7 www.national.com CLC5612 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) IBN & VIO vs. Temperature Frequency Response -0.1 0.5 -0.2 VIO 0 -0.3 IBN -0.5 -0.4 -1 -0.5 -1.5 Vo = 1.0Vpp Av = +1 Av = -1 Gain Phase 0 -45 -90 -135 Av = +2 -180 -225 100M -0.6 -60 -40 -20 0 20 40 60 80 1M 100 Phase (deg) 1 Normalized Magnitude (1dB/div) 0 IBN (µA) Offset Voltage VIO (mV) 1.5 10M Frequency (Hz) Temperature (ϒC) DS015001-19 DS015001-18 Frequency Response vs. RL Gain Flatness & Linear Phase 0.2 RL = 1kΩ RL = 100Ω Phase 0 -90 -180 RL = 25Ω -270 0 Gain Magnitude (0.1dB/div) Gain -0.2 -0.4 Phase -0.6 -0.8 -1.0 -360 1M -450 100M 10M -1.2 0 5 Frequency (Hz) 10 15 20 Frequency Response vs. VO (Av 2) Frequency Response vs. VO (AV = 1) Vo = 1Vpp Magnitude (1dB/div) Magnitude (1dB/div) 30 DS015001-21 Vo = 0.1Vpp Vo = 1Vpp Vo = 5Vpp Vo = 2Vpp 10M Vo = 0.1Vpp Vo = 5Vpp Vo = 2Vpp 1M 100M 10M 100M Frequency (Hz) Frequency (Hz) DS015001-22 www.national.com 25 Frequency (MHz) DS015001-20 1M Phase (deg) Phase (deg) Vo = 1.0Vpp Magnitude (1dB/div) CLC5612 Typical Performance Characteristics DS015001-23 8 (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) Frequency Response vs. VO (AV = −1) Output Voltage (0.5V/div) Large & Small Signal Pulse Response Vo = 1Vpp Magnitude (1dB/div) Vo = 0.1Vpp Vo = 5Vpp Vo = 2Vpp Large Signal Small Signal Time (20ns/div) 1M 10M DS015001-25 100M Frequency (Hz) DS015001-24 Differential Gain & Phase 2nd & 3rd Harmonic Distortion vs. Frequency DS015001-26 DS015001-27 2nd & 3rd Harmonic Distortion vs. Frequency, RL = 25Ω -30 2nd & 3rd Harmonic Distortion vs. Frequency, RL = 100Ω -40 3rd, 10MHz -50 Distortion (dBc) Distortion (dBc) -40 -50 2nd, 10MHz -60 3rd, 1MHz -70 2nd, 1MHz 3rd, 10MHz -60 2nd, 10MHz -70 3rd, 1MHz -80 -80 0 1 2 3 4 2nd, 1MHz 5 -90 0 Output Amplitude (Vpp) 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) DS015001-28 DS015001-29 9 www.national.com CLC5612 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) 2nd & 3rd Harmonic Distortion vs. Frequency, RL = 1kΩ Short Term Settling Time 0.2 -50 -70 Vo (% Output Step) Distortion (dBc) 0.15 3rd, 10MHz -60 2nd, 10MHz -80 2nd, 1MHz -90 3rd, 1MHz -100 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -110 0 1 2 3 4 1 5 10 100 1000 10000 Time (ns) Output Amplitude (Vpp) DS015001-31 DS015001-30 Long Term Settling Time IBN & VOSvs. Temperature 0.2 0.15 Vo (% Output Step) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1µ 10µ 100µ 1m 100m 10m Time (s) DS015001-32 DS015001-33 Channel Matching Input Referred Crosstalk -20 Vo = 1Vpp Magnitude (dB) -40 Magnitude (0.5dB/div) CLC5612 Typical Performance Characteristics Channel 2 -60 -80 -100 Channel 1 -120 1M 1M 10M Frequency (Hz) 100M DS015001-35 DS015001-34 www.national.com 10M Frequency (Hz) 100M 10 (AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to VCM, unless specified) (Continued) Pulse Crosstalk Active Channel Amplitude (0.2V/div) Inactive Output Channel Inactive Channel Amplitude (20mV/div) Active Output Channel Time (10ns/div) DS015001-36 Application Division • Z(jω) is the CLC5612’s open loop transimpedance gain • Z(jω)/Rf is the loop gain The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the −3dB corner frequency in the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: • Decreases loop gain • Decreases bandwidth • Reduces gain peaking • Lowers pulse response overshoot • Affects frequency response phase linearity CLC5612 Design Information Closed Loop Gain Selection The CLC5612 is a current feedback op amp with Rf=Rg=1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and −1V/V by connecting pins 2 and 3 (or 5 and 6) as described in the chart below. CLC5612 Operation The CLC5612 is a current feedback buffer fabricated in an advanced complementary bipolar process. The CLC5612 operates from a single 5V supply or dual ± 5V supplies. Operating from a single 5V supply, the CLC5612 has the following features: • Gains of +1, −1, and 2V/V are achievable without external resistors • Provides 100mA of output current while consuming only 7.5mW of power • • Offers low −79/−81dBc 2nd and 3rd harmonic distortion Provides BW > 50MHz and 1MHz distortion < −75dBc at VO = 2VPP The CLC5612 performance is further enhanced in ± 5V supply applications as indicated in the ± 5V Electrical Characteristics table and ± 5V Typical Performance plots. If gains other than +1, −1, or +2V/V are required, then the CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Current Feedback Amplifiers Some of the key features of current feedback technology are: • Independence of AC bandwidth and voltage gain • Inherently stable at unity gain • Adjustable frequency response with feedback resistor • High slew rate • Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. Vo = Vin Input Connections Non-Inverting (pins 3,5) Inverting (pins 2,6) −1V/V ground input signal +1V/V input signal NC (open) +2V/V input signal ground The gain accuracy of the CLC5612 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of −2000ppm/˚C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. Single Supply Operation (Vcc = +5V/V, VEE =GND) Av Rf 1+ Z(jω ) The specifications given in the ± 5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. (1) where: • • Gain AV AV is the closed loop DC voltage gain Rf is the feedback resistor 11 www.national.com CLC5612 Typical Performance Characteristics Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5612 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. VCC For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following sections. DC Coupled Single Supply Operation 6.8µF Vo VCC Vin 1kΩ 1kΩ 2 3 R 1kΩ 4 1kΩ Rt 3 FIGURE 4. AC Coupled, AV = -1V/V Configuration 0.1µF The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC2 = 2.5V (For VCC = +5V). 7 6 1kΩ - Rb 4 5 + Vcm Vcm VCC CLC5612 6.8µF Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ. FIGURE 1. DC Coupled, AV = -1V/V Configuration Vo VCC VCC CC 1kΩ 1kΩ R 1kΩ 4 5 CLC5612 - 7 + Vcm Vin 3 1kΩ 1kΩ 6 - 2 1kΩ + R 7 1kΩ 1kΩ RL + 3 0.1µF 8 1 Vin + 0.1µF 8 1 2 6.8µF Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown. + Note: Channel 2 not shown. DS015001-39 Vo Vo = Vin + 2.5 Low frequency cutoff = R where Rin = 2 6 1 , 2πRinCC R >> R source DS015001-43 - 4 5 + Rt FIGURE 5. AC Coupled, AV = +1V/V Configuration CLC5612 Vcm VCC DS015001-40 6.8µF FIGURE 2. DC Coupled, AV = +1V/V Configuration + Note: Channel 2 not shown. Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown. 8 1 RL + Vin 0.1µF 2 1kΩ - 3 1kΩ 7 1kΩ 6 - 7 + 3 1kΩ 1kΩ 6 4 5 Vo = 2Vin + 2.5 Low frequency cutoff = R 2 1 , 2πRinCC R >> Rsource DS015001-44 5 FIGURE 6. AC Coupled, AV = +2V/V Configuration CLC5612 DS015001-41 FIGURE 3. DC Coupled, AV = +2V/V Configuration www.national.com 2 where Rin = - Vcm 4 + Rt 1kΩ 1kΩ CLC5612 + Vcm Vin R C R 1kΩ Vcm CC 0.1µF 8 1 - 6.8µF + Vo VCC VCC Vo 1 , 2πR gCC DS015001-42 - 1kΩ Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. + Vcm 6 5 + 8 2 1kΩ CLC5612 1kΩ Vin 7 6.8µF 1 RL + VCC Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown. 0.1µF 8 1 CC R Figure 1, Figure 2, and Figure 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC. Vo + Note: Channel 2 not shown. - CLC5612 AC Coupled Single Supply Operation Figure 4, Figure 5, and Figure 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. (Continued) + Application Division 12 CLC5612 Application Division (Continued) Dual Supply Operation The CLC5612 on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figure 7, Figure 8, and Figure 9. VCC 6.8µF + Vo 0.1µF 8 1 1kΩ Vin 1kΩ 2 - 7 + Rt 3 1kΩ 1kΩ 6 - Rb 4 5 + 0.1µF CLC5612 Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. Channel 2 not shown. + 6.8µF VEE DS015001-45 FIGURE 7. Dual Supply, AV = -1V/V Configuration VCC 6.8µF + Vo 8 1 0.1µF 1kΩ 1kΩ 2 - 7 + Vin 3 1kΩ 1kΩ 6 - Rt 4 5 + 0.1µF CLC5612 Note: Channel 2 not shown. + 6.8µF VEE DS015001-46 FIGURE 8. Dual Supply, AV = +1V/V Configuration 13 www.national.com • • (Continued) VCC 8 1 0.1µF 1kΩ 1kΩ - 7 + 3 1kΩ 1kΩ 6 - Rt 4 5 0.1µF R6 CLC5612 R4 Note: Channel 2 not shown. Z0 8 1 V1 +- 6.8µF R5 R1 VEE Z0 2 V2 +- 3 R3 R2 1kΩ - R7 7 + 4 DS015001-47 1kΩ 1kΩ 6 5 CLC5612 FIGURE 9. Dual Supply, AV = +2V/V Configuration Note: Channel 2 not shown. DS015001-49 Load Termination The CLC5612 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5612 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 10, gives the recommended series resistance value for optimum flatness at various capacitive loads. FIGURE 11. Transmission Line Matching Power Dissipation Follow these steps to determine the power consumption of the CLC5612: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC−VEE) 2. Calculate the RMS power at the output stage: P0 = (V CC-Vload)(Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp +Po The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12. The power derating curve for any CLC5612 package can be derived by utilizing the following equation: Vo = 1Vpp Magnitude (1dB/div) Vo C6 1kΩ + CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 17.4Ω where Tamb = Ambient temperature (˚C) CL = 1000pF Rs = 6.7Ω + θJA =Thermal resistance, from junction to ambient, for a given package (˚C/W) Rs - 1k CL 1k 1k 1M 10M 100M Frequency (Hz) DS015001-48 FIGURE 10. Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 11 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications: • Z0 - Vin + 2 Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics • Connect R3 directly to ground. • Make the resistors R4, R6, and R7 equal to Z0. • Make R5\Rg=Z0. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. + Vo Make R1, R2,R6 and R7 equal to Z0. Inverting gain applications: 6.8µF + CLC5612 Application Division DS015001-51 FIGURE 12. Power Derating Curve Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section. www.national.com 14 CLC5612 Application Division (Continued) Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5612 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: • Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. • Place the 6.8µF capacitors within 0.75 inches of the power pins. • Place the 0.1µF capacitors less than 0.1 inches from the power pins. • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. • • Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730038/CLC730036 evaluation boards. The evaluation board data sheets provide: DS015001-61 730036 Top +Vcc • Evaluation board schematics • Evaluation board layouts • General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC5612 To optimize off-isolation of the CLC5612, cut the Rf trace on both the CLC730038 and the CLC730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and the ouptut. Figure 13 shows where to cut both evaluation boards for improved off-isolation. + C3 ROUT2 + C4 -Vcc OUT1 OUT2 GND RG2 IN2 RF2 C1 C2 ROUT1 RF1 (970) 226-0500 RIN2 RG1 RIN1 IN1 Cut traces here DS015001-52 FIGURE 13. Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: • • Support Berkeley SPICE 2G and its many deriatives Reproduce typical DC, AC, Transient, and Noise performance • Support room temperature simulations The readme file that accompanies the diskette lists released models and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. 15 www.national.com (Continued) Rm/2 Application Circuits Single Supply Cable Driver Vd/2 Figure 14 below shows the CLC5612 driving 10m of 75Ω coaxial cable. The CLC5612 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. The response after 10m of cable is illustrated in Figure 15. - 7 -Vd/2 + Vin 3 1kΩ 1kΩ 6 4 5 Rt2 CLC5612 +5V 75Ω Rm/2 1kΩ 1kΩ RL - Vo Zo UTP 8 1 2 Rt 10m of 75Ω Coaxial Cable Io 1:n Req + 6.8µF Note: Supplies and bypassing not shown. + DS015001-55 0.1µF 75Ω +5V 8 1 5kΩ Vin 0.1µF 0.1µF FIGURE 16. Differential Line Driver with Load Impedance Conversionn 0.1µF 1kΩ 2 1kΩ - 7 Set up the CLC5612 as a difference amplifier. • Set the Channel 1 amplifier to a gain of +1V/V + 3 1kΩ 1kΩ 6 - 5kΩ 4 + • Set the Channel 2 amplifier to a gain of −1V/V Make the best use of the CLC5612’s output drive capability as follows: 5 CLC5612 NOTE: Channel 2 not shown DS015001-53 FIGURE 14. Single Supply Cable Driver Rm + Req = Vin = 10MHz, 0.5Vpp 2 ⋅ Vmax Imax where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic, impedance: 100mV/div CLC5612 Application Division RL = Z o Rm = Req n= 20ns/div RL Req Select the transformer so that it loads the line with a value very near Zo over frequency range. The output impedance of the CLC5612 also affects the match. With an ideal transformer we obtain: DS015001-54 FIGURE 15. Response After 10m of Cable Differential Line Driver with Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 16, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5612’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5612. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. Return Loss = −20 ⋅ log10 n2 ⋅ Z o(5612) ( jω ) ,dB Zo where Zo(5612)(jω) is the output impedance of the CLC5612 and |Zo(5612)(jω)|