CLC5602IMX

CLC5602 Dual, High Output, Video Amplifier June 1999 N CLC5602 Dual, High Output, Video Amplifier General Description The National CLC5602 has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1.5mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear-phase response up to one half of the -3dB frequency. The CLC5602 offers 0.1dB gain flatness to 22MHz and differential gain and phase errors of 0.06% and 0.02°. These features are ideal for professional and consumer video applications. The CLC5602 offers superior dynamic performance with a 135MHz small-signal bandwidth, 300V/µs slew rate and 5.7ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high-speed performance make the CLC5602 well suited for many battery-powered personal communication/computing systems. The ability to drive low-impedance, highly capacitive loads, makes the CLC5602 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5602 will drive a 100Ω load with only -86/-85dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -86/ -72dBc second/third harmonic distortion. The CLC5602 can also be used for driving differential-input stepup transformers for applications such as Asynchronous Digital Subscriber Lines (ADSL) or High-Bit-Rate Digital Subscriber Lines (HDSL). When driving the input of high-resolution A/D converters, the CLC5602 provides excellent -87/-95dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. Features s s s s s s s s s 130mA output current 0.06%, 0.02° differential gain, phase 1.5mA/ch supply current 135MHz bandwidth (Av = +2) -87/-95dBc HD2/HD3 (1MHz) 15ns settling to 0.05% 300V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V or ±5V supplies Video line driver ADSL/HDSL driver Coaxial cable driver UTP differential line driver Transformer/coil driver High capacitive load driver Portable/battery-powered applications Differential A/D driver Maximum Output Voltage vs. RL 10 9 Applications s s s s s s s s Output Voltage (Vpp) 8 7 6 5 4 3 2 1 10 100 1000 Vs = +5V VCC = ±5V RL (Ω) Typical Application Differential Line Driver with Load Impedance Conversion Rg2 Vin Rt1 Vd/2 + 1/2 CLC5602 Pinout DIP & SOIC Vo1 +VCC Vo2 Vinv2 Vnon-inv2 Rf2 1/2 CLC5602 Rf1 Rt2 -Vd/2 Rm/2 Req Rm/2 1:n Io Zo RL UTP Vinv1 + Vo - + Vnon-inv1 -VCC Rg1 © 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com +5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) CONDITIONS CLC5602IN/IM TYP +25°C 100 65 22 0 0.1 0.3 0.04 0.09 6.1 25 10 220 -77 -80 -63 -85 -82 -62 3.4 6.3 8.7 -72 1 7 5 25 3 10 48 49 1.5 0.46 1.8 4.2 0.8 4.0 1.0 4.1 0.9 100 55 MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C 85 60 20 0.5 0.3 0.5 – – 8.5 35 20 190 -74 -77 -59 -81 -79 -57 4.4 8.2 11.3 – 4 – 12 – 10 – 45 47 1.7 0.36 2.75 4.1 0.9 3.9 1.1 4.0 1.0 80 90 75 55 17 0.9 0.4 0.6 – – 9.2 50 22 165 -71 -75 -57 -78 -76 -54 4.9 9.0 12.4 – 5 15 15 60 12 20 43 45 1.8 0.32 2.75 4.1 0.9 3.9 1.1 4.0 1.0 65 90 70 50 15 1.0 0.5 0.6 – – 10.0 80 22 150 -71 -70 -57 -78 -76 -54 4.9 9.0 12.4 – 6 15 16 60 13 20 43 45 1.8 0.32 2.75 4.0 1.0 3.8 1.2 3.9 1.1 40 120 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 0.5Vpp Vo = 2.0Vpp -0.1dB bandwidth Vo = 0.5Vpp gain peaking 1MHz crosstalk (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current per channel DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC B Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) J-level: spec is 100% tested at +25°C. B) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE Absolute Maximum Ratings supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) +14V 140mA VEE to VCC +150°C -65°C to +150°C +300°C 1000V Reliability Information Transistor Count MTBF (based on limited test data) 98 290Mhr http://www.national.com 2 ±5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC5602IN/IM TYP +25°C 135 48 20 0 0.1 0.15 0.06 0.02 5.7 15 18 300 -86 -87 -70 -85 -95 -66 3.4 6.3 8.7 -72 2 8 5 40 8 20 48 51 1.6 0.59 1.45 ±4.2 ±3.8 ±4.0 130 40 GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C 115 45 18 0.5 0.3 0.3 0.18 0.04 6.2 25 20 225 -82 -83 -64 -81 -90 -64 4.4 8.2 11.3 – 6 – 12 – 24 – 45 49 1.9 0.47 2.15 ±4.1 ±3.6 ±3.8 100 70 105 42 15 0.9 0.4 0.4 – – 6.8 40 22 190 -79 -80 -61 -78 -87 -61 4.9 9.0 12.4 – 7 – 16 – 28 45 43 47 2.0 0.43 2.15 ±4.1 ±3.6 ±3.8 80 70 100 40 12 1.0 0.5 0.4 – – 7.3 60 22 175 -79 -80 -60 -78 -87 -60 4.9 9.0 12.4 – 8 – 17 – 28 45 43 47 2.0 0.43 2.15 ±4.0 ±3.5 ±3.7 50 90 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.0Vpp Vo = 4.0Vpp -0.1dB bandwidth Vo = 1.0Vpp gain peaking 1MHz crosstalk (input referred) 10MHz, 1Vpp STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current (per channel) DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC B Notes B) The short circuit current can exceed the maximum safe output current. Model CLC5602IN CLC5602IM CLC5602IMX Ordering Information Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C Description 8-pin PDIP 8-pin SOIC 8-pin SOIC tape & reel Package Thermal Resistance Package Plastic (IN) Surface Mount (IM) θJC 65°C/W 50°C/W θJA 130°C/W 145°C/W 3 http://www.national.com +5V Typical Performance (A Non-Inverting Frequency Response Normalized Magnitude (1dB/div) Vo = 0.5Vpp Gain Av = +1 Rf = 1.0kΩ Av = +2 Rf = 649Ω v = +2, Rf = 750Ω, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Phase (deg) Phase (deg) Vo = 0.5Vpp Gain Av = -2 Rf = 649Ω Av = -1 Rf = 649Ω Frequency Response vs. RL Phase (deg) Vo = 0.5Vpp RL = 1kΩ Magnitude (1dB/div) RL = 100Ω Gain Phase 0 -90 -180 -270 -360 -450 100M Phase 180 135 90 45 0 -45 100M Phase RL = 25Ω 0 -90 -180 -270 -360 -450 Av = +5 Rf = 301Ω Av = +10 Rf = 200Ω Av = -5 Rf = 649Ω Av = -10 Rf = 500Ω 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo Frequency (Hz) Gain Flatness & Linear Phase 0.5 140 120 Phase Gain Frequency (Hz) Open Loop Transimpedance Gain, Z(s) 225 180 0.4 Magnitude (1dB/div) Vo = 0.1Vpp Magnitude (0.05dB/div) Magnitude (dBΩ) 0.3 Phase (deg) Phase (deg) Gain 0.2 0.1 Vo = 1Vpp Vo = 2Vpp 100 80 60 40 1k 10k 100k 1M 10M 135 90 45 0 100M Phase 0 -0.1 -0.2 -0.3 1M 10M 100M 0 10 20 30 Frequency (Hz) PSRR & CMRR 60 3.6 PSRR CMRR Frequency (MHz) Equivalent Input Noise 12.5 -30 Vo = 2Vpp Frequency (Hz) 2nd & 3rd Harmonic Distortion -40 Noise Voltage (nV/√Hz) Noise Current (pA/√Hz) PSRR & CMRR (dB) 50 40 30 20 10 0 1k Distortion (dBc) 3.5 Inverting Current 8.7pA/√Hz 10 -50 -60 -70 -80 -90 2nd RL = 100Ω 2nd RL = 1kΩ 3rd RL = 1kΩ 3.4 Non-Inverting Current 7pA/√Hz Voltage 3.35nV/√Hz 7.5 3.3 5 3rd RL = 100Ω 3.2 10k 100k 1M 10M 100M 10k 100k 1M 10M 2.5 -100 1M 10M Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 25Ω -20 -30 3rd, 10MHz Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 100Ω -40 3rd, 10MHz Frequency (Hz) 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 3rd, 10MHz -50 -60 Distortion (dBc) Distortion (dBc) Distortion (dBc) -40 -50 2nd, 10MHz -60 -70 -80 -90 2nd, 10MHz 3rd, 1MHz 2nd, 10MHz -70 -80 2nd, 1MHz -60 -70 -80 2nd, 1MHz 3rd, 1MHz 2nd, 1MHz -90 3rd, 1MHz -90 0 0.5 1 1.5 2 2.5 -100 0 0.5 1 1.5 2 2.5 -100 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Large & Small Signal Pulse Response 100 Output Amplitude (Vpp) Closed Loop Output Resistance -1.5 VCC = ±5V Output Amplitude (Vpp) IBI, IBN, VIO vs. Temperature 3 VIO IBI Output Voltage (0.5V/div) 10 Offset Voltage VIO (mV) Large Signal Output Resistance (Ω) 1.0 0.5 0 -0.5 -1.0 -1.5 2 1 0 -1 -2 -3 IBI, IBN (µA) Small Signal 1 IBN 0.1 0.01 Time (10ns/div) 10k 100k 1M 10M 100M -60 -20 20 60 100 140 Frequency (Hz) Temperature (°C) http://www.national.com 4 ±5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 1.0Vpp Gain Av = +1 Rf = 1.0kΩ Av = +2 Rf = 649Ω v = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Phase (deg) Phase (deg) Vo = 1.0Vpp Gain Av = -1 Rf = 649Ω Av = -2 Rf = 649Ω Frequency Response vs. RL Phase (deg) Vo = 1.0Vpp Magnitude (1dB/div) Gain RL = 100Ω Phase RL = 1kΩ Phase 0 -45 -90 -135 -180 -225 100M Phase 180 135 90 45 0 -45 100M 0 -90 RL = 25Ω Av = +5 Rf = 301Ω Av = +10 Rf = 200Ω Av = -5 Rf = 649Ω Av = -10 Rf = 500Ω -180 -270 -360 -450 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo Vo = 5Vpp Frequency (Hz) Gain Flatness & Linear Phase 0.4 0.3 Gain Frequency (Hz) Small Signal Pulse Response Vo = 1Vpp Vo = 0.1Vpp 0.2 0.1 Phase Vo = 2Vpp 0 -0.1 Amplitude (200mV/div) Magnitude (0.1dB/div) Av = +2 Magnitude (1dB/div) Phase (deg) Av = -2 1M 10M 100M 0 5 10 15 20 25 30 Time (10ns/div) Frequency (Hz) Large Signal Pulse Response 0 Av = +2 Frequency (MHz) Differential Gain & Phase 0 -0.04 -30 Vo = 2Vpp 2nd & 3rd Harmonic Distortion vs. Frequency -40 -50 -60 -70 -80 -90 3rd RL = 1kΩ 2nd RL = 1kΩ 3rd RL = 100Ω 2nd RL = 100Ω Amplitude (0.5V/div) -0.04 Gain Pos Sync -0.08 -0.12 -0.16 Phase Pos Sync Phase Neg Sync -0.08 -0.12 -0.16 -0.2 Av = -2 -0.2 Time (20ns/div) 2nd & 3rd Harmonic Distortion, RL = 25Ω -30 -40 3rd, 10MHz 1 2 3 4 Distortion Level (dBc) Gain Neg Sync Phase (deg) Gain (%) -100 1 10 Number of 150 Ω Loads 2nd & 3rd Harmonic Distortion, RL = 100Ω -40 -50 3rd, 10MHz Frequency (MHz) 2nd & 3rd Harmonic Distortion, RL = 1kΩ -50 3rd, 10MHz -60 Distortion (dBc) Distortion (dBc) -50 -60 -70 -80 2nd, 1MHz 2nd, 10MHz 3rd, 1MHz -60 -70 -80 -90 2nd, 1MHz 2nd, 10MHz Distortion (dBc) 2nd, 10MHz -70 -80 -90 2nd, 1MHz 3rd, 1MHz 3rd, 1MHz -90 -100 0 1 2 3 4 5 -100 -110 0 0.5 1 1.5 -100 -110 2 2.5 0 1 2 3 4 5 Output Amplitude (Vpp) Short Term Settling Time 0.2 0.15 0.2 0.15 Output Amplitude (Vpp) Long Term Settling Time 1.4 Output Amplitude (Vpp) IBI, IBN, VOS vs. Temperature 3 2 IBI Offset Voltage VOS(mV) 1.3 1.2 1.1 VOS Vo (% Output Step) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1 10 100 1000 10000 Vo (% Output Step) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1µ 10µ 100µ 1m 10m 100m 1 0 -1 IBN IBI, IBN (µA) 1 0.9 0.8 -60 -20 20 60 100 140 -2 -3 Time (ns) Time (s) Temperature (°C) 5 http://www.national.com ±5V Typical Channel Matching Performance (A Channel Matching -20 Vo = 1Vpp v = +2, Rf = 750Ω, RL = 100Ω, VCC = ±5V, unless specified) Pulse Crosstalk Active Output Channel Input Referred Crosstalk -30 Magnitude (0.5dB/div) Inactive Channel Amplitude (20mV/div) Magnitude (dB) -40 -50 -60 -70 -80 -90 Active Channel Amplitude (0.2V/div) Channel 2 Inactive Output Channel Channel 1 1M 10M 100M 1M 10M 100M Time (10ns/div) Frequency (Hz) Frequency (Hz) CLC5602 OPERATION The CLC5602 is a current feedback amplifier built in an advanced complementary bipolar process. The CLC5602 operates from a single 5V supply or dual ±5V supplies. Operating from a single supply, the CLC5602 has the following features: s s s Vo = Vin where: s s s Av Rf 1+ Z(jω ) Equation 1 Provides 100mA of output current while consuming 7.5mW of power Offers low -80/-82dB 2nd and 3rd harmonic distortion Provides BW > 60MHz and 1MHz distortion < -65dBc at Vo = 2.0Vpp Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC5602’s open loop transimpedance gain Z( jω ) is the loop gain Rf s The CLC5602 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. Current Feedback Amplifiers Some of the key features of current feedback technology are: s Independence of AC bandwidth and voltage gain s Inherently stable at unity gain s Adjustable frequency response with feedback resistor s High slew rate s Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: s s s s s Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Refer to the Feedback Resistor Selection section for more details on selecting a feedback resistor value. CLC5602 DESIGN INFORMATION Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5602 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. http://www.national.com 6 DC Coupled Single Supply Operation Figures 1 and 2 show the recommended non-inverting and inverting configurations for input signals that remain above 0.8V DC. VCC Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. VCC 6.8µF + VCC 2 Vin Cc Rg R 3 2 6.8µF + 1/2 CLC5602 + 8 0.1µF 1 Vo - 4 Rf Vin Rt Vcm 3 2 1/2 CLC5602 + 8 0.1µF 1 R Vo RL Vcm  R Vo = Vin  − f  + 2.5  Rg  low frequency cutoff = 1 2πR gC c - 4 Rf Rg Vcm R Vo = A v = 1+ f Vin Rg Figure 4: AC Coupled Inverting Configuration Dual Supply Operation The CLC5602 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6. VCC 6.8µF + Figure 1: Non-Inverting Configuration VCC 6.8µF + Note: Rb, provides DC bias for non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. 3 Rb Vin Vcm Rt Vcm Rg 2 1/2 CLC5602 + 8 0.1µF 1 Vo RL Vcm Vin Rt 3 - 4 Rf 2 1/2 CLC5602 + 8 0.1µF 1 Vo - 4 Rf 0.1µF + Rg R Vo = Av = − f Vin Rg Select Rt to yield desired Rin = Rt || Rg R Vo = A v = 1+ f Vin Rg 6.8µF Figure 2: Inverting Configuration AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + 2 VEE Figure 5: Dual Supply Non-Inverting Configuration VCC 6.8µF + Rb 3 1/2 CLC5602 + 8 0.1µF 1 Vo Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt || Rg. Vin Rg - 4 Rf 0.1µF + Vin Cc VCC 2 R 3 R 2 1/2 CLC5602 + 8 0.1µF 1 Rt Vo R Vo = Av = − f Vin Rg VEE - 4 Rf 6.8µF  R Vo = Vin 1 + f  + 2.5 Rg   low frequency cutoff = Rg C 1 R , where: Rin = 2πRinC c 2 R >> R source Figure 6: Dual Supply Inverting Configuration Figure 3: AC Coupled Non-Inverting Configuration 7 http://www.national.com Feedback Resistor Selection The feedback resistor, Rf, affects the loop gain and frequency response of a current feedback amplifier. Optimum performance of the CLC5602, at a gain of +2V/V, is achieved with Rf equal to 750Ω. The frequency response plots in the Typical Performance sections illustrate the recommended Rf for several gains. These recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be adjusted to optimize the frequency response. s Figure 8 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications: s s s Connect Rg directly to ground. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. R1 Z0 R3 R2 R4 Z0 Rg R5 C6 1/2 CLC5602 s Decrease Rf to peak frequency response and extend bandwidth Increase Rf to roll off frequency response and compress bandwidth + - Z0 R6 V1 + - Vo R7 Rf As a rule of thumb, if the recommended Rf is doubled, then the bandwidth will be cut in half. Unity Gain Operation The recommended Rf for unity gain (+1V/V) operation is 1kΩ. Rg is left open. Parasitic capacitance at the inverting node may require a slight increase in Rf to maintain a flat frequency response. Load Termination The CLC5602 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5602 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 7, gives the recommended series resistance value for optimum flatness at various capacitive loads. V2 + - Figure 8: Transmission Line Matching Inverting gain applications: s s s Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Power Dissipation Follow these steps to determine the power consumption of the CLC5602: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP and SOIC packages can dissipate at a given temperature is illustrated in Figure 9. The power derating curve for any CLC5602 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA where Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) Vo = 1Vpp Magnitude (1dB/div) CL = 10pF Rs = 46.4Ω CL = 100pF Rs = 20Ω CL = 1000pF Rs = 6.7Ω + - Rs 1k CL 1k 1k 1M 10M 100M Frequency (Hz) Figure 7: Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. http://www.national.com 8 1.0 0.8 IM IN s s Power (W) 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 140 160 180 s Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Ambient Temperature (°C) Figure 9: Power Derating Curves Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5602 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s Application Circuits Single Supply Cable Driver The typical application shown below shows one of the CLC5602 amplifiers driving 10m of 75Ω coaxial cable. The CLC5602 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. +5V 6.8µF + s s s s s Evaluation Board Information A data sheet is available for the CLC730038/ CLC730036 evaluation boards. The evaluation board data sheet provides: s s s Evaluation board schematics Evaluation board layouts General information about the boards 100mV/div Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Vin 0.1µF 5kΩ 5kΩ 3 2 1/2 CLC5602 + 8 0.1µF 1 75Ω 0.1µF 10m of 75Ω Coaxial Cable Vo 75Ω - 4 1kΩ 1kΩ 0.1µF Figure 10: Single Supply Cable Driver Vin = 10MHz, 0.5Vpp 20ns/div The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: Figure 11: Response After 10m of Cable Single Supply Lowpass Filter Figures 12 and 13 illustrate a lowpass filter and design equations. The circuit operates from a single supply of +5V. The voltage divider biases the non-inverting input to 2.5V. And the input is AC coupled to prevent the need for level shifting the input signal at the source. Use the design equations to determine R1, R2, C1, and C2 based on the desired Q and corner frequency. 9 http://www.national.com +5V 0.1µF R2 C2 100pF 3 2 Vin 0.1µF 5kΩ R1 5kΩ 158Ω 158Ω + 8 C1 1 1/2 CLC5602 0.1µF Vo 100Ω - 4 Rf 1kΩ 1.698kΩ Rg 0.1µF Differential Line Driver With Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 15, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5602’s output capabilites. The single-ended input signal is converted to a differential signal by the CLC5602. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven. Rg2 Vin Rt1 Vd/2 + 1/2 CLC5602 Figure 12: Lowpass Filter Topology R Gain = K = 1 + f Rg Corner frequency = ω c = Q= 1 R 2C 2 + R1C1 R1C2 R1C1 + (1− K) R 2C1 R 2C 2 1 R1R 2C1C2 Rf2 1/2 CLC5602 Rf1 Rt2 -Vd/2 Rm/2 Req Rm/2 1:n Io Zo RL UTP + + Vo - Rg1 Figure 15: Differential Line Driver wtih Load Impedance Conversion Set up the CLC5602 as a difference amplifier:  Vd R R = 2 ⋅ 1 + f1  = 2 ⋅ f2 Vin R g1  R g2  Make the best use of the CLC5602’s output drive capability as follows: Rm + Req = 2 ⋅ Vmax Imax For R1 = R 2 = R and C1 = C2 = C ωc = Q= 1 RC 1 (3 − K) Figure 13: Design Equations This example illustrates a lowpass filter with Q = 0.707 and corner frequency fc = 10MHz. A Q of 0.707 was chosen to achieve a maximally flat, Butterworth response. Figure 14 indicates the filter response. where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic impedance: 3 RL = Z o Rm = Req n= RL Req Magnitude (dB) -3 -9 -15 -21 1M 10M 100M Select the transformer so that it loads the line with a value very near Zo over frequency range. The output impedance of the CLC5602 also affects the match. With an ideal transformer we obtain: Return Loss = −20 ⋅ log10 n2 ⋅ Z o(5602) ( jω ) ,dB Zo Frequency (Hz) Figure 14: Lowpass Response http://www.national.com 10 where Zo(5602)(jω) is the output impedance of the CLC5602 and |Zo(5602)(jω)|