CLC5612 Dual, High Output, Programmable Gain Buffer
January 2001
CLC5612 Dual, High Output, Programmable Gain Buffer
General Description
The CLC5612 is a dual, low cost, high speed (90MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5612 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1.5mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear phase response up to one half of the −3dB frequency. The CLC5612 offers 0.1dB gain flatness to 18MHz and differential gain and phase errors of 0.15% and 0.02˚. These features are ideal for professional and consumer video applications. The CLC5612 offers superior dynamic performance with a 90MHz small signal bandwidth, 290V/µs slew rate and 6.2ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high speed performance make the CLC5612 well suited for many battery powered personal communication/computing systems. The ability to drive low impedance, highly capacitive loads, makes the CLC5612 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5612 will drive a 100Ω load with only −74/−86dBc second/third harmonic distortion (AV = +2, VOUT = 2VPP, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -70/-67dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high resolution A/D converters, the CLC5612 provides excellent −87/−93dBc second/third harmonic distortion (AV = +2, VOUT, f = 1MHz, RL = 1kΩ) and fast settling time. n n n n n n n n 0.15%, 0.02˚ differential gain, phase 1.5mA/ch supply current 90MHz bandwidth (AV = +2) −87/−93dBc HD2/HD3 (1MHz) 17ns settling to 0.05% 290V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V to ± 5V supplies
Applications
n n n n n n n Video line driver Coaxial cable driver Twisted pair driver Transformer/coil driver High capacitive load driver Portable/battery powered applications A/D driver Maximum Output Voltage vs. RL
DS015001-1
Features
n 130mA output current
Connection Diagram
DS015001-3
Pinout DIP & SOIC
© 2001 National Semiconductor Corporation
DS015001
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CLC5612
Typical Application
DS015001-2
Differential Line Driver with Load Impedance Conversion
Ordering Information
Package 8-pin plastic DIP 8-pin plastic SOIC Temperature Range Industrial −40˚C to +85˚C −40˚C to +85˚C Part Number CLC5612IN CLC5612IM CLC5612IMX Package Marking CLC5612IN CLC5612IM CLC5612IM NSC Drawing N08E M08A
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CLC5612
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC - VEE)
± 7V +14V
Output Current (see (Note 4)) Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec)
140mA VEE to VCC +150˚C −65˚C to +150˚C +300˚C
+5 Electrical Characteristics
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE + (VS/2), RL tied to Vcm, unless specified) Symbol Ambient Temperature Frequency Domain Response -3dB Bandwidth −0.1dB Bandwidth Gain Peaking Gain Rolloff Linear Phase Deviation Differential Gain Differential Phase Time Domain Response Rise and Fall Time Settling Time to 0.05% Overshoot Slew Rate Distortion And Noise Response 2nd Harmonic Distortion 2VPP,1MHz 2VPP,1MHz; RL = 1KΩ 2VPP,5MHz 3rd Harmonic Distortion 2VPP,1MHz 2VPP,1MHz; RL = 1kΩ 2VPP,5MHz Equivalent Input Noise Voltage (eni) Non-Inverting Current (ibn) Inverting Current (ibi) Crosstalk (Input Referred) Static, DC Performance Input Offset Voltage (Note 3) Average Drift Input Bias Current (Non-Inverting)(Note 3) Average Drift Gain Accuracy (Note 3) Internal Resistors (Rf, Rg) Power Supply Rejection Ratio DC 8 80 3 25 30 14 35 18 35 18 mV µV/˚C µA nA/˚C % Ω dB −74 −79 −65 −86 −81 −60 3.4 6.3 8.7 −80 −70 −77 −58 −82 −79 −55 4.4 8.2 11.3 −67 −72 −58 −79 −76 −53 4.9 9.0 12.4 −67 −72 −58 −79 −76 −53 4.9 9.0 12.4 dBc dBc dBc dBc dBc dBc nV/ pA/ pA/ dB 2V Step 1V Step 2V Step 2V Step 5.5 20 3 185 9.0 28 6.5 150 9.7 45 14 130 10.5 70 14 120 ns ns % V/µs VO = 0.5VPP VO = 2.0VPP VO = 0.5VPP 75 62 18 0 0.2 0.1 0.09 0.14 50 57 13 0.5 0.9 0.4 – – 50 54 11 0.9 1.0 0.5 – – 50 52 11 1.2 1.0 0.5 – – MHz MHz MHz dB dB deg % deg Parameter Conditions CLC5612IN/IM Typ +25˚C Min/Max Ratings (Note 2) +25˚C 0 to 70˚C −40 to 85˚C Units
< 200MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP < 30MHz, VO = 0.5VPP
NTSC, RL = 150Ω to −1V NTSC, RL = 150Ω to −1V
> 1MHz > 1MHz > 1MHz > 10MHz, 1VPP
± 0.3
1000 48
± 1.5 ± 20%
45
± 2.0 ± 26%
43
± 2.0 ± 30%
43
3
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CLC5612
+5 Electrical Characteristics
Symbol Parameter
(Continued)
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE + (VS/2), RL tied to Vcm, unless specified) Conditions Typ Min/Max Ratings (Note 2) 45 1.7 43 1.8 43 1.8 Units
Static, DC Performance Common Mode Rejection Ratio Supply Current (Per Amplifier) (Note 3) Miscellaneous Performance Input Resistance (Non-Inverting) Input Capacitance (Non-Inverting) Input Voltage Range, High Input Voltage Range, Low Output Voltage Range, High Output Voltage Range, Low Output Voltage Range, High Output Voltage Range, Low Output Current Output Resistance, Closed loop DC RL = 100Ω RL = 100Ω RL = ∞ RL = ∞ 0.41 2.2 4.2 0.8 4.0 1.0 4.1 0.9 100 400 0.29 3.3 4.1 0.9 3.9 1.1 4.0 1.0 80 600 0.26 3.3 4.0 1.0 3.8 1.2 4.0 1.0 65 600 0.26 3.3 4.0 1.0 3.8 1.2 3.9 1.1 40 600 MΩ pF V V V V V V mA mΩ DC RL = ∞ 47 1.5 dB mA
± 5V Electrical Characteristics
(AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Symbol Ambient Temperature Frequency Domain Response -3dB Bandwidth −0.1dB Bandwidth Gain Peaking Gain Rolloff Linear Phase Deviation Differential Gain Differential Phase Time Domain Response Rise and Fall Time Settling Time to 0.05% Overshoot Slew Rate Distortion And Noise Response 2nd Harmonic Distortion 2VPP,1MHz 2VPP,1MHz; RL = 1KΩ 2VPP,5MHz 3rd Harmonic Distortion 2VPP,1MHz 2VPP,1MHz; RL = 1KΩ 2VPP,5MHz Equivalent Input Noise −74 −87 −67 −86 −93 −63 −70 −80 −61 −82 −88 −59 −67 −77 −59 −79 −85 −56 −67 −77 −59 −79 −85 −56 dBc dBc dBc dBc dBc dBc 2V Step 2V Step 2V Step 2V Step 6.2 17 10 290 6.9 19 16 250 7.3 35 18 220 7.7 55 18 200 ns ns % V/µs VO = 1.0VPP VO = 4.0VPP VO = 1.0VPP 90 49 17 0 0.2 0.2 0.15 0.02 75 43 12 0.5 0.5 0.4 0.4 0.06 65 40 10 0.9 0.7 0.5 – – 65 38 10 1.0 0.7 0.5 – – MHz MHz MHz dB dB deg % deg Parameter Conditions CLC5612IN/IM Typ +25˚C Min/Max Ratings (Note 2) +25˚C 0 to 70˚C −40 to 85˚C Units
< 200MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP < 30MHz, VO = 1.0VPP
NTSC, RL = 150Ω NTSC, RL =150Ω
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CLC5612
± 5V Electrical Characteristics
Symbol Parameter Voltage (eni) Non-Inverting Current (ibn) Inverting Current (ibi) Crosstalk (Input Referred) Static, DC Performance Output Offset Voltage Average Drift Input Bias Current (Non-Inverting) Average Drift Gain Accuracy Internal Resistors (Rf, Rg) Power Supply Rejection Ratio Common Mode Rejection Ratio Supply Current (Per Amplifier) Miscellaneous Performance Input Resistance (Non-Inverting) Input Capacitance (Non-Inverting) Common Mode Input Range Output Voltage Range Output Voltage Range Output Current (Note 4) Output Resistance, Closed Loop Distortion And Noise Response
(Continued)
(AV = +2, RL = 100Ω, VCC = ± 5V, unless specified) Conditions Typ 3.4 6.3 8.7 −80 3 80 5 40 Min/Max Ratings (Note 2) 4.4 8.2 11.3 30 12 4.9 9.0 12.4 35 16 4.9 9.0 12.4 35 17 Units nV/ pA/ pA/ dB mV µV/˚C µA nA/˚C % Ω dB dB mA MΩ pF V V V mA mΩ
> 1MHz > 1MHz > 1MHz
10MHz, 1VPP
± 0.3
1000 DC DC RL = ∞ 48 48 1.6 0.52 1.9 RL = 100Ω RL = ∞ DC
± 1.5 ± 20%
45 46 1.9 0.38 2.85
± 2.0 ± 26%
43 44 2.0 0.34 2.85
± 2.0 ± 30%
43 44 2.0 0.34 2.85
± 4.2 ± 3.8 ± 4.0
130 400
± 4.1 ± 3.6 ± 3.8
100 600
± 4.1 ± 3.6 ± 3.8
80 600
± 4.0 ± 3.5 ± 3.7
50 600
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Note 4: The short circuit current can exceed the maximum safe output current Note 5: VS = VCC − VEE
Typical Performance Characteristics
VCM, unless specified)
Non-Inverting Frequency Response Normalized Magnitude (1dB/div)
Vo = 0.5Vpp Gain Av = -1 Av = +1
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Frequency Response vs. RL
Phase (deg) Phase (deg)
Vo = 0.5Vpp
Magnitude (1dB/div)
Gain
RL = 1kΩ
Phase
0
Av = +2
Phase RL = 25Ω RL = 100Ω
0 -90 -180 -270 -360 -450
-90 -180 -270 -360 -450
1M
10M
100M
DS015001-4
1M
10M
100M
DS015001-5
Frequency (Hz)
Frequency (Hz)
5
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) Gain Flatness & Linear Phase
0.4
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Frequency Response vs. Vo (AV = 2)
Magnitude (0.1dB/div)
0.3 0.2
Gain
Magnitude (1dB/div)
Vo = 0.1Vpp Vo = 1Vpp Vo = 2Vpp Vo = 2.5Vpp
Phase (deg)
0.1
Phase
0 -0.1 -0.2 -0.3
0
10
20
30
DS015001-6
1M
10M
100M
DS015001-7
Frequency (MHz)
Frequency (Hz)
Frequency Response vs. Vo (Av = 1)
Vo = 0.1Vpp Vo = 1Vpp
Frequency Response vs. Vo (AV = −1)
Magnitude (1dB/div)
Vo = 0.1Vpp
Vo = 1Vpp
Vo = 2Vpp
Magnitude (1dB/div)
Vo = 2Vpp Vo = 2.5Vpp
Vo = 2.5Vpp
1M
10M
100M
DS015001-8
1M
10M
100M
DS015001-9
Frequency (Hz)
Frequency (Hz)
PSRR & CMRR
60
Equivalent Input Noise
3.6 15
Noise Voltage (nV/√Hz)
PSRR & CMRR (dB)
50 40 30 20 10
CMRR PSRR
3.5 3.4 3.3 3.2
Voltage 3.1nV/√Hz Inverting Current 10.8pA/√Hz
Noise Current (pA/√Hz)
11
Non-Inverting Current 7.6pA/√Hz
7
3.1 3.0 3 10k 100k 1M 10M
0 1k 10k 100k 1M 10M 100M
DS015001-10
Frequency (Hz)
DS015001-11
Frequency (Hz)
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) 2nd & 3rd Harmonic Distortion
-50
Vo = 2Vpp
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
2nd & 3rd Harmonic Distortion, RL = 25Ω
-30
-60
3rd RL = 1kΩ
Distortion (dBc)
-40 -70 -80 -90
2nd RL = 1kΩ 2nd RL = 100Ω
3rd, 10MHz
Distortion (dBc)
-50
2nd, 10MHz
-60
3rd, 1MHz
-100 1M
3rd RL = 100Ω
-70
2nd, 1MHz
10M
-80 0 0.5 1 1.5 2 2.5
DS015001-13
Frequency (Hz)
DS015001-12
Output Amplitude (Vpp)
2nd & 3rd Harmonic Distortion, RL = 100Ω
-40 -50
3rd, 10MHz
2nd & 3rd Harmonic Distortion, RL = 1kΩ
-50 -60
3rd, 10MHz
Distortion (dBc)
-60
2nd, 10MHz
Distortion (dBc)
-70 -80 -90
2nd, 10MHz 2nd, 1MHz
-70 -80 -90 0 0.5 1 1.5 2 2.5
DS015001-14
2nd, 1MHz
3rd, 1MHz
3rd, 1MHz
-100 0 0.5 1 1.5 2 2.5
DS015001-15
Output Amplitude (Vpp)
Output Amplitude (Vpp)
Large & Small Signal Pulse Response
Output Voltage (0.02V/div)
Closed Loop Output Resistance
100
VCC = ±5V
Large Signal
Small Signal
Output Resistance (Ω)
DS015001-16
10
1
0.1
Time (10ns/div)
0.01 10k 100k 1M 10M 100M
Frequency (Hz)
DS015001-17
7
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) IBN & VIO vs. Temperature
1.5 0 -0.1 -0.2
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Frequency Response
Normalized Magnitude (1dB/div) Phase (deg)
Vo = 1.0Vpp Gain
Offset Voltage VIO (mV)
1 0.5
VIO
Av = -1
Av = +1
IBN (µA)
Phase
0 -0.5 -1 -1.5 -60 -40 -20 0 20 40 60 80 100
IBN
-0.3 -0.4 -0.5 -0.6
0 -45 -90 -135
Av = +2
-180 -225 100M
DS015001-19
1M
10M
Temperature (ϒ C)
DS015001-18
Frequency (Hz)
Frequency Response vs. RL
Phase (deg)
Vo = 1.0Vpp
Gain Flatness & Linear Phase
0.2
Gain RL = 1kΩ RL = 100Ω Phase
Magnitude (0.1dB/div)
Magnitude (1dB/div)
Gain
0 -0.2
Phase (deg)
0 -90
RL = 25Ω
Phase
-0.4 -0.6 -0.8 -1.0 -1.2
-180 -270 -360 -450 100M
DS015001-20
1M
10M
0
5
10
15
20
25
30
DS015001-21
Frequency (Hz)
Frequency (MHz)
Frequency Response vs. VO (Av 2)
Frequency Response vs. VO (AV = 1)
Vo = 1Vpp Vo = 0.1Vpp
Vo = 0.1Vpp
Magnitude (1dB/div)
Vo = 1Vpp
Magnitude (1dB/div)
Vo = 5Vpp
Vo = 5Vpp
Vo = 2Vpp
Vo = 2Vpp
1M
10M
100M
DS015001-22
1M
10M
100M
DS015001-23
Frequency (Hz)
Frequency (Hz)
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) Frequency Response vs. VO (AV = −1)
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Large & Small Signal Pulse Response
Output Voltage (0.5V/div)
Large Signal
Vo = 1Vpp
Magnitude (1dB/div)
Vo = 0.1Vpp
Vo = 5Vpp
Small Signal
Vo = 2Vpp
Time (20ns/div)
1M 10M 100M
DS015001-24 DS015001-25
Frequency (Hz)
Differential Gain & Phase
2nd & 3rd Harmonic Distortion vs. Frequency
DS015001-26 DS015001-27
2nd & 3rd Harmonic Distortion vs. Frequency, RL = 25Ω
-30 -40
2nd & 3rd Harmonic Distortion vs. Frequency, RL = 100Ω
-40
Distortion (dBc)
3rd, 10MHz
-50
3rd, 10MHz
-50
2nd, 10MHz
Distortion (dBc)
-60
2nd, 10MHz
-60
3rd, 1MHz
-70 -80
3rd, 1MHz
-70
2nd, 1MHz
-80 0 1 2 3 4 5
DS015001-28
2nd, 1MHz
-90 0 0.5 1 1.5 2 2.5
DS015001-29
Output Amplitude (Vpp)
Output Amplitude (Vpp)
9
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) 2nd & 3rd Harmonic Distortion vs. Frequency, RL = 1kΩ
-50 -60
3rd, 10MHz
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Short Term Settling Time
0.2 0.15
Vo (% Output Step)
Distortion (dBc)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2
-70 -80
2nd, 10MHz
2nd, 1MHz
-90
3rd, 1MHz
-100 -110 0 1 2 3 4 5
DS015001-30
1
10
100
1000
10000
DS015001-31
Output Amplitude (Vpp)
Time (ns)
Long Term Settling Time
0.2 0.15
IBN & VOSvs. Temperature
Vo (% Output Step)
0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 1µ 10µ 100µ 1m 10m 100m
DS015001-32
Time (s)
DS015001-33
Channel Matching
Input Referred Crosstalk
-20
Vo = 1Vpp
-40
Magnitude (0.5dB/div)
Channel 2
Magnitude (dB)
-60 -80
Channel 1
-100 -120 1M 10M 100M
DS015001-35 DS015001-34
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
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CLC5612
Typical Performance Characteristics
VCM, unless specified) (Continued) Pulse Crosstalk
Active Output Channel
(AV = +2, RL = 100Ω, VS +5V1, VCM = VEE+(VS/2), RL tied to
Inactive Channel Amplitude (20mV/div)
Active Channel Amplitude (0.2V/div)
Inactive Output Channel
Time (10ns/div)
DS015001-36
Application Division
CLC5612 Operation The CLC5612 is a current feedback buffer fabricated in an advanced complementary bipolar process. The CLC5612 operates from a single 5V supply or dual ± 5V supplies. Operating from a single 5V supply, the CLC5612 has the following features:
• • • •
Gains of +1, −1, and 2V/V are achievable without external resistors Provides 100mA of output current while consuming only 7.5mW of power Offers low −79/−81dBc 2nd and 3rd harmonic distortion Provides BW > 50MHz and 1MHz distortion < −75dBc at VO = 2VPP
The CLC5612 performance is further enhanced in ± 5V supply applications as indicated in the ± 5V Electrical Characteristics table and ± 5V Typical Performance plots. If gains other than +1, −1, or +2V/V are required, then the CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Current Feedback Amplifiers Some of the key features of current feedback technology are:
• Z(jω) is the CLC5612’s open loop transimpedance gain • Z(jω)/Rf is the loop gain The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the −3dB corner frequency in the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: • Decreases loop gain • Decreases bandwidth • Reduces gain peaking • Lowers pulse response overshoot • Affects frequency response phase linearity CLC5612 Design Information Closed Loop Gain Selection The CLC5612 is a current feedback op amp with Rf=Rg=1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and −1V/V by connecting pins 2 and 3 (or 5 and 6) as described in the chart below.
Gain AV −1V/V +1V/V +2V/V Input Connections Non-Inverting (pins 3,5) ground input signal input signal Inverting (pins 2,6) input signal NC (open) ground
• Independence of AC bandwidth and voltage gain • Inherently stable at unity gain • Adjustable frequency response with feedback resistor • High slew rate • Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1.
Vo = Vin
Av Rf 1+ Z(jω )
(1)
The gain accuracy of the CLC5612 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of −2000ppm/˚C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. Single Supply Operation (Vcc = +5V/V, VEE =GND) The specifications given in the ± 5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified.
where:
• •
AV is the closed loop DC voltage gain Rf is the feedback resistor
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CLC5612
Application Division
(Continued)
Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5612 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following sections. DC Coupled Single Supply Operation
AC Coupled Single Supply Operation Figure 4, Figure 5, and Figure 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC.
VCC 6.8µF
Note: Channel 2 not shown.
+
Vo VCC R Vin CC
1 2 3
1kΩ
1kΩ
-
8 7
1kΩ
0.1µF
R
VCC
Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown.
CLC5612
6.8µF
+
Vo RL
1 Vin Rt Rb Vcm Vcm 2 3 4
1kΩ
1kΩ
-
8 7
1kΩ
0.1µF
FIGURE 4. AC Coupled, AV = -1V/V Configuration The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC2 = 2.5V (For VCC = +5V).
VCC 6.8µF
Note: Channel 2 not shown.
Vcm
1kΩ
+ -
6 5
CLC5612
Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.
DS015001-39
FIGURE 1. DC Coupled, AV = -1V/V Configuration
VCC 6.8µF
Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown.
Vo VCC Vin CC R
1 2 3
1kΩ
+
1kΩ
+ -
Vo RL Vcm Vin Rt Vcm
1 2 3 4
1kΩ
1kΩ
-
8 7
1kΩ
0.1µF
R
4
CLC5612
1kΩ
+ -
6 5
FIGURE 5. AC Coupled, AV = +1V/V Configuration
DS015001-40
CLC5612
VCC 6.8µF
Note: Channel 2 not shown.
FIGURE 2. DC Coupled, AV = +1V/V Configuration
VCC 6.8µF
Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. Channel 2 not shown.
Vo VCC Vin CC RC R
1 2 3 4
1kΩ
+
RL Vcm Vin
3 Rt Vcm 4
1kΩ
+ -
CLC5612
DS015001-41
FIGURE 3. DC Coupled, AV = +2V/V Configuration
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+
-
Vcm
2
1kΩ
1kΩ
7
1kΩ
CLC5612
6 5
FIGURE 6. AC Coupled, AV = +2V/V Configuration
+
1
8
-
Vo
0.1µF
1kΩ
+
-
+
-
+
4
-
Figure 1, Figure 2, and Figure 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC.
1kΩ
+
6 5
Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. 1 , 2πR gCC
DS015001-42
+
+
1kΩ
8 7
1kΩ
0.1µF
6 5
Vo = Vin + 2.5 Low frequency cutoff = R where Rin = 2 1 , 2πRinCC R >> R source
DS015001-43
+
+
1kΩ
8 7
1kΩ
0.1µF
6 5
Vo = 2Vin + 2.5 Low frequency cutoff = where Rin = R 2 1 , 2πRinCC R >> Rsource
DS015001-44
CLC5612
Application Division
Dual Supply Operation
(Continued)
The CLC5612 on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figure 7, Figure 8, and Figure 9.
VCC 6.8µF
+
Vo Vin Rt Rb
1 2 3 4 0.1µF
+
1kΩ
1kΩ
-
8 7
1kΩ
0.1µF
1kΩ
+ -
CLC5612
Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. Channel 2 not shown.
6.8µF VEE
FIGURE 7. Dual Supply, AV = -1V/V Configuration
Vo
1 2
1kΩ
1kΩ
-
Vin Rt
3 4 0.1µF
+
1kΩ
+ -
CLC5612
Note: Channel 2 not shown.
6.8µF VEE
DS015001-46
FIGURE 8. Dual Supply, AV = +1V/V Configuration
13
+
6 5
DS015001-45
VCC 6.8µF
+
8 7
1kΩ
0.1µF
+
6 5
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CLC5612
Application Division
(Continued)
• •
6.8µF
+
Make R1, R2,R6 and R7 equal to Z0. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics
VCC
Inverting gain applications:
Vo
1 2
1kΩ
1kΩ
-
8 7
1kΩ
0.1µF
Vin Rt
3 4 0.1µF
+
1kΩ
+ -
6 5
• Connect R3 directly to ground. • Make the resistors R4, R6, and R7 equal to Z0. • Make R5\Rg=Z0. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency.
R6 Z0 Vo R7
CLC5612
Note: Channel 2 not shown.
6.8µF VEE
DS015001-47
V2 + -
R2
CLC5612
Note: Channel 2 not shown.
FIGURE 9. Dual Supply, AV = +2V/V Configuration Load Termination The CLC5612 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5612 will improve stability and settling performance. The Frequency Response vs. CL plot, shown below in Figure 10, gives the recommended series resistance value for optimum flatness at various capacitive loads.
FIGURE 11. Transmission Line Matching Power Dissipation Follow these steps to determine the power consumption of the CLC5612: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC−VEE) 2. Calculate the RMS power at the output stage: P0 = (V CC-Vload)(Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp +Po The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12. The power derating curve for any CLC5612 package can be derived by utilizing the following equation:
Vo = 1Vpp
Magnitude (1dB/div)
CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 17.4Ω CL = 1000pF Rs = 6.7Ω
+ -
where Tamb = Ambient temperature (˚C) θJA =Thermal resistance, from junction to ambient, for a given package (˚C/W)
Rs 1k CL 1k
1k
1M
10M
100M
DS015001-48
Frequency (Hz)
FIGURE 10. Frequency Response vs. CL Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 11 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications:
FIGURE 12. Power Derating Curve
•
Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section.
14
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+
4
-
R1
Z0
3 R3
1kΩ
+
R5
-
+
R4 V1 + -
Z0
1 2
1kΩ
1kΩ
8 7
1kΩ
C6
6 5
DS015001-49
DS015001-51
CLC5612
Application Division
Layout Considerations
(Continued)
A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC5612 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout:
• • • •
Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances.
DS015001-61
Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information A data sheet is available for the CLC730038/CLC730036 evaluation boards. The evaluation board data sheets provide:
• •
730036 Top
• Evaluation board schematics • Evaluation board layouts • General information about the boards The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC5612 To optimize off-isolation of the CLC5612, cut the Rf trace on both the CLC730038 and the CLC730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and the ouptut. Figure 13 shows where to cut both evaluation boards for improved off-isolation.
+Vcc
OUT2
ROUT2 RF2
+
C4
C3
+
-Vcc
C1 C2 ROUT1
GND RG2 IN2
OUT1
RIN2 RG1 RIN1
RF1
(970) 226-0500
IN1
Cut traces here
DS015001-52
FIGURE 13. Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that:
• •
Support Berkeley SPICE 2G and its many deriatives Reproduce typical DC, AC, Transient, and Noise performance
• Support room temperature simulations The readme file that accompanies the diskette lists released models and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file.
15 www.national.com
CLC5612
Application Division
Application Circuits Single Supply Cable Driver
(Continued)
Rm/2 Req Vd/2 1 2 Vin Rt 3 4
1kΩ 1kΩ
-
1:n
Io Zo RL UTP
1kΩ
+ -
Vo 75Ω
10m of 75Ω Coaxial Cable
75Ω 0.1µF +5V 1 5kΩ
-
+5V 6.8µF
+
CLC5612
Vin
3 5kΩ 4
1kΩ
+ -
CLC5612
NOTE: Channel 2 not shown
DS015001-53
FIGURE 14. Single Supply Cable Driver
Vin = 10MHz, 0.5Vpp
100mV/div
20ns/div
DS015001-54
FIGURE 15. Response After 10m of Cable Differential Line Driver with Load Impedance Conversion The circuit shown in the Typical Application schematic on the front page and in Figure 16, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5612’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5612. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line; other types of lines can also be driven.
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+
0.1µF
0.1µF
2
1kΩ
1kΩ
8 7
1kΩ
0.1µF
FIGURE 16. Differential Line Driver with Load Impedance Conversionn Set up the CLC5612 as a difference amplifier. • Set the Channel 1 amplifier to a gain of +1V/V
6 5
• Set the Channel 2 amplifier to a gain of −1V/V Make the best use of the CLC5612’s output drive capability as follows:
Rm + Req =
where Req is the transformed value of the load impedance, Vmax is the Output Voltage Range, and Imax is the maximum Output Current. Match the line’s characteristic, impedance:
Select the transformer so that it loads the line with a value very near Zo over frequency range. The output impedance of the CLC5612 also affects the match. With an ideal transformer we obtain:
Return Loss = −20 ⋅ log10
where Zo(5612)(jω) is the output impedance of the CLC5612 and |Zo(5612)(jω)|
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