TLC354CPW

TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 D D D D D D D D D D D Single- or Dual-Supply Operation Wide Range of Supply Voltages 1.4 V to 18 V Very Low Supply Current Drain 300 µA Typ at 5 V 130 µA Typ at 1.4 V Built-In ESD Protection High Input Impedance . . . 1012 Ω Typ Extremely Low Input Blas Current 5 pA Typ Ultrastable Low Input Offset Voltage Input Offset Voltage Change at Worst-Case Input Conditions Typically 0.23 µV/Month, Including the First 30 Days Common-Mode Input Voltage Range Includes Ground Outputs Compatible With TTL, MOS, and CMOS Pin-Compatible With LM339 D, N, OR PW PACKAGE (TOP VIEW) 1OUT 2OUT VDD 2IN – 2IN + 1IN – 1IN + 1 14 2 13 3 12 4 11 5 10 6 9 7 8 3OUT 4OUT VDD – /GND 4IN + 4IN – 3IN + 3IN – symbol (each comparator) IN + OUT IN – description This device is fabricated using LinCMOS technology and consists of four independent differential voltage comparators; each is designed to operate from a single power supply. Operation from dual supplies is also possible if the difference between the two supplies is 1.4 V to 18 V. Each device features extremely high input impedance (typically greater than 1012 Ω), which allows direct interface to high-impedance sources. The outputs are n-channel open-drain configurations and can be connected to achieve positive-logic wired-AND relationships. The capability of the TLC354 to operate from a 1.4-V supply makes this device ideal for low-voltage battery applications. The TLC354 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating tested under MIL-STD-833C, Method 3015. However, care should be exercised in handling this device as exposure to ESD may result in degradation of the device parametric performance. The TLC354C is characterized for operation from 0°C to 70°C. The TLC354I is characterized for operation over the industrial temperature range of – 40° to 85°C. The TLC354M is characterized for operation over the full military temperature range – 55°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICES SMALL OUTLINE (D) PLASTIC DIP (P) TSSOP (PW) CHIP FORM (Y) 5 mV TLC354CD TLC354CN TLC354CPW TLC354Y – 40°C to 85°C 5 mV TLC354ID TLC354IN — — – 55°C to 125°C 5 mV TLC354MD TLC354MN — — TA VIO max AT 25°C 0°C to 70°C The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC354CDR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. Copyright  1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 equivalent schematic (each comparator) Common to All Channels VDD OUT VDD – / GND IN + IN – absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 1 8 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC354C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC354I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C TLC354M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values except differential voltages are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN –. 3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction. DISSIPATION RATING TABLE 2 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR DERATE ABOVE TA TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 500 mW 7.6 mW/°C 84°C 500 mW 494 mW 190 mW N 500 mW 9.2 mW/°C 96°C 500 mW 500 mW 230 mW PW 700 mW 5.6 mW/°C 25°C 448 mW N/A N/A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 TLC364Y chip information This chip, when properly assembled, displays characteristics similar to the TLC354C. Thermal compression or ultrasonic bonding can be used on the doped-aluminum bonding pads. Chips can be mounted with conductive epoxy or a gold-silicon preform. VDD (3) BONDING PAD ASSIGNMENTS 1IN + (13) (12) (11) (10) (9) (7) (6) 1IN – 2OUT (14) (8) 3 IN + 65 (9) (7) 3IN – 4OUT (13) (1) 1OUT – + (2) (8) (1) + – + (5) (4) 2IN + 2IN – (14) 3OUT – + – (11) (10) 4IN + 4IN – (12) (2) (3) (4) (5) VDD – /GND (6) CHIP THICKNESS: 15 TYPICAL 90 BONDING PADS: 4 × 4 MINIMUM TJMAX = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 Common-mode input voltage, VIC MIN TLC354M MAX MIN MAX 1.4 16 1.4 16 1.4 16 VDD = 1.4 V VDD = 5 V 0 0.2 0 0.2 0 0.2 0 3.5 0 3.5 0 3.5 VDD = 10 V 0 8.5 0 8.5 0 8.5 0 70 – 40 85 – 55 125 Operating free-air temperature, TA UNIT V V °C electrical characteristics at specified free-air temperature, VDD = 1.4 V PARAMETER POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIO Input offset voltage IIO Input offset current IIB Input bias current VICR Common-mode input voltage range IOH High level output current High-level TEST CONDITIONS VIC = VICRmin min, See Note 4 TA† TLC354C MIN 25°C TYP 2 Full range Low level output voltage Low-level VID = – 0.5 0 5 V, V IOL = 0 0.6 6 mA IOL Low-level output current VID = – 0.5 V, VOL = 300 mV IDD Supply y current (four comparators) VID = 0 0.5 5V V, No load 1.6 130 400 1.6 130 400 200 200 1 300 nA nA 1 100 200 1 300 0.1 200 nA V 1 100 mV pA 20 0 to 0.2 200 1 5 0.1 UNIT pA 10 2 200 5 10 5 1 Full range 2 MAX 1 0 to 0.2 100 TYP 1 0.1 25°C Full range 5 MIN 1 0 to 0.2 Full range 25°C 2 0.6 25°C 25°C MAX 7 5 MAX VOL 5 TLC354M TYP 0.3 25°C VOH = 5 V VOH = 15 V MIN 1 MAX VID = 1 V MAX 6.5 25°C 25°C TLC354I 1.6 130 µA mV mA 300 400 µA † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC354C, – 40°C to 85°C for TLC354I, and – 55°C to 125°C for the TLC354M. MAX is 70°C for TLC354C, 85°C TLC354I, and 125°C for the TLC354M. IMPORTANT: See Parameter Measurement Information. NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. Template Release Date: 7–11–94 Supply voltage, VDD TLC354I MAX TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS TLC354C MIN SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 4 recommended operating conditions electrical characteristics at specified free-air temperature, VDD = 5 V PARAMETER VIO Input offset voltage IIO Input offset current IIB TEST CONDITIONS VIC = VICRmin min, See Note 5 TA† TLC354C MIN 25°C TYP 2 Full range VOH = 5 V VOH = 15 V VOL Low level output voltage Low-level V VID = – 1 V, IOL = 4 mA IOL Low-level output current VID = – 1 V, VOL = 1.5 mV IDD Supply y current (four comparators) VID = 1 V V, No load 5 1 1 5 5 2 25°C Full range 0 to VDD – 1.5 0 to VDD – 1.5 0 to VDD – 1.5 0.1 25°C 150 Full range 25°C 0.1 1 150 700 6 25°C 16 0.3 Full range 0.1 150 700 6 0.6 16 0.3 0.8 400 700 6 0.6 nA nA 1 400 nA V 1 400 mV pA 20 0 to VDD – 1 UNIT pA 10 0 to VDD – 1 25°C 5 10 1 0.6 MAX 2 7 0 to VDD – 1 Full range TYP 16 0.3 0.8 µA mV mA 0.6 0.8 mA † All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70 °C for TLC354C, – 40°C to 85°C for TLC354I, and – 55°C to 125°C for the TLC354M. MAX is 70°C for TLC354C, 85°C TLC354I, and 125°C for the TLC354M. IMPORTANT: See Parameter Measurement Information. NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. switching characteristics, VDD = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TLC354C, TLC354I TLC354M MIN Response time RL connected to 5 V through g 5.1 kΩ, CL = 15 pF ‡, See Note 6 TYP 100-mV input step with 5-mV overdrive 650 TTL-level input step 200 ‡ CL includes probe and jig capacitance. NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. UNIT MAX ns 5 TLC354 LinCMOS  QUADRUPLE DIFFERENTIAL COMPARATORS VID = 1 V 2 5 MIN SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 High level output current High-level MAX 5 MAX TLC354M TYP 0.3 25°C IOH MIN 1 MAX Common-mode input VICR voltage range MAX 6.5 25°C Input bias current TLC354I TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 electrical characteristics at specified free-air temperature, VDD = 1.4 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS VIC = VICR min, TLC354Y MIN See Note 4 TYP MAX 2 5 UNIT VIO IIO Input offset voltage Input offset current 1 pA IIB Input bias current 5 pA VICR Common-mode input voltage range IOH VOL High-level output current IOL IDD Low-level output current 0 to 0.2 Low-level output voltage Supply current (four comparators) VID = 1 V, VID = – 0.5 V, VOH = 5 V IOL = 0.6 mA VID = – 0.5 V, VID = 0.5 V, VOL = 300 mV No load V 0.1 100 1 mV nA 200 1.6 130 mV mA 300 µA NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. electrical characteristics at specified free-air temperature, VDD = 5 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS VIC = VICR min, TLC354Y MIN See Note 5 TYP MAX 2 5 UNIT VIO IIO Input offset voltage Input offset current 1 pA IIB Input bias current 5 pA VICR Common-mode input voltage range IOH VOL High-level output current IOL IDD Low-level output current 0 to VDD – 1 Low-level output voltage Supply current (four comparators) VID = 1 V, VID = – 1 V, VOH = 5 V IOL = 4 mA VID = – 1 V, VID = 1 V, VOL = 1.5 mV No load V 0.1 150 6 mV nA 400 16 0.3 mV mA 0.6 mA NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state. switching characteristics, VDD = 5 V, TA = 25°C PARAMETER Response time TEST CONDITIONS RL connected to 5 V through g 5.1 kΩ, CL = 15 pF ‡, See Note 6 TLC354Y MIN TYP 100-mV input step with 5-mV overdrive 650 TTL-level input step 200 MAX ‡ CL includes probe and jig capacitance. NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION The digital output stage of the TLC354 can be damaged if it is held in the linear region of the transfer curve. Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are offered. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal but opposite in polarity to the input offset voltage, the output changes state. 5V 1V 5.1 kΩ Applied VIO Limit VO 5.1 kΩ Applied VIO Limit VO –4 V (a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION Figure 2 illustrates a practicle circuit for direct dc measurement of input offset voltage that does not bias the comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be 1% or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. VDD U1b 1/4 TLC274CN Buffer + C2 1 µF – R4 47 kΩ R1 240 kΩ + C1 0.1 µF – R6 5.1 kΩ R2 R3 10 kΩ 100 kΩ C3 0.68 µF U1c 1/4 TLC274CN – OUT R7 1 MΩ R8 1.8 kΩ, 1% U1a 1/4 TLC274CN Triangle Generator R5 1.8 kΩ, 1% R10 100 Ω, 1% + Integrator C4 0.1 µF R9 10 kΩ, 1% Figure 2. Test Circuit for Input Offset Voltage Measurement 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VIO (X100) TLC354 LinCMOS QUADRUPLE DIFFERENTIAL COMPARATORS SLCS116B – SEPTEMBER 1985 – REVISED FEBRUARY 1997 PARAMETER MEASUREMENT INFORMATION Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the trailing edge of the input pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a low signal, for example, 105-mV or 5-mV overdrive, causes the output to change. VDD 1 µF 5.1 kΩ Pulse Generator OUT CL (see Note A) 50 Ω 1V Input Offset Voltage Compensation Adjustment 10 Ω 10 Turn 1 kΩ 0.1 µF –1 V TEST CIRCUIT Overdrive 100 mV Overdrive Input Input 100 mV 90% 50% Low-to-HighLevel Ouptut 10% High-to-LowLevel Ouptut 90% 50% 10% tf tr tPLH tPLH VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 3. Response, Rise, and Fall Times Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC354CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC354C Samples TLC354CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC354CN Samples TLC354CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P354 Samples TLC354CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P354 Samples TLC354ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC354I Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of