CY7C1020B-15VCT

CY7C1020B 32K x 16 Static RAM Features Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). • High speed — tAA = 12, 15 ns • CMOS for optimum speed/power • Low active power — 825 mW (max.) • Low CMOS standby power (L version only) — 2.75 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in lead-free and non-lead-free 44-pin TSOP II and 44-pin (400-mil) SOJ packages Functional Description The CY7C1020B is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020B is available in standard 44-pin TSOP Type II and 44-pin 400-mil-wide SOJ packages. Logic Block Diagram Pin Configuration SOJ / TSOP II Pinout Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Selection Guide CY7C1020B-12 CY7C1020B-15 Maximum Access Time (ns) 12 15 Maximum Operating Current (mA) 140 130 3 3 0.5 0.5 Maximum CMOS Standby Current (mA) L Cypress Semiconductor Corporation Document #: 38-05171 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 26, 2006 CY7C1020B Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Range Commercial Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% DC Input Voltage[1] .................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Parameter CY7C1020B-12 Test Conditions Description VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. CY7C1020B-15 Max. Min. 2.4 Max. V 0.4 Voltage[1] Unit 2.4 0.4 V V 2.2 6.0 2.2 6.0 VIL Input LOW –0.5 0.8 –0.5 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 –1 +1 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 140 130 mA ISB1 Automatic CE Power-Down Current—TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 20 20 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 3 3 mA 0.5 0.5 mA L Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 8 pF Thermal Resistance[4] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board TSOP II Package SOJ Package Unit 50.55 56.31 °C/W 15.8 32.9 °C/W Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05171 Rev. *B Page 2 of 9 CY7C1020B AC Test Loads and Waveforms R 481Ω 5V R 481Ω 5V OUTPUT ALL INPUT PULSES 3.0V 90% OUTPUT 30 pF R2 255Ω R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) 167 OUTPUT Equivalent to: THÉVENIN EQUIVALENT 90% 10% 10% GND Rise Time: 1 V/ns Fall Time: 1 V/ns 1.73V 30 pF Switching Characteristics[5] Over the Operating Range Parameter Description CY7C1020B-12 CY7C1020B-15 Min. Min. Max. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE tDOE tLZOE ns OE LOW to Data Valid 6 7 ns Z[6] Z[6] CE HIGH to High 0 Z[6, 7] tPD CE HIGH to Power-Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low Z 0 6 3 Z[6, 7] CE LOW to Power-Up Write 3 ns ns tPU tHZBE 3 15 CE LOW to Data Valid CE LOW to Low tHZCE 12 ns 15 OE HIGH to High tLZCE 15 12 OE LOW to Low tHZOE 12 3 6 0 7 6 0 ns ns 15 ns 7 ns 0 6 ns ns 0 12 Byte Disable to High Z ns 7 ns 7 ns Cycle[8] tWC Write Cycle Time 12 15 ns tSCE CE LOW to Write End 9 10 ns tAW Address Set-Up to Write End 8 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 8 10 ns tSD Data Set-Up to Write End 6 8 ns tHD Data Hold from Write End 0 0 ns 3 3 ns WE HIGH to Low Z[6] tHZWE WE LOW to High Z[6, 7] tBW Byte Enable to End of Write tLZWE 6 8 7 9 ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05171 Rev. *B Page 3 of 9 CY7C1020B Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05171 Rev. *B Page 4 of 9 CY7C1020B Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05171 Rev. *B Page 5 of 9 CY7C1020B Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X L L L X I/O1–I/O8 I/O9–I/O16 Mode Power BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High Z Read – Lower bits only Active (ICC) H L High Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High Z Write – Lower bits only Active (ICC) H L High Z Data In Write – Upper bits only Active (ICC) L L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05171 Rev. *B Page 6 of 9 CY7C1020B Ordering Information Speed (ns) 12 Ordering Code CY7C1020B-12VC Package Diagram 51-85082 Package Type 44-pin (400-Mil) Molded SOJ Operating Range Commercial CY7C1020BL-12VC CY7C1020B-12VXC CY7C1020B-12ZC 44-pin (400-Mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP Type II 51-85082 44-pin (400-Mil) Molded SOJ 51-85087 44-pin TSOP Type II CY7C1020BL-12ZC CY7C1020B-12ZXC 15 CY7C1020B-15VC 44-pin TSOP Type II (Pb-free) CY7C1020BL-15VC CY7C1020B-15ZC CY7C1020BL-15ZC CY7C1020B-15ZXC 44-pin TSOP Type II (Pb-free) Package Diagrams 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B Document #: 38-05171 Rev. *B Page 7 of 9 CY7C1020B Package Diagrams (continued) 44-pin TSOP II (51-85087) 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05171 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1020B Document History Page Document Title: CY7C1020B 32K x 16 Static RAM Document #: 38-05171 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 115439 05/09/02 DSG New Data Sheet *A 116869 08/21/02 DFP Added L-Power Specifications. *B 426747 See ECN ZSD Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court”. Added thermal resistance table. Updated the ordering information table and replaced the Package Name column with Package Diagram. Document #: 38-05171 Rev. *B Page 9 of 9