CY7C188-15VCT

CY7C188 32K x 9 Static RAM Features Functional Description • High speed The CY7C188 is a high-performance CMOS static RAM organized as 32,768 words by 9 bits. Easy memory expansion is provided by an active-LOW chip enable (CE1), an active-HIGH chip enable (CE2), an active-LOW output enable (OE), and tri-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. — 15 ns • Automatic power-down when deselected • Low active power — 660 mW • Low standby power Writing to the device is accomplished by taking CE1 and write enable (WE) inputs LOW and CE2 input HIGH. Data on the nine I/O pins (I/Oo – I/O8) is then written into the location specified on the address pins (A0 – A14). — 55 mW • CMOS for optimum speed/power • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE features • Available in non Pb-free 32-Lead (300-Mil) Molded SOJ Reading from the device is accomplished by taking CE1 and OE LOW while forcing WE and CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The nine input/output pins (I/O0 – I/O8) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C188 is available in standard 300-mil-wide SOJ. Logic Block Diagram Pin Configuration SOJ Top View I/O0 I/O1 I/O2 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 ROW DECODER INPUT BUFFER 32K x 9 ARRAY I/O3 I/O4 I/O5 I/O6 COLUMN DECODER POWER DOWN Cypress Semiconductor Corporation Document #: 38-05053 Rev. *A I/O0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A14 CE2 WE A13 A9 A10 A11 OE A12 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 C188–2 I/O7 I/O8 A7 A8 A9 A 10 A 11 A 12 A 13 A 14 CE1 CE2 WE OE NC NC A8 A7 A6 A5 A4 A3 A2 A1 A0 C188–1 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 28, 2006 CY7C188 Selection Guide Maximum Access Time (ns) –15 15 –20 20 Maximum Operating Current (mA) 120 170 Maximum CMOS Standby Current (mA) 10 15 DC Input Voltage[1] ................................. –0.5V to VCC +0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND (Pin 32 to Pin 16) .......................................... –0.5V to + 7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Electrical Characteristics Over the Operating Range[2] –15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Voltage[1] Min. –20 Max. Min. 2.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC + 0.3 2.2 VCC + 0.3 V –0.5 0.8 –0.5 0.8 V VIL Input LOW IIX Input Leakage Current GND ≤ VI ≤ VCC –5 +5 –5 +5 µA IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled –5 +5 –5 +5 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 120 170 mA ISB1 Automatic CE Power-Down Current— TTL Inputs Max. VCC, CE1 ≥ VIH or CE2 ≤ VIL,VIN ≥ VIH or VIN ≤ VIL, f = fMAX 35 35 mA ISB2 Automatic CE Power-Down Current — CMOS Inputs Max. VCC, CE1 ≥ VCC –0.3V or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V, f = 0 10 15 mA Capacitance[3] Parameter Description CIN: Addresses Input Capacitance CIN: Controls Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 6 pF 8 pF 8 pF Notes: 1. Minimum voltage is equal to –2.0V for pulse durations less than 20 ns. 2. See the last page of this specification for Group A subgroup testing information. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05053 Rev. *A Page 2 of 7 CY7C188 AC Test Loads and Waveforms[4, 5] R1 481Ω R1 481Ω 5V 5V OUTPUT ALLINPUTPULSES OUTPUT R2 255Ω 30 pF INCLUDING JIGAND SCOPE Equivalent to: 3.0V R2 255Ω 5 pF INCLUDING JIGAND SCOPE (a) (b) 10% 90% 10% 90% GND ≤ 3 ns ≤ 3 ns C188–3 C188–4 THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[2, 4] –15 Parameter Description Min. –20 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 15 20 ns tDOE OE LOW to Data Valid 7 9 ns 15 Z[6] tLZOE OE LOW to Low tHZOE OE HIGH to High Z[5,6] 3 20 CE1 LOW or CE2 HIGH to Low tHZCE CE1 HIGH or CE2 LOW to High Z[5, 6] tPU CE1 LOW or CE2 HIGH to Power-Up tPD CE1 HIGH or CE2 LOW to Power-Down 3 ns 9 3 7 0 ns ns 9 0 15 ns ns 0 7 Z[6] ns 3 0 tLZCE WRITE 20 ns ns 20 ns CYCLE[7, 8] tWC Write Cycle Time 15 20 ns tSCE CE1 LOW or CE2 HIGH to Write End 10 15 ns tAW Address Set-Up to Write End 10 15 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 10 15 ns tSD Data Set-Up to Write End 8 10 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[5] 0 tLZWE WE HIGH to Low Z[5, 6] 3 0 7 0 3 ns 7 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE1, LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 8. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05053 Rev. *A Page 3 of 7 CY7C188 Switching Waveforms Read Cycle No. 1[9,10] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C188–5 Read Cycle No. 2 (Chip-Enable Controlled)[10,11,12] tRC CE1 tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C188–6 Write Cycle No. 1 (WE Controlled)[7,12,13,14] tWC ADDRESS CE1 tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATA IN VALID NOTE 15 tHZOE C188–7 Notes: 9. Device is continuously selected. OE, CE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. 12. Timing parameters are the same for all chip enable signals (CE1 and CE2), so only the timing for CE1 is shown. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in the output state and input signals should not be applied. Document #: 38-05053 Rev. *A Page 4 of 7 CY7C188 Switching Waveforms (Continued) Write Cycle No.2 (CE Controlled)[7,12,13,14] tWC ADDRESS tSCE CE1 tSA tAW tHA WE tSD tHD DATA IN VALID DATA I/O C188–8 Write Cycle No. 3 (WE Controlled, OE LOW)[8,12,14] tWC ADDRESS CE tAW tHA tSA WE tSD NOTE 15 DATA I/O tHD DATA IN VALID tLZWE tHZWE C188–9 Truth Table CE WE OE Input/Output Mode Power H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C188–15VC 51-85041 32-Lead (300-Mil) Molded SOJ Commercial 20 CY7C188–20VC 51-85041 32-Lead (300-Mil) Molded SOJ Commercial Document #: 38-05053 Rev. *A Page 5 of 7 CY7C188 Package Diagrams 32-Lead (300-Mil) Molded SOJ (51-85041) PIN 1 I.D DIMENSIONS IN INCHES 0.330 0.292 0.340 0.305 MIN. MAX. LEAD COPLANARITY 0.004 MAX. 0.810 0.830 0.128 * 0.140 0.050 TYP. 0.026 0.032 0.014 * 0.025 MIN. 0.006 0.012 0.260 * 0.275 51-85041-*A 0.020 All products and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-05053 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C188 Document History Page Document Title: CY7C188 32K x 9 Static RAM Document Number: 38-05053 Orig. of Issue Date Change Description of Change 107155 09/10/01 SZV Change from Spec number: 38-00220 to 38-05053 506367 See ECN NXR Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information table REV. ECN NO. ** *A Document #: 38-05053 Rev. *A Page 7 of 7