LPC662AIM

LPC662 Low Power CMOS Dual Operational Amplifier March 1998 LPC662 Low Power CMOS Dual Operational Amplifier General Description The LPC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It features a wide range of operating voltage from +5V to +15V, rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain (into 100 kΩ and 5 kΩ) are all equal to or better than widely accepted bipolar equivalents, while the power supply requirement is typically less than 0.5 mW. This chip is built with National’s advanced Double-Poly Silicon-Gate CMOS process. See the LPC660 datasheet for a Quad CMOS operational amplifier and LPC661 for a single CMOS operational amplifier with these same features. n n n n n Long-term integrator High-impedance preamplifier Active filter Sample-and-Hold circuit Peak detector Features n n n n n n n n n n n n Rail-to-rail output swing Micropower operation ( < 0.5 mW) Specified for 100 kΩ and 5 kΩ loads High voltage gain 120 dB Low input offset voltage 3 mV Low offset voltage drift 1.3 µV/˚C Ultra low input bias current 2 fA Input common-mode includes GND Operating range from +5V to +15V Low distortion 0.01% at 1 kHz Slew rate 0.11 V/µs Full military temperature range available Applications n High-impedance buffer n Precision current-to-voltage converter Connection Diagram 8-Pin DIP/SO DS010548-1 Top View Ordering Information Package 8-Pin Side Brazed Ceramic DIP 8-Pin Small Outline 8-Pin Molded DIP 8-Pin Ceramic DIP © 1999 National Semiconductor Corporation DS010548 www.national.com Temperature Range Military LPC662AMD Industrial NSC Drawing D08C Transport Media Rail LPC662AIM or LPC662IM LPC662AIN or LPC662IN LPC662AMJ/883 M08A N08E J08A Rail Tape and Reel Rail Rail Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Differential Input Voltage Supply Voltage (V+ − V−) Output Short Circuit to V+ Output Short Circuit to V− Lead Temperature (Soldering, 10 sec.) Storage Temp. Range Junction Temperature ESD Rating (C = 100 pF, R = 1.5 kΩ) Power Dissipation Current at Input Pin Current at Output Pin Current at Power Supply Pin Voltage at Input/Output Pin 35 mA (V+) + 0.3V, (V−) −0.3V Operating Ratings (Note 3) Temperature Range LPC662AMJ/883 LPC662AM LPC662AI LPC662I Supply Range Power Dissipation Thermal Resistance (θJA) (Note 10) 8-Pin Ceramic DIP 8-Pin Molded DIP 8-Pin SO 8-Pin Side Brazed Ceramic DIP −55˚C ≤ TJ ≤ +125˚C −55˚C ≤ TJ ≤ +125˚C −40˚C ≤ TJ ≤ +85˚C −40˚C ≤ TJ ≤ +85˚C 4.75V to 15.5V (Note 9) 100˚C/W 101˚C/W 165˚C/W 100˚C/W ± Supply Voltage 16V (Note 11) (Note 1) 260˚C −65˚C to +150˚C 150˚C 1000V (Note 2) ± 5 mA ± 18 mA DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. LPC662AM Parameter Conditions Typ LPC662AMJ/883 Limit (Notes 4, 8) Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current Input Offset Current Input Resistance Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Input Common-Mode Voltage Range V+ = 5V and 15V For CMRR ≥ 50 dB V+ − 1.9 Large Signal Voltage Gain RL = 100 kΩ (Note 5) Sourcing Sinking RL = 5 kΩ (Note 5) Sourcing Sinking 250 500 1000 1000 −0.4 0V ≤ VCM ≤ 12.0V V+ = 15V 5V ≤ V+ ≤ 15V VO = 2.5V 0V ≤ V− ≤ −10V 0.002 0.001 20 100 20 100 2 70 68 70 68 84 83 −0.1 0 V+ − 2.3 V+ − 2.5 400 300 180 120 200 160 100 60 2 63 61 63 61 74 73 −0.1 0 V+ − 2.3 V+ − 2.5 300 200 90 70 100 80 50 40 4 4 pA max pA max Tera Ω 70 68 83 94 70 68 84 82 −0.1 0 V+ − 2.3 V+ − 2.6 400 250 180 70 200 150 100 35 dB min dB min dB min V max V min V/mV min V/mV min V/mV min V/mV min 1 1.3 3 3.5 3 3.3 6 6.3 mV max µV/˚C LPC662AI Limit (Note 4) LPC662I Limit (Note 4) Units >1 83 www.national.com 2 DC Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. LPC662AM Parameter Conditions Typ LPC662AMJ/883 Limit (Notes 4, 8) Output Swing V+ = 5V RL = 100 kΩ to V+/2 4.987 0.004 V+ = 5V RL = 5 kΩ to V+/2 4.940 0.040 V+ = 15V RL = 100 kΩ to V+/2 14.970 0.007 V+ = 15V RL = 5 kΩ to V+/2 14.840 0.110 Output Current V+ = 5V Sourcing, VO = 0V Sinking, VO = 5V Output Current V+ = 15V Sourcing, VO = 0V Sinking, VO = 13V (Note 11) Supply Current Both Amplifiers VO = 1.5V 86 22 21 40 39 4.970 4.950 0.030 0.050 4.850 4.750 0.150 0.250 14.920 14.880 0.030 0.050 14.680 14.600 0.220 0.300 16 12 16 12 19 19 19 19 120 145 4.970 4.950 0.030 0.050 4.850 4.750 0.150 0.250 14.920 14.880 0.030 0.050 14.680 14.600 0.220 0.300 16 14 16 14 28 25 28 24 120 140 4.940 4.910 0.060 0.090 4.750 4.650 0.250 0.350 14.880 14.820 0.060 0.090 14.580 14.480 0.320 0.400 13 11 13 11 23 20 23 19 140 160 V min V max V min V max V min V max V min V max mA min mA min mA min mA min µA max LPC662AI Limit (Note 4) LPC662I Limit (Note 4) Units 3 www.national.com AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. LPC662AM Parameter Conditions Typ LPC662AMJ/883 Limit (Notes 4, 8) Slew Rate Gain-Bandwidth Product Phase Margin Gain Margin Amp-to-Amp Isolation Input Referred Voltage Noise Input Referred Current Noise Total Harmonic Distortion (Note 7) F = 1 kHz F = 1 kHz F = 1 kHz, AV = −10, V+ = 15V RL = 100 kΩ, VO = 8 VPP (Note 6) 0.11 0.35 50 17 130 42 0.0002 0.01 % 0.07 0.04 0.07 0.05 0.05 0.03 V/µs min MHz Deg dB dB LPC662AI Limit (Note 4) LPC662I Limit (Note 4) Units Note 1: Applies to both single supply and split supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability. Note 2: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation of any ambient temperature is PD = (TJ(max) − TA)/θJA. Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 4: Limits are guaranteed by testing or correlation. Note 5: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 6: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 7: Input referred. V+ = 15V and RL = 100 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP. Note 8: A military RETS electrical test specification is available on request. At the time of printing, the LPC662AMJ/883 RETS specification complied fully with the boldface limits in this column. The LPC662AMJ/883 may also be procured to a Standard Military Drawing specification. Note 9: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. Note 10: All numbers apply for packages soldered directly into a PC board. Note 11: Do not connect output to V+when V+ is greater than 13V or reliability may be adversely affected. www.national.com 4 Typical Performance Characteristics Supply Current vs Supply Voltage VS = ± 7.5V, TA = 25˚C unless otherwise specified Input Common-Mode Voltage Range vs Temperature Input Bias Current vs Temperature DS010548-28 DS010548-29 DS010548-30 Output Characteristics Current Sinking Output Characteristics Current Sourcing Input Voltage Noise vs Frequency DS010548-32 DS010548-31 DS010548-33 Crosstalk Rejection vs Frequency CMRR vs Frequency CMRR vs Temperature DS010548-35 DS010548-34 DS010548-36 5 www.national.com Typical Performance Characteristics Open-Loop Voltage Gain vs Temperature VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Gain and Phase Responses vs Load Capacitance Open-Loop Frequency Response DS010548-38 DS010548-39 DS010548-40 Gain and Phase Responses vs Temperature Gain Error (VOSvs VOUT) Non-Inverting Slew Rate vs Temperature DS010548-41 DS010548-42 DS010548-43 Inverting Slew Rate vs Temperature Large-Signal Pulse Non-Inverting Response (AV = +1) Non-Inverting Small Signal Pulse Response (AV = +1) DS010548-44 DS010548-45 DS010548-46 www.national.com 6 Typical Performance Characteristics Inverting Large-Signal Pulse Response VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Inverting Small-Signal Pulse Response Power Supply Rejection Ratio vs Frequency DS010548-47 DS010548-37 DS010548-48 Stability vs Capacitive Load Stability vs Capacitive Load DS010548-4 DS010548-5 Note: Avoid resistive loads of less than 500Ω, as they may cause instability. Application Hints AMPLIFIER TOPOLOGY The topology chosen for the LPC662 is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the integrator. As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain stages with two fed forward. DS010548-6 FIGURE 1. LPC662 Circuit Topology (Each Amplifier) The large signal voltage gain while sourcing is comparable to traditional bipolar op amps for load resistance of at least 5 kΩ. The gain while sinking is higher than most CMOS op 7 www.national.com Application Hints (Continued) amps, due to the additional gain stage; however, when driving load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical Characteristics. The op amp can drive load resistance as low as 500Ω without instability. COMPENSATING INPUT CAPACITANCE Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary for compensation and what the value of that capacitor would be. CAPACITIVE LOAD TOLERANCE Like many other op amps, the LPC662 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp’s phase margin so that the amplifier is no longer stable at low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp’s output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capacitance is near the threshold for oscillation. amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). DS010548-26 FIGURE 3. Compensating for Large Capacitive Loads with A Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LPC662, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LPC662’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs. See Figure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012 ohms, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the LPC662’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 ohms would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier’s performance. See Figure 5a, Figure 5b, Figure 5c for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 5d. DS010548-7 FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 3. Typically a pull up resistor conducting 50 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the www.national.com 8 Application Hints (Continued) DS010548-19 FIGURE 4. Example of Guard Ring in P.C. Board Layout, using the LPC660 DS010548-22 (c) Follower DS010548-20 (a) Inverting Amplifier DS010548-21 (b) Non-Inverting Amplifier DS010548-23 (d) Howland Current Pump FIGURE 5. Guard Ring Connections The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. 9 www.national.com Application Hints (Continued) DS010548-24 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) FIGURE 6. Air Wiring BIAS CURRENT TESTING The test method of Figure 7 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then DS010548-25 FIGURE 7. Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2 should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted) where Cx is the stray capacitance at the + input. Typical Single-Supply Applications Photodiode Current-to-Voltage Converter (V = 5.0 VDC) Micropower Current Source + DS010548-18 DS010548-17 Note: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current). Note: (Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current requirement of LM385.) www.national.com 10 Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) Low-Leakage Sample-and-Hold DS010548-8 Instrumentation Amplifier DS010548-9 For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7. 11 www.national.com Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) Sine-Wave Oscillator DS010548-10 Oscillator frequency is determined by R1, R2, C1, and C2: fOSC = 1/2πRC where R = R1 = R2 and C = C1 = C2. This circuit, as shown, oscillates at 2.0 kHz with a peak-to-peak output swing of 4.5V 1 Hz Square-Wave Oscillator Power Amplifier DS010548-12 DS010548-11 www.national.com 12 Typical Single-Supply Applications 10 Hz Bandpass Filter (V+ = 5.0 VDC) (Continued) 10 Hz High-Pass Filter (2 dB Dip) DS010548-14 DS010548-13 fO = 10 Hz Q = 2.1 Gain = −8.8 fc = 10 Hz d = 0.895 Gain = 1 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) High Gain Amplifier with Offset Voltage Reduction DS010548-15 DS010548-16 Gain = −46.8 Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred to VBIAS. 13 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Cavity Dual-In-Line Package (D) Order Number LPC662AMD NS Package Number D08C Ceramic Dual-In-Line Package (J) Order Number LPC662AMJ/883 NS Package Number J08A www.national.com 14 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Pin Small Outline Molded Package (M) Order Number LPC662AIM or LPC662IM NS Package Number M08A 8-Pin Molded Dual-In-Line Package (N) Order Number LPC662AIN or LPC662IN NS Package Number N08E 15 www.national.com LPC662 Low Power CMOS Dual Operational Amplifier Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.