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NTE74HC32

NTE74HC32

  • 厂商:

    NTE

  • 封装:

    DIP-14

  • 描述:

    IC GATE OR 4CH 2-INP 14DIP

  • 数据手册
  • 价格&库存
NTE74HC32 数据手册
NTE74HC32 Integrated Circuit TTL − High Speed CMOS, Quad 2−Input OR Gate Description: The NTE74HC32 contains four 2−input OR gates in a 14−Lead DIP type package. Logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LS−TTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LS− TTL loads. Features: D Wide Power Supply Range: 2V to 6V D High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V D Typical Propagation Delay: 7ns at VCC = 5V, CL = 15pF, TA = +25C D Fanout (Over Temperature Range): Standard Outputs . . . 10 LS−TTL Loads Bus Driver Outputs . . 15 LS−TTL Loads D Balanced Propagation Delay and Transition Times D Significant Power Reduction Compared to LS−TTL Logic ICs Absolute Maximum Ratings: (Note 1, Note 2) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V Clamp Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA DC Drain Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA DC Output Source or Sink Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Maximum Junction, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C Typical Thermal Resistance, Junction−to−Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2. Unless otherwise specified, all voltages are referenced to GND. Recommended Operating Conditions: Parameter Supply Voltage DC Input or Output Voltage Operating Temperature Range Input Rise or Fall Times VCC = 2.0V VCC = 4.5V VCC = 6.0V Symbol Min Typ Max Unit VCC VIN, VOUT TA tr, tf 2.0 0 −40 − − − 6.0 VCC +85 V V C − − − − − − 1000 500 400 ns ns ns DC Electrical Characteristics: TA = +25C Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage Minimum LOW Level Output Voltage Symbol VIH Test Conditions VIL VOH VOL VIN = VIH or VIL VIN = VIH or VIL TA = −40 to +85C VCC Typ Guaranteed Limits 2.0 − 1.5 1.5 Unit V 4.5 − 3.15 3.15 V 6.0 − 4.2 4.2 V 2.0 − 0.5 0.5 V 4.5 − 1.35 1.35 V 6.0 − 1.8 1.8 V VCC VCC −0.1 VCC −0.1 IOUT = −20A − V IOUT = −4mA 4.5 − 3.98 3.84 V IOUT = −5.2mA 6.0 − 5.48 5.34 V IOUT = 20A − − 0.1 0.1 V IOUT = 4mA 4.5 0.2 0.26 0.33 V IOUT = 5.2mA 6.0 0.2 0.26 0.33 V Maximum Input Leakage Current IIN VIN = VCC or GND 6.0 − 0.1 1.0 A Maximum Quiescent Device Current ICC VIN = VCC or GND, IOUT = 0A 6.0 − 2.0 20 A Switching Specifications: (tr = tf = 6ns unless otherwise specified) TA = +25C Parameter Propagation Delay Time (Input to Output) Symbol Test Conditions tPLH, tPHL CL = 50pF TA = −40 to +85C VCC Typ 2.0 − 90 Guaranteed Limits 115 Unit ns 4.5 − 18 23 ns 6.0 − 15 20 ns Propagation Delay Time (Data Input to Output Y) tPLH, tPHL CL = 15pF 5.0 7 − − ns Transition Time tTLH, tTHL CL = 50pF 2.0 − 75 95 ns 4.5 − 15 19 ns 6.0 − 13 16 ns − − 10 10 pF 5.0 22 − − pF Maximum Input Capacitance CIN Power Dissipation Capacitance CPD Note 3 Note 3. CPD is used to determine the dynamic power consumption, per gate. PD = CPD VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Truth Table: Inputs nA L L H H nB L H L H H = HIGH Level L = LOW Level Output nY L H H H Logic Diagram nA nY nB Pin Connection Diagram 1A 1 14 VCC 1B 2 1Y 3 13 4B 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 14 8 1 7 .300 (7.62) .770 (19.56) Max .200 (5.08) Max .100 (2.45) .600 (15.24) .125 (3.17) Min
NTE74HC32 价格&库存

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