MSM51V18165F

Semiconductor MSM51V18165F This version:Oct.1999 1,048,576-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSM51V18165F is a 1,048,576-word ´ 16-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V18165F achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V18165F is available in a 42-pin plastic SOJ or 50/44-pin plastic TSOP. FEATURES · · · · · · · · · 1,048,576-word ´ 16-bit configuration Single 3.3V power supply, ±0.3V tolerance Input Output Refresh : LVTTL compatible, low input capacitance : LVTTL compatible, 3-state : 1024 cycles/16ms Fast page mode with EDO, read modify write capability CAS before RAS refresh, hidden refresh, RAS-only refresh capability CAS before RAS self-refresh capability Package options: 42-pin 400mil plastic SOJ 50/44-pin 400mil plastic TSOP (SOJ42-P-400-1.27) (TSOPII50/44-P-400-0.80-K) (TSOPII50/44-P-400-0.80-L) (Product : MSM51V18165F-xxJS) (Product : MSM51V18165F-xxTS-K) (Product : MSM51V18165F-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family tRAC 50ns MSM51V18165F 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 84ns 104ns 124ns Power Dissipation Operating (Max.) 324mW 288mW 252mW 1.8mW Standby (Max.) No. 1/14 PIN CONFIGRATION (TOP VIEW) VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC 50 49 48 47 46 45 44 43 42 41 40 1 2 3 4 5 6 7 8 9 10 11 VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC 42-Pin Plastic SOJ NC 15 NC 16 WE 17 RAS 18 NC 19 NC 20 A0 21 A1 22 A2 23 A3 24 VCC 25 36 35 34 33 32 31 30 29 28 27 26 NC 36 NC LCAS LCAS 35 UCAS UCAS 34 OE OE 33 A9 A9 32 A8 A8 31 A7 30 A7 A6 29 A6 A5 A5 28 A4 A4 27 VSS 26 VSS 15 16 17 18 19 20 21 22 23 24 25 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 55/44-Pin Plastic TSOP (K Type) 55/44-Pin Plastic TSOP (L Type) Pin Name A0–A9 RAS LCAS UCAS DQ1–DQ16 OE WE VCC VSS NC Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. No. 2/14 BLOCK DIAGRAM WE RAS LCAS UCAS Column Address Buffers Internal Address Counter Row Address Buffers Timing Generator I/O Controller I/O Controller 10 10 Column Decoders 8 Output Buffers 8 OE DQ1-DQ8 8 I/O Selector Input Buffers 8 A0-A9 Refresh Control Clock Sense Amplifiers 16 16 Input Buffers 8 10 10 Row Decoders Word Drivers Memory Cells 8 8 DQ9-DQ16 Output Buffers 8 VCC On Chip VBB Generator On Chip IVCC Generator VSS FUNCTION TABLE Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H DQ Pin Function Mode DQ1-DQ8 High-Z High-Z DOUT High-Z DOUT DIN Don’t Care DIN High-Z DQ9-DQ16 High-Z High-Z High-Z DOUT DOUT Don’t Care DIN DIN High-Z Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write ¾ * : “H” or “L” No. 3/14 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg Rating - 0.5 to VCC + 0.3 - 0.5 to 4.6 50 1 0 to 70 - 55 to 150 Unit V V mA W °C °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0 °C to 70 °C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 3.0 0 2.0 - 0.3 *2 Typ. 3.3 0 ¾ ¾ Max. 3.6 0 VCC + 0.3 0.8 *1 Unit V V V V VCC VSS VIH VIL Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). Capacitance (VCC = 3.3V ± 0.3V, Ta = 25°C, f=1MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol Typ. ¾ ¾ ¾ Max. 5 7 7 Unit pF pF pF CIN1 CIN2 CI/O No. 4/14 DC Characteristics (VCC = 3.3V ± 0.3V, Ta = 0°C to 70°C) MSM51V18165 MSM51V18165 MSM51V18165 F-50 F-60 F-70 Unit Note Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL ILI IOH = -2.0mA IOL = 2mA 0V £ VI £ VCC+0.3V; All other pins not under test = 0V DQ disable 0V £ VO £ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ³ VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. ¾ 90 ¾ 80 ¾ 70 mA 1,3 ¾ ¾ ¾ ¾ 5 ¾ 5 ¾ 5 mA 1 ¾ 90 ¾ 80 ¾ 70 mA 1,2 - 10 10 - 10 10 - 10 10 mA 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V Parameter Symbol Condition ILO - 10 10 - 10 10 - 10 10 mA ICC1 ¾ ¾ ¾ 90 ¾ ¾ ¾ 80 ¾ ¾ ¾ 70 mA 1,2 2 0.5 2 0.5 2 0.5 mA 1 90 80 70 mA 1,2 Notes: 1. 2. 3. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. No. 5/14 AC Characteristic (1/2) (VCC = 3.3V ± 0.3V, Ta = 0°C to 70°C) Note1,2,3 MSM51V18165 F-50 Symbol Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turnoff Delay Time RAS to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turnoff Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP 84 110 20 58 ¾ ¾ ¾ ¾ ¾ 0 5 0 0 0 0 1 ¾ 30 50 50 7 7 7 7 35 5 30 Max. ¾ ¾ ¾ ¾ 50 13 25 30 13 ¾ ¾ 13 13 13 13 50 16 ¾ 10,000 100,000 ¾ ¾ ¾ 10,000 ¾ ¾ ¾ MSM51V18165 F-60 Min. 104 135 25 68 ¾ ¾ ¾ ¾ ¾ 0 5 0 0 0 0 1 ¾ 40 60 60 10 10 10 10 40 5 35 Max. ¾ ¾ ¾ ¾ 60 15 30 35 15 ¾ ¾ 15 15 15 15 50 16 ¾ 10,000 100,000 ¾ ¾ ¾ 10,000 ¾ ¾ ¾ MSM51V18165 F-70 Min. 124 160 30 78 ¾ ¾ ¾ ¾ ¾ 0 5 0 0 0 0 1 ¾ 50 70 70 13 13 10 13 45 5 40 Max. ¾ ¾ ¾ ¾ 70 20 35 40 20 ¾ ¾ 20 20 20 20 50 16 ¾ 10,000 100,000 ¾ ¾ ¾ 10,000 ¾ ¾ ¾ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns 13 13 15 7,8 7,8 7 7 3 4, 5, 6 4,5 4,6 4,13 4 4 Parameter Unit Note RAS Hold Time from CAS Precharge tRHCP No. 6/14 AC Characteristic (2/2) (VCC = 3.3V ± 0.3V, Ta = 0°C to 70°C) Note1,2,3 MSM51V18165 F-50 Symbol Min. OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR 5 11 9 0 7 0 7 25 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 Max. ¾ 37 25 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MSM51V18165 F-60 Min. 5 14 12 0 10 0 10 30 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 Max. ¾ 45 30 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ MSM51V18165 F-70 Unit Note Min. 5 14 12 0 10 0 13 35 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 Max. ¾ 50 35 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 12 12 13 14 11,12 11,12 12 9,12 9 10,12 12 12 12 5 6 Parameter No. 7/14 Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization cycles(RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 2ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF. The output timing reference levels are VOH = 2.0V and VOL = 0.8V. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tCEZ, and tREZ must be satisfied for open circuit condition. tRCH or tRRH must be satisfied for a read cycle. 2. 3. 4. 5. 6. 7. 8. 9. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ³ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ³ tCWD (Min.), tRWD ³ tRWD(Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. No. 8/14 Timing Chart x Read Cycle RAS VIH VIL tCRP tRCD tRAD tRC tRAS tRP tCSH tRSH tCAS tRAL tASR tRAH tASC Column tCRP CAS VIH VIL tCAH Address VIH VIL VIH VIL VIH VIL Row tRCS tAA tROH tOEA tCAC tRAC tRRH tRCH tREZ WE OE tOEZ tCLZ Valid Data-out tCEZ DQ VOH VOL Open “H” or “L” x W rite Cycle (Early Write) RAS VIH VIL tCRP tRCD tRAD tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP CAS VIH VIL tASR tRAH tASC tCAH Address VIH VIL Row Column tCWL tWCS tWP tWCH WE VIH VIL VIH VIL VIH VIL tRWL OE tDS Valid Data-in tDH Open DQ “H” or “L” 1 R1