SI4922DY

SPICE Device Model Si4922DY Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71563 16-Apr-01 www.vishay.com 1 SPICE Device Model Si4922DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol VGS(th) ID(on) Test Conditions VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 8.8 A Typical 1.1 365 0.013 0.015 0.024 31 0.72 Unit V A Drain-Source On-State Resistance a rDS(on) VGS = 4.5 V, ID = 8.3 A VGS = 2.5 V, ID = 7.2 A Ω Forward Transconductance Diode Forward Voltage a a gfs VSD VDS = 15 V, ID = 8.8 A IS = 1.7 A, VGS = 0 V S V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. Qg Qgs Qgd td(on) tr td(off) tf trr IF = 1.7 A, di/dt = 100 A/µs VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω VDS = 15 V, VGS = 4.5 V, ID = 8.8 A 22.8 5.8 5.8 13 17 20 47 30 ns nC www.vishay.com 2 Document Number: 71563 16-Apr-01 SPICE Device Model Si4922DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71563 16-Apr-01 www.vishay.com 3