CLC427AJ

Comlinear CLC427 Dual Voltage Feedback Amplifier for Single Supply Operation August 1996 N Comlinear CLC427 Dual Voltage Feedback Amplifier for Single Supply Operation General Description The Comlinear CLC427 is a dual wideband voltage-feedback operational amplifier that is uniquely designed to provide high performance from a single power supply. This CLC427 provides near rail-to-rail operation and the common-mode input range includes the negative rail. Each of the CLC427’s amplifiers offers plenty of headroom for single-supply applications as evidenced by its 4.3Vpp output voltage from a single 5V supply. Fabricated with a high-speed complementary bipolar process, the CLC427 delivers a wide 94MHz unity-gain bandwidth, 7.5ns rise/fall time and 150V/µs slew rate. For single supply applications such as video distribution or desktop multimedia, the CLC427 offers low 0.35%, 0.55° differential gain and phase errors. Each of the CLC427’s amplifiers provides high signal fidelity with -74/-94dBc 2nd/3rd harmonics (1Vpp, 1MHz, RL=150Ω). Combining this high fidelity performance with CLC427’s quick 46ns settling time to 0.1% makes it an excellent choice for ADC buffering. With its traditional voltage-feedback architecture and high-speed performance, the CLC427 is the perfect choice for composite signal conditioning circuit functions such as active filters, integrators, differentiators, simple gain blocks and buffering. Features s s s s s s s Single +5V supply Input includes VEE 94MHz unity-gain bandwidth -74/-94dBc HD2/HD3 60mA output current 7.5ns rise/fall time (1Vpp) 46ns settling time to 0.1% Video ADC driver Desktop multimedia Single supply cable driver Instrumentation Video cards Wireless IF amplifiers Telecommunications Frequency Response vs. Vout Av = +2V/V Applications s s s s s s s Magnitude (1dB/div) 1Vpp 2Vpp 4Vpp 1 10 100 Frequency (MHz) Single Supply Response Typical Application Single +5V Supply operation +5V 0.1µF Vin 1/2 CLC427 VCC 5 4 Output Voltage (V) VEE 3 2 1 0 6.8µF + Vo + - Time (100ns/div) 50Ω 250Ω 250Ω 150Ω Vo1 VCC Vo2 Vinv2 Vnon-inv2 http://www.national.com Pinout DIP & SOIC NOTE: Vin = 0.15V to 2.3V Vinv1 Vnon-inv1 VEE © 1996 National Semiconductor Corporation Printed in the U.S.A. Electrical Characteristics PARAMETERS (Vs = +5V1, Vcm = +2.5V, Av = +2, Rf = 250W, RL = 150W to GND; unless specified) TYP 25° 48 26 94 0.1 0 0.3 0.35 0.55 7.5 46 5 150 74 62 94 75 10 4 65 2 4 17 80 0.2 10 82 82 7 1 700 0.07 3.7 0 4.5 0.35 4.8 0.45 60 36 25° 32 16 0.5 0.5 0.6 0.7 2 13 70 13 90 – 55 – 65 12.5 5 59 7 – 30 – 5 – 65 55 8.5 2 500 0.15 3.45 0 4.35 0.5 4.6 0.65 50 20 7 4 MIN/MAX RATINGS 0° to +70° -40° to +85° 28 14 0.7 0.7 0.8 – – 14 – – 83 – 52 – 63 13.6 5.5 59 8 22 36 145 6 22 64 53 8.5 2 450 0.24 3.25 0 4.3 0.5 4.55 0.7 40 16 7 4 27 11 0.8 0.8 0.9 – – 16 – – 65 – 52 – 62 14 5.7 59 10 35 45 175 7.5 27 60 50 8.5 2 360 0.7 3.15 0 4.2 0.55 4.45 0.75 34 10 7 4 UNITS NOTES CONDITIONS CLC427AJ FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo < 1.0Vpp -3dB bandwidth Vo < 3.0Vpp -3dB bandwidth AV = +1V/V Vo < 1.0Vpp rolloff 1MHz crosstalk, input referred 10MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input offset current average drift power supply rejection ratio common-mode rejection ratio supply current (per amplifier) B B A A DC DC no load B A MISCELLANEOUS PERFORMANCE input capacitance input resistance output impedance @DC input voltage range, high input voltage range, low output voltage range, high RL = 150Ω output voltage range, low RL = 150Ω output voltage range, high no load output voltage range, low no load output current source output current sink supply voltage, maximum supply voltage, minimum 1 1 transistor count = 124 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage (Vs) Iout is short circuit protected to ground common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) differential input voltage ESD tolerance (Note 3) +7V VEE to VCC +175˚C -65˚C to +150˚C +260˚C ±2V 2000V Notes A) J-level: spec is 100% tested at 25°C, sample tested at 85°C. B) J-level: spec is sample tested at 25°C. 1) Vs = VCC – VEE. 2) Tested with RL tied to +2.5V. 3) Human body model, 1.5kΩ in series with 100pF. http://www.national.com 2 Typical Performance Characteristics (Vs = +5V1, Vcm = +2.5V, Av = +2, Rf = 250 Non-Inverting Frequency Response Vo = 0.25Vpp Av = 1 Rf = 0 W, RL = 150W to GND; unless specified) 225 Inverting Frequency Response Vo = 0.25Vpp Frequency Response vs. RL Vo = 0.25Vpp Av = -1 RL = 1kΩ RL = 150Ω RL = 75Ω RL = 1kΩ 180 135 90 45 0 -45 -90 Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) Av = 4 Av = 2 Av = -5 Av = -2 Phase (deg) Phase (deg) Phase (deg) Av = 10 Av = 10 Av = 1 Av = -10 Av = -1 Av = -10 Av = -5 Av = -2 0 -45 Av = 2 Av = 4 180 135 90 45 0 -45 -90 -135 -180 -225 RL = 75Ω RL = 150Ω -135 -180 -225 1 10 100 1 10 100 0 10 100 Frequency (MHz) Frequency Response vs. Vout Frequency (MHz) Frequency Response vs. CL CL = 100pF Rs = 54.9Ω CL = 1000pF Rs = 22Ω CL = 10pF Rs = 249Ω Frequency (MHz) Open Loop Gain & Phase 100 0 -20 Gain Vo = 0.25Vpp Open Loop Gain (dB) Magnitude (1dB/div) Magnitude (1dB/div) 80 60 40 20 0 -20 0.001 -40 -60 -80 Phase (deg) Phase Vo = 4Vpp Vo = 2Vpp Vo = 1Vpp Rs 250Ω 250Ω CL 1k -100 -120 0.01 0.1 1 10 100 1 10 100 1 10 100 Frequency (MHz) Harmonic Distortion vs. Frequency -50 Vo = 1Vpp 2nd RL = 150Ω Frequency (MHz) 2nd Harmonic Distortion vs. Vout -30 RL = 150Ω Frequency (MHz) 3rd Harmonic Distortion vs. Vout -30 RL = 150Ω -60 -40 10MHz -40 Distortion (dBc) Distortion (dBc) Distortion (dBc) -70 -80 -90 2nd RL = 1kΩ -50 -60 -70 -80 -90 5MHz 2MHz -50 -60 -70 -80 -90 2MHz 5MHz 10MHz 3rd RL = 1kΩ 3rd RL = 150Ω 1MHz 0.1MHz 1MHz 0.1MHz -100 0.1 1 10 -100 0 1 2 3 4 0 1 2 3 4 Frequency (MHz) Small Signal Pulse Response Output Voltage (0.05V/div) Output Voltage (0.5V/div) Output Amplitude (Vpp) Large Signal Pulse Response 100 Output Amplitude (Vpp) Equivalent Input Noise 100 Voltage Noise (nV/Hz) Current Noise (pA/Hz) 10 Voltage = 9.5nV/√Hz 10 Current = 3.2pA/√Hz Time (20ns/div) IB, VIO, vs. Temperature 1.7 1.5 1.3 VIO Time (20ns/div) Differential Gain and Phase (3.58MHz) -10 -12 -14 2.5 RL tied to +2.5V 1 0.001 1 0.01 0.1 1 10 Frequency (MHz) PSRR, CMRR & Linear Rout vs. Frequency 2.5 2 100 80 60 40 20 Rout PSRR 25 Output Resistance (Ω) PSRR, CMRR (dB) 2 CMRR 20 15 10 5 0 Phase (deg) Gain (%) VIO (mV) 1.5 1 Phase Neg Sync 1.5 1 Gain Neg Sync IB (µA) 1.1 0.9 0.7 0.5 -40 -20 0 20 IB -16 -18 -20 -22 40 60 80 0.5 0 1 2 3 4 0.5 0 0 0.001 0.01 0.1 1 10 Temperature (°C) Number of 150Ω Loads Frequency (MHz) 3 http://www.national.com CLC427 OPERATIONS Description The CLC427 contains two single supply voltage-feedback amplifiers. The CLC427 is a dual version of the CLC423 with the following features: • Operates from a single +5V supply • Maintains near rail-to-rail performance • Includes the negative rail (0V) in the Common Mode Input Range (CMIR) • Offers low -74/-94dBc 2nd and 3rd harmonic distortion • Provides BW > 20MHz and 1MHz distortion < -50dBc at Vo = 4Vpp Single Supply Operation (VCC = +5V, VEE = GND) The CLC427 is designed to operate from 0 and 5V supplies. The specifications given in the Electrical Characteristics table are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the CMIR of the CLC427 is typically 0V to +3.7V. The typical output range with RL = 150Ω is +0.35V to +4.5V. For simple single supply operation, it is recommended that input signal levels remain above ground. For input signals that drop below ground, AC coupling and level shifting the signal are possible remedies. For input signals that remain above ground, no adjustments need to be made. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. Standard Single Supply Operation Figures 1 and 2 show the recommended non-inverting and inverting configurations for purely positive input signals. +5V 6.8µF + +5V 6.8µF + 3(5) Rb Vin Rt Rg 2(6) 1/2 CLC427 + 8 0.1µF 1(7) Vo - 4 Rf R Vo =− f Vin Rg Select R t to yield desired Rin = R t || R g Figure 2: Inverting Configuration Single Supply Operation for Inputs that go below 0V Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below ground. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V. +5V 6.8µF + Vin Cc 2.5V R 3(5) R 2(6) 1/2 CLC427 + 8 0.1µF 1(7) Vo - 4 Rf  R Vo = Vin 1+ f  + 2.5  Rg  low frequency cutoff = Rg C 1 R , where: Rin = 2πRinC c 2 R gC >> RC c R >> Rsource Figure 3: AC Coupled Non-inverting Configuration +5V 6.8µF + 2.5V R 3(5) 2(6) Vin Rt 3(5) 2(6) 1/2 CLC427 + 8 0.1µF 1(7) Vo Vin Cc Rg R 1/2 CLC427 + 8 0.1µF 1(7) Vo - - 4 Rf 4 Rf  R Vo = Vin  − f  + 2.5  Rg  low frequency cutoff = Rg R Vo = 1+ f Vin Rg 1 2πR gC c Figure 1: Non-inverting Configuration Figure 4: AC Coupled Inverting Configuration http://www.national.com 4 Crosstalk (dB) Load Termination Since the CLC427 design has been optimized for Single Supply Operation, it is more capable of sourcing rather than sinking current. For optimum performance, the load should be tied to VEE. When the load is tied to VEE, the output always sources current. Output Overdrive Recovery When the output range of an amplifier is exceeded, time is required for the amplifier to recover from this over driven condition. Figure 5 illustrates the overload recovery of the CLC427 when the output is overdriven. An input was applied in an attempt to drive the output to twice the supply rails, VCC - VEE = 10V, but the output limits. An inverting gain topology was used, see Figure 2. As indicated, the CLC427 recovers within 25ns on the rising edge and within 10ns on the falling edge. Input -40 -50 -60 -70 -80 -90 -100 1 10 100 Frequency (MHz) Figure 7: Input Referred Crosstalk vs. Frequency Output Channel B (20mV/div) Output Channel A (1V/div) Channel A Output Voltage (2V/div) Input Voltage (4V/div) Channel B Output Time (50ns/div) Figure 8: Pulsed crosstalk Time (50ns/div) Figure 5: Overdrive Recovery Channel Matching Channel matching and crosstalk rejection are largely dependent on board layout. The layout of Comlinear’s dual amplifier evaluation boards are designed to produce optimum channel matching and isolation. Channel matching for the CLC427 is shown in Figure 6. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC427 will improve stability. The Frequency Response vs. Capacitive Load plot, in the typical performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: • Quiescent Power Dissipation PQ (No Load Condition) • Total Power Dissipation PT (with Load Condition) The following steps can be taken to determine the power consumption for each CLC427 amplifier: Vout = 0.25Vpp Magnitude (0.5dB/div) Channel A Channel B 1 10 Frequency (MHz) Figure 6: Channel Matching The CLC427’s channel-to-channel isolation is better than -70dB for video frequencies of 4MHz. Input referred crosstalk vs frequency is illustrated in Figure 7. Pulsed crosstalk is shown in Figure 8. 1. Determine the quiescent power PQ = ICC (VCC – VEE) 2. Determine the RMS power at the output stage PO = (VCC – Vload) (Iload) 3. Determine the total RMS power PT = PQ + PO Add the total RMS powers for both channels to determine the power dissipated by the dual. 5 http://www.national.com The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utilizing the following equation: +5V 6.8µF + 5.1kΩ 3(5) (175° − Tamb ) θ JA Vin R1 50Ω 5.1kΩ C 390pF 2(6) 1/2 CLC427 + 8 0.1µF 1(7) Vo - 4 R2 3.16kΩ where: Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC427 (730038 - DIP, 730036SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: 1. Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. 2. Place the 6.8µF capacitors within 0.75 inches of the power pins. 3. Place the 0.1µF capacitors within 0.1 inches of the power pins. 4. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. C 390pF R2 = R1 = Q π fr c R2 4Q 2 fr = resonant frequency A = 2Q 2 A = mid− band gain Figure 9: Bandpass Filter Topology 40 30.6dB 940kHz 30 Magnitude (dB) 20 10 0 -10 1 10 Frequency (MHz) Figure 10: Bandpass Response Distribution Amplifier Figure 11 illustrates a distribution amplifier. The topology utilizes the dual amplifier package. The input is AC coupled and the non-inverting terminals of both amplifiers are biased at 2.5V. +5V 6.8µF + Applications Circuits Typical Application Circuit The typical application shown on the front page illustrates the near rail-to-rail performance of the CLC427. Multiple Feedback Bandpass Filter Figure 9 illustrates a bandpass filter and design equations. The circuit operates from a single supply of +5V. The voltage divider biases the non-inverting input to 2.5V. The input is AC coupled to prevent the need for level shifting the input signal at the source. Use the design equations to determine R1 and R2 based on the desired Q and center frequency. This example illustrates a bandpass filter with Q = 4 and center frequency fc = 1MHz. Figure 10 indicates the filter response. Vin CC Ro R 3(5) R 2(6) 1/2 CLC427 + 8 0.1µF 1(7) Ro Zo Vo1 Ro - Rf Rg C 3(5) 2(6) 1/2 CLC427 + 1(7) Ro Zo Vo2 Ro - 4 Rf Rg C Figure 11: Distribution Amplifier http://www.national.com 6 DC Coupled Single-to-Differential Converter A DC coupled single-to-differential converter is illustrated in Figure 12. +5V 6.8µF + Ordering Information Model CLC427AJP CLC427AJE Temperature Range -40˚C to +85˚C -40˚C to +85˚C Description 8-pin PDIP 8-pin SOIC Package Thermal Resistance 1(7) Vin Rt 250Ω 2kΩ 3kΩ 3(5) 2(6) 1/2 CLC427 + 8 0.1µF VH (Av = +1V/V) Vo Package Plastic (AJP) Surface Mount (AJE) qJC qJA - 75˚/W 90˚/W 90˚/W 115˚/W 3(5) 2(6) 1/2 CLC427 + 1(7) VL (Av = -1V/V) Vo = VH – VL Vo = 2Vin - 4 250Ω Figure 12: Single-to-Differential Converter 7 http://www.national.com Comlinear CLC427, Dual Voltage Feedback Amplifier for Single Supply Operation Customer Design Applications Support National Semiconductor is committed to design excellence. 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