CLC450AJ

CLC450 Single Supply, Low-Power, High Output, Current Feedback Amp June 1999 N CLC450 Single Supply, Low-Power, High Output, Current Feedback Amplifier General Description The CLC450 has a new output stage that delivers high output drive current (100mA), but consumes minimal quiescent supply current (1.5mA) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear-phase response up to one half of the -3dB frequency. The CLC450 offers superior dynamic performance with a 100MHz small-signal bandwidth, 280V/µs slew rate and 6.1ns rise/fall times (2Vstep). The combination of low quiescent power, high output current drive, and high-speed performance make the CLC450 well suited for many battery-powered personal communication/computing systems. The ability to drive low-impedance, highly capacitive loads, makes the CLC450 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC450 will drive a 100Ω load with only -75/-64dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -70/-60dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high-resolution A/D converters, the CLC450 provides excellent -79/-75dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. Available in SOT23-5, the CLC450 is ideal for applications where space is critical. +5V 6.8µF + Features s s s s s s s s s 100mA output current 1.5mA supply current 100MHz bandwidth (Av = +2) -79/-75dBc HD2/HD3 (1MHz) 20ns settling to 0.05% 280V/µs slew rate Stable for capacitive loads up to 1000pf Single 5V to ±5V supplies Available in Tiny SOT23-5 package Coaxial cable driver Twisted pair driver Transformer/Coil Driver High capacitive load driver Video line driver Portable/battery-powered applications A/D driver Maximum Output Voltage vs. RL 10 9 Applications s s s s s s s Output Voltage (Vpp) 8 7 6 5 4 3 2 1 10 100 1000 Vs = +5V VCC = ±5V RL (Ω) Response After 10m of Cable Vin = 10MHz, 0.5Vpp Typical Application Single Supply Cable Driver 10m of 75Ω Coaxial Cable 100mV/div Vin 0.1µF 5kΩ 5kΩ 3 + - 7 0.1µF 6 CLC450 2 4 75Ω 0.1µF Vo 75Ω 1kΩ 1kΩ 0.1µF Vo VCC 20ns/div Pinout SOT23-5 VEE Vinv Pinout DIP & SOIC Vnon-inv © 1999 National Semiconductor Corporation Printed in the U.S.A. VEE http://www.national.com +5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, Rf = 1kΩ, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) CONDITIONS CLC450AJ TYP +25°C 100 75 30 0 0.1 0.2 6.1 20 16 280 -75 -79 -62 -64 -75 -52 3.0 6.9 8.5 1 7 5 25 3 10 54 51 1.5 0.46 1.5 4.2 0.8 4.0 1.0 4.1 0.9 100 55 MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C 85 60 25 0.5 0.3 0.4 8.5 30 20 200 – – -58 – – -48 3.7 9 11 4 – 12 – 10 – 50 47 1.7 0.37 2.3 4.1 0.9 3.9 1.1 4.0 1.0 80 90 75 55 20 0.9 0.4 0.5 9.2 50 22 185 – – -57 – – -46 4.0 10 12 5 15 15 60 12 20 48 45 1.8 0.33 2.3 4.1 0.9 3.9 1.1 4.0 1.0 65 90 70 50 20 1.0 0.5 0.5 10.0 80 22 170 – – -56 – – -46 4.0 10 12 6 15 16 60 13 20 48 45 1.8 0.33 2.3 4.0 1.0 3.8 1.2 3.9 1.1 40 120 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo < 0.5Vpp Vo < 2.0Vpp -0.1dB bandwidth Vo < 0.5Vpp gain peaking 1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC B Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) J-level: spec is 100% tested at +25°C. B) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE Absolute Maximum Ratings supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) +14V 140mA VEE to VCC +150°C -65°C to +150°C +300°C 500V Reliability Information Transistor Count MTBF (based on limited test data) 49 31Mhr http://www.national.com 2 ±5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, Rf = 1kΩ, RL = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC450AJ TYP +25°C 135 55 40 0 0.1 0.1 0.03 0.3 4.4 15 15 370 -86 -85 -68 -65 -74 -52 3.0 6.9 8.5 2 8 5 40 5 20 56 53 1.6 0.62 1.2 ±4.2 ±3.8 ±4.0 130 40 GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C 115 45 30 0.5 0.3 0.3 – – 5.8 25 20 280 – – -64 – – -48 3.7 9 11 6 – 12 – 13 – 51 48 1.9 0.50 1.8 ±4.1 ±3.6 ±3.8 100 70 105 42 25 0.9 0.4 0.4 – – 6.2 40 22 260 – – -61 – – -46 4.0 10 12 7 20 16 70 15 45 49 46 2.0 0.45 1.8 ±4.1 ±3.6 ±3.8 80 70 100 40 25 1.0 0.5 0.4 – – 6.8 60 22 240 – – -60 – – -46 4.0 10 12 8 20 17 70 16 45 49 46 2.0 0.45 1.8 ±4.0 ±3.5 ±3.7 50 90 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo < 1.0Vpp Vo < 4.0Vpp -0.1dB bandwidth Vo < 1.0Vpp gain peaking 1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift input bias current (inverting) average drift power supply rejection ratio common-mode rejection ratio supply current DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC B Notes B) The short circuit current can exceed the maximum safe output current. Model CLC450AJP CLC450AJE CLC450AJM5 CLC450ALC Ordering Information Temperature Range -40°C -40°C -40°C -40°C to to to to +85°C +85°C +85°C +85°C Description 8-pin PDIP 8-pin SOIC 5-pin SOT dice Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) Surface Mount (AJM5) Dice (ALC) θJC 115°C/W 130°C/W 140°C/W 25°C/W θJA 125°C/W 150°C/W 210°C/W – 3 http://www.national.com +5V Typical Performance (A Non-Inverting Frequency Response Normalized Magnitude (1dB/div) Vo = 1Vpp Gain Av = 2 Rf = 845Ω Av = 1 Rf = 1.1kΩ v = +2, Rf = 1kΩ, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Phase (deg) Phase (deg) Vo = 1Vpp Gain Av = -2 Rf = 866Ω Av = -1 Rf = 1.1kΩ Frequency Response vs. RL Phase (deg) Vo = 1Vpp RL = 1kΩ Magnitude (1dB/div) RL = 100Ω Gain Phase 0 -90 -180 -270 -360 -450 100M Phase -180 -270 -360 -450 -540 -630 100M Phase RL = 25Ω 0 -90 -180 -270 -360 -450 Av = 5 Rf = 845Ω Av = 10 Rf = 845Ω Av = -5 Rf = 825Ω Av = -10 Rf = 787Ω 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo Frequency (Hz) Frequency Response vs. CL 140 Vo = 1Vpp Frequency (Hz) Open Loop Transimpedance Gain, Z(s) 225 Phase Gain Magnitude (1dB/div) Magnitude (1dB/div) Vo = 1Vpp Magnitude (dBΩ) CL = 10pF Rs = 46.4Ω CL = 100pF Rs = 20Ω CL = 1000pF Rs = 6.7Ω + - 120 100 80 60 40 180 Phase (deg) Vo = 2.5Vpp Vo = 2Vpp 135 90 45 0 100M Rs 1k CL 1k Vo = 0.1Vpp 1k 1M 10M 100M 1M 10M 100M 1k 10k 100k 1M 10M Frequency (Hz) Gain Flatness 4 Frequency (Hz) Equivalent Input Noise 12 11 3.5 Inverting Current 8.5pA/√Hz Frequency (Hz) 2nd & 3rd Harmonic Distortion -40 Vo = 2Vpp 3rd RL = 100Ω Noise Voltage (nV/√Hz) Magnitude (0.05dB/div) Noise Current (pA/√Hz) -50 10 9 8 7 6 0.1k 1k 10k 100k 1M 10M Distortion (dBc) -60 -70 -80 2nd RL = 1kΩ 2nd RL = 100Ω 3rd RL = 1kΩ 3 Voltage 3.0nV/√Hz Non-Inverting Current 6.9pA/√Hz 2.5 10 20 30 -90 1M 10M Frequency (MHz) 2nd Harmonic Distortion, RL = 25Ω -30 -40 -20 -30 Frequency (Hz) 3rd Harmonic Distortion, RL = 25Ω Frequency (Hz) 2nd Harmonic Distortion, RL = 100Ω Distortion (dBc) Distortion (dBc) 10MHz 10MHz -50 5MHz -40 -50 -60 5MHz 2MHz 1MHz Distortion (dBc) -40 -50 -60 -70 -80 10MHz 5MHz 2MHz 1MHz -60 -70 -80 0 0.5 2MHz 1MHz -70 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 -90 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 100Ω -30 -55 -60 Output Amplitude (Vpp) 2nd Harmonic Distortion, RL = 1kΩ -50 -55 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 1kΩ 10MHz 10MHz Distortion (dBc) Distortion (dBc) 10MHz -70 -75 Distortion (dBc) -40 -65 5MHz -60 -65 5MHz -50 5MHz 2MHz -70 -75 -80 -85 1MHz 2MHz -60 2MHz 1MHz -80 1MHz -85 -90 -70 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.55 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Output Amplitude (Vpp) Output Amplitude (Vpp) http://www.national.com 4 +5V Typical Performance (A Closed Loop Output Resistance 100 v = +2, Rf = 1kΩ, RL = 100Ω, Vs = + 5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Recommended Rs vs. CL 50 + Large & Small Signal Pulse Response Output Voltage (0.5V/div) Rs Output Resistance (Ω) 40 10 30 20 10 0 10k 100k 1M 10M 100M 10 100 - 1k 1k CL 1k Large Signal Small Signal 1 0.1 0.01 Rs (Ω) 1000 Time (20ns/div) Frequency (Hz) PSRR & CMRR 60 PSRR CL (pF) IBI, IBN, Vos vs. Temperature -0.6 6 5 5 4.5 IBN Vos Maximum Output Voltage vs. RL PSRR & CMRR (dB) Output Voltage (Vpp) 50 40 30 20 10 0 1k Offset Voltage Vos (mV) CMRR -0.7 -0.8 -0.9 IBI 4 3.5 3 2.5 2 1.5 IBI, IBN (µA) 4 3 2 1 -100 -50 0 50 100 150 -1 -1.1 1 10 100 1000 10k 100k 1M 10M 100M Frequency (Hz) Temperature (°C) RL (Ω) ±5V Typical Performance (A Non-Inverting Frequency Response Normalized Magnitude (1dB/div) Vo = 1Vpp Gain Av = +1 Rf = 1.3kΩ Av = +2 Rf = 845Ω v = +2, Rf = 1kΩ, RL = 100Ω, VCC = ± 5V, unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Phase (deg) Phase (deg) Vo = 1Vpp Gain Av = -1 Rf = 866Ω Av = -2 Rf = 825Ω Frequency Response vs. RL Phase (deg) Vo = 1Vpp RL = 1kΩ Magnitude (1dB/div) RL = 100Ω Gain Phase 0 -90 -180 -270 -360 -450 100M Phase -180 -270 -360 -450 -540 -630 100M Phase RL = 25Ω 0 -90 -180 -270 -360 -450 Av = +5 Rf = 825Ω Av = +10 Rf = 845Ω Av = -5 Rf = 825Ω Av = -10 Rf = 787Ω 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo Frequency (Hz) Frequency Response vs. CL Vo = 1Vpp Frequency (Hz) Gain Flatness Magnitude (1dB/div) Magnitude (1dB/div) Vo = 1Vpp CL = 10pF Rs = 68.1Ω CL = 100pF Rs = 17.4Ω CL = 1000pF Rs = 6.7Ω + - Vo = 5Vpp Vo = 2Vpp Rs 1k CL 1k Vo = 0.1Vpp 1k 1M 10M 100M 1M Magnitude (0.05dB/div) 10M 100M 10 20 30 Frequency (Hz) Frequency (Hz) Frequency (MHz) 5 http://www.national.com ±5V Typical Performance (A Small Signal Pulse Response Output Voltage (200mV/div) Av = +2 v = +2, Rf = 1kΩ, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Large Signal Pulse Response -40 Vo = 2Vpp 2nd & 3rd Harmonic Distortion 3rd RL = 100Ω 3rd RL = 1kΩ Output Voltage (1V/div) Av = +2 -50 Distortion (dBc) -60 -70 -80 -90 2nd RL = 100Ω 2nd RL = 1kΩ Av = -2 Av = -2 Time (20ns/div) 2nd Harmonic Distortion, RL = 25Ω -30 10MHz Time (20ns/div) 3rd Harmonic Distortion, RL = 25Ω -20 10MHz 0.1M 1M 10M Frequency (Hz) 2nd Harmonic Distortion, RL = 100Ω -50 -55 -40 Distortion (dBc) Distortion (dBc) -50 2MHz -40 -50 -60 -70 5MHz Distortion (dBc) 5MHz -30 -60 10MHz -65 -70 -75 -80 -85 2MHz 1MHz 5MHz -60 -70 -80 0 1 2 3 4 5 1MHz 2MHz 1MHz 0 1 2 3 4 5 0 1 2 3 4 5 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 100Ω -30 -40 -60 -65 Output Amplitude (Vpp) 2nd Harmonic Distortion, RL = 1kΩ -50 -55 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 1kΩ 10MHz 5MHz Distortion (dBc) Distortion (dBc) -50 -60 -70 -80 0 1 2 10MHz Distortion (dBc) -70 -75 5MHz -60 -65 -70 -75 -80 -85 -90 10MHz 2MHz 5MHz 2MHz 1MHz -80 -85 -90 -95 2MHz 1MHz 1MHz 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 Output Amplitude (Vpp) Recommended Rs vs. CL 70 + Output Amplitude (Vpp) Maximum Output Voltage vs. RL 10 -0.01 Output Amplitude (Vpp) Differential Gain & Phase -0.2 f = 3.58MHz Gain Positive Sync 60 - Rs 1k 9 Output Voltage (Vpp) CL RL 50 8 -0.015 Gain Negative Sync -0.3 1k Phase (deg) Gain (%) Rs (Ω) 40 30 20 10 0 10 100 1000 7 6 5 4 3 2 10 100 1000 -0.02 -0.025 Phase Positive Sync -0.4 -0.5 -0.6 Phase Negative Sync -0.03 -0.035 1 2 3 4 -0.7 CL (pF) IBI, IBN, Vos vs. Temperature 1.5 12 0 Vo = 2Vstep RL (Ω) Short Term Settling Time 0.2 0.15 Number of 150Ω Loads Long Term Settling Time Vo = 2Vstep Offset Voltage Vos (mV) Vo (% Output Step) 1 IBI 8 -0.05 Vo (% Output Step) 0.1 0.05 0 -0.05 -0.1 -0.15 IBI, IBN (µA) 0.5 IBN Vos 4 -0.1 0 0 -0.15 -0.5 -100 -50 0 50 100 150 -4 -0.2 1 10 100 1000 -0.2 1µ 10µ 100µ 1m 10m 100m 1 Temperature (°C) Time (ns) Time (s) http://www.national.com 6 CLC450 OPERATION The CLC450 is a current feedback amplifier built in an advanced complementary bipolar process. The CLC450 operates from a single 5V supply or dual ±5V supplies. Operating from a single supply, the CLC450 has the following features: s s s Vo = Vin where: s s s Av Rf 1+ Z(jω ) Equation 1 Provides 100mA of output current while consuming 7.5mW of power Offers low -79/-75dB 2nd and 3rd harmonic distortion Provides BW > 60MHz and 1MHz distortion < -65dBc at Vo = 2.5Vpp Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC450’s open loop transimpedance gain Z( jω ) is the loop gain Rf s The CLC450 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. Current Feedback Amplifiers Some of the key features of current feedback technology are: s Independence of AC bandwidth and voltage gain s Inherently stable at unity gain s Adjustable frequency response with feedback resistor s High slew rate s Fast settling Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: s s s s s Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity Refer to the Feedback Resistor Selection section for more details on selecting a feedback resistor value. CLC450 DESIGN INFORMATION Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC450 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. VCC Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. DC Coupled Single Supply Operation Figures 1 and 2 show the recommended non-inverting and inverting configurations for input signals that remain above 0.8V DC. Note: Rb, provides DC bias for non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. VCC 6.8µF + 6.8µF + Vin Rt Vcm 3 2 + - 7 0.1µF 6 3 CLC450 4 Vo Rb 2 + - 7 0.1µF 6 CLC450 4 Vo RL Vcm Rf RL Vin Vcm Vcm Rt Vcm Rg Rf Rg Vcm R Vo = A v = 1+ f Vin Rg R Vo = Av = − f Vin Rg Select Rt to yield desired Rin = Rt || Rg Figure 1: Non-Inverting Configuration 7 Figure 2: Inverting Configuration http://www.national.com AC Coupled Single Supply Operation Figures 3 and 4 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + VCC 6.8µF + Rb 3 + - 7 0.1µF 6 CLC450 2 Vo Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt || Rg. Vin Rg 4 Rf 0.1µF + Rt Vin Cc VCC 2 R 3 + - 7 0.1µF 6 R 2 CLC450 4 Vo 6.8µF VEE Rf Figure 6: Dual Supply Inverting Configuration Feedback Resistor Selection The feedback resistor, Rf, affects the loop gain and frequency response of a current feedback amplifier. Optimum performance of the CLC450, at a gain of +2V/V, is achieved with Rf equal to 1kΩ. The frequency response plots in the Typical Performance sections illustrate the recommended Rf for several gains. These recommended values of Rf provide the maximum bandwidth with minimal peaking. Within limits, Rf can be adjusted to optimize the frequency response. s  R Vo = Vin 1 + f  + 2.5 Rg   low frequency cutoff = Rg C 1 R , where: Rin = 2πRinC c 2 R >> R source Figure 3: AC Coupled Non-Inverting Configuration VCC 6.8µF + VCC 2 Vin Cc Rg R 3 2 + - 7 0.1µF 6 CLC450 4 Vo s Decrease Rf to peak frequency response and extend bandwidth Increase Rf to roll off frequency response and compress bandwidth Rf R  R Vo = Vin  − f  + 2.5  Rg  low frequency cutoff = 1 2πR gC c As a rule of thumb, if the recommended Rf is doubled, then the bandwidth will be cut in half. Unity Gain Operation The recommended Rf for unity gain (+1V/V) operation is 1.5kΩ. Rg is left open. Parasitic capacitance at the inverting node may require a slight increase in Rf to maintain a flat frequency response. Bandwidth vs. Output Amplitude The bandwidth of the CLC450 is at a maximum for output voltages near 1Vpp. The bandwidth decreases for smaller and larger output amplitudes. Refer to the Frequency Response vs. Vo plots. Load Termination The CLC450 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Figure 4: AC Coupled Inverting Configuration Dual Supply Operation The CLC450 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 5 and 6. VCC 6.8µF + Vin Rt 3 + - 7 0.1µF 6 CLC450 2 4 Vo Rf 0.1µF + Rg 6.8µF VEE Figure 5: Dual Supply Non-Inverting Configuration http://www.national.com Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC450 will improve stability and settling performance. The Frequency Response vs. CL and Recommended Rs vs. CL plots, in the typical performance section, give the recommended series resistance value for optimum flatness at various capacitive loads. 8 Power (W) Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 7 shows typical inverting and non-inverting circuit configurations for matching transmission lines. R1 V1 + R4 V2 + Z0 Z0 R3 R2 Rg R5 C6 + 1.0 AJP 0.8 0.6 0.4 0.2 0 -40 -20 0 AJE SOT Z0 R6 CLC450 - Vo R7 Rf 20 40 60 80 100 120 140 160 180 Ambient Temperature (°C) Figure 8: Power Derating Curves Figure 7: Transmission Line Matching Non-inverting gain applications: s s s Connect Rg directly to ground. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides evaluation boards for the CLC450 (730013-DIP, 730027SOIC, 730068-SOT) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: s s s s Inverting gain applications: s s s Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. Power Dissipation Follow these steps to determine the power consumption of the CLC450: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP, SOIC, and SOT packages can dissipate at a given temperature is illustrated in Figure 8. The power derating curve for any CLC450 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA where Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) 9 s s Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. Evaluation Board Information Data sheets are available for the CLC730013/ CLC730027 and CLC730068 evaluation boards. The evaluation board data sheets provide: s s s Evaluation board schematics Evaluation board layouts General information about the boards The CLC730013/CLC730027 data sheet also contains tables of recommended components to evaluate several of National’s high speed amplifiers. This table for the CLC450 is illustrated below. Refer to the evaluation board data sheet for schematics and further information. Components Needed to Evaluate the CLC450 on the Evaluation Board: s s Rf, Rg - Use this product data sheet to select values Rin, Rout - Typically 50Ω (Refer to the Basic Operation section of the evaluation board data sheet for details) http://www.national.com s s s Rt - Optional resistor for inverting gain configurations (Select Rt to yield desired input impedance = Rg || Rt) C1, C2 - 0.1µF ceramic capacitors C3, C4 - 6.8µF tantalum capacitors C5, C6, C7, C8 R1 thru R8 Gain = K = 1 + Rf Rg 1 R1R 2C1C2 Corner frequency = ω c = Q= 1 R 2C 2 + R1C1 Components not used: s s The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: s s s R1C2 R1C1 + (1− K) R 2C1 R 2C 2 For R1 = R 2 = R and C1 = C2 = C ωc = Q= 1 RC 1 (3 − K) Figure 10: Design Equations Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations This example illustrates a lowpass filter with Q = 0.707 and corner frequency fc = 10MHz. A Q of 0.707 was chosen to achieve a maximally flat, Butterworth response. Figure 11 indicates the filter response. 3 Magnitude (dB) The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. -3 -9 Application Circuits Single Supply Cable Driver The typical application shown on the front page shows the CLC450 driving 10m of 75Ω coaxial cable. The CLC450 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. Single Supply Lowpass Filter Figures 9 and 10 illustrate a lowpass filter and design equations. The circuit operates from a single supply of +5V. The voltage divider biases the non-inverting input to 2.5V. And the input is AC coupled to prevent the need for level shifting the input signal at the source. Use the design equations to determine R1, R2, C1, and C2 based on the desired Q and corner frequency. +5V 0.1µF R2 C2 100pF 3 2 -15 -21 1M 10M 100M Frequency (Hz) Figure 11: Lowpass Response Twisted Pair Driver The high output current and low distortion, of the CLC450, make it well suited for driving transformers. Figure 12 illustrates a typical twisted pair driver utilizing the CLC450 and a transformer. The transformer provides the signal and its inversion for the twisted pair. Vin Rt V= Rm I:n n A v Vin 4 Zo RL UTP Req R A v = 1+ f Rg V= -n A v Vin 4 3 2 + CLC450 V = Av Vin 6 IL Vin 0.1µF 5kΩ R1 5kΩ 158Ω 158Ω + 7 Rf C1 6 + Vo - 0.1µF CLC450 4 Vo 100Ω Rg Vo = Rf 1kΩ 1n A v Vin 2 1.698kΩ Rg 0.1µF Figure 12: Twisted Pair Driver To match the line’s characteristic impedance (Zo) set: s s Figure 9: Lowpass Filter Topology http://www.national.com RL = Zo Rm = Req 10 Where Req is the transformed value of the load impedance, (RL), and is approximated by: Req = RL n2 The load current (IL) and voltage (Vo) are related to the CLC450’s maximum output voltage and current by: Vo ≤ n ⋅ Vmax IL ≤ I max n Select the transformer so that it loads the line with a value close to Zo, over the desired frequency range. The output impedance, Ro, of the CLC450 varies with frequency and can also affect the return loss. The return loss, shown below, takes into account an ideal transformer and the value of Ro. Return Loss(dB) ≈ − 20log10 n2 ⋅ Ro Zo From the above current relationship, it is obvious that an amplifier with high output drive capability is required. 11 http://www.national.com CLC450, Single Supply, Low-Power, High Output, Current Feedback Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 National Semiconductor Europe Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12