CLC451AJ

CLC451 Single Supply, Low-Power, High Output, Programmable Buffer June 1999 N CLC451 Single Supply, Low-Power, High Output, Programmable Buffer General Description The CLC451 is a low cost, high speed (85MHz) buffer that features user-programmable gains of +2, +1, and -1V/V. It has a new output stage that delivers high output drive current (100mA), but consumes minimal quiescent supply current (1.5mA) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a programmable range of gains and wide signal levels, and has a linear-phase response up to one half of the -3dB frequency. The CLC451’s internal feedback network provides an excellent gain accuracy of 0.3% The CLC451 offers superior dynamic performance with a 85MHz small-signal bandwidth, 260V/µs slew rate and 6.5ns rise/fall times (2Vstep). The combination of the small SOT23-5 package, low quiescent power, high output current drive, and high-speed performance make the CLC451 well suited for many batterypowered personal communication/computing systems. The ability to drive low-impedance, highly capacitive loads, makes the CLC451 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC451 will drive a 100Ω load with only -78/-65dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz). With a 25Ω load, and the same conditions, it produces only -55/-60dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils. When driving the input of high-resolution A/D converters, the CLC451 provides excellent -66/-75dBc second/third harmonic distortion (Av = +2, Vout = 2Vpp, f = 1MHz, RL = 1kΩ) and fast settling time. Features s s s s s s s s s 100mA output current 1.5mA supply current 85MHz bandwidth (Av = +2) -66/-75dBc HD2/HD3 (1MHz) 25ns settling to 0.05% 260V/µs slew rate Stable for capacitive loads up to 1000pF Single 5V to ±5V supplies Available in Tiny SOT23-5 package Coaxial cable driver Twisted pair driver Transformer/Coil Driver High capacitive load driver Video line driver Portable/battery-powered applications A/D driver Maximum Output Voltage vs. RL 10 9 Applications s s s s s s s Output Voltage (Vpp) 8 7 6 5 4 3 2 1 10 100 1000 Vs = +5V VCC = ±5V RL (Ω) Response After 10m of Cable Vin = 10MHz, 0.5Vpp +5V 6.8µF +5V 1 5kΩ Vin 0.1µF 0.1µF 2 3 5kΩ 4 1kΩ 1kΩ Typical Application Single Supply Cable Driver 100mV/div + 8 7 6 0.1µF 75Ω 0.1µF 10m of 75Ω Coaxial Cable Vo 75Ω 20ns/div CLC451 5 Vo VCC 1kΩ Pinout SOT23-5 VEE Vnon-inv © 1999 National Semiconductor Corporation Printed in the U.S.A. Pinout DIP & SOIC 1kΩ 1kΩ + 1kΩ Vinv VEE http://www.national.com +5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) CONDITIONS CLC451AJ TYP +25°C 85 70 20 0 0.2 0.1 6.5 25 13 260 -78 -66 -60 -65 -75 -52 3.0 6.9 8.5 8 80 3 25 ±0.3 1000 49 51 1.5 0.5 1.5 4.2 0.8 4.0 1.0 4.1 0.9 100 400 MIN/MAX RATINGS +25°C 0 to 70°C -40 to 85°C 60 55 15 0.5 0.5 0.4 9.0 – 15 180 -72 -60 -54 -61 -69 -48 3.7 9 11 30 – 14 – ±1.5 ±20% 46 48 1.7 0.37 2.3 4.1 0.9 3.9 1.1 4.0 1.0 80 600 55 50 13 0.9 0.7 0.5 9.7 – 18 165 -70 -58 -52 -59 -67 -46 4 10 12 37 – 17 – ±2.0 ±26% 44 46 1.8 0.33 2.3 4.0 1.0 3.8 1.2 4.0 1.0 65 600 55 45 13 1.0 0.7 0.5 10.5 – 18 150 -70 -58 -52 -59 -67 -46 4 10 12 37 – 18 – ±2.0 ±30% 44 46 1.8 0.33 2.3 4.0 1.0 3.8 1.2 3.9 1.1 40 600 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 0.5Vpp Vo = 2.0Vpp -0.1dB bandwidth Vo = 0.5Vpp gain peaking 1MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current (non-inverting) average drift gain accuracy internal resistors (Rf, Rg) power supply rejection ratio common-mode rejection ratio supply current DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) input voltage range, High input voltage range, Low output voltage range, High RL = 100Ω output voltage range, Low RL = 100Ω output voltage range, High RL = ∞ output voltage range, Low RL = ∞ output current output resistance, closed loop DC B Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes A) J-level: spec is 100% tested at +25°C. B) The short circuit current can exceed the maximum safe output current. 1) Vs = VCC - VEE Absolute Maximum Ratings supply voltage (VCC - VEE) output current (see note C) common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) +14V 140mA VEE to VCC +150°C -65°C to +150°C +300°C 500V Reliability Information Transistor Count MTBF (based on limited test data) 49 31Mhr http://www.national.com 2 ±5V Electrical Characteristics (A PARAMETERS Ambient Temperature v = +2, RL = 100Ω, VCC = ±5V, unless specified) CONDITIONS CLC451AJ TYP +25°C 100 55 20 0 0.2 0.1 0.3 0.3 5.0 20 10 350 -72 -69 -66 -65 -73 -52 3.0 6.9 8.5 3 80 1 40 ±0.3 1000 48 53 1.6 0.7 1.2 ±4.2 ±3.8 ±4.0 130 400 GUARANTEED MIN/MAX +25°C 0 to 70°C -40 to 85°C 80 45 15 0.5 0.7 0.3 – – 6.5 – 13 260 -66 -63 -60 -61 -67 -48 3.7 9 11 30 – 12 – ±1.5 ±20% 45 50 1.9 0.50 1.8 ±4.1 ±3.6 ±3.8 100 600 68 42 13 0.9 0.8 0.4 – – 7.0 – 15 240 -64 -61 -58 -59 -65 -46 4 10 12 35 – 19 – ±2.0 ±26% 43 48 2.0 0.45 1.8 ±4.1 ±3.6 ±3.8 80 600 65 40 13 1.0 0.8 0.4 – – 7.7 – 15 220 -64 -61 -58 -59 -65 -46 4 10 12 35 – 19 – ±2.0 ±30% 43 48 2.0 0.45 1.8 ±4.0 ±3.5 ±3.7 50 600 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vo = 1.0Vpp Vo = 4.0Vpp -0.1dB bandwidth Vo = 1.0Vpp gain peaking 1MHz STATIC DC PERFORMANCE output offset voltage average drift input bias current (non-inverting) average drift gain accuracy internal resistors (Rf, Rg) power supply rejection ratio common-mode rejection ratio supply current DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance (non-inverting) input capacitance (non-inverting) common-mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop DC B Notes B) The short circuit current can exceed the maximum safe output current. Model CLC451AJP CLC451AJE CLC451AJM5 CLC451ALC Ordering Information Temperature Range -40°C -40°C -40°C -40°C to to to to +85°C +85°C +85°C +85°C Description 8-pin PDIP 8-pin SOIC 5-pin SOT dice Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) Surface Mount (AJM5) Dice (ALC) θJC 105°C/W 95°C/W 140°C/W 25°C/W θJA 155°C/W 175°C/W 210°C/W – 3 http://www.national.com +5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 0.5Vpp Av = 1 Av = -1 Gain Av = 2 v = +2, RL = 100Ω, Vs = +5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Frequency Response vs. RL Vo = 0.5Vpp RL = 1kΩ RL = 100Ω Frequency Response vs. Vo (Av = 2) Phase (deg) Magnitude (1dB/div) Gain RL = 25Ω Magnitude (1dB/div) Phase (deg) Vo = 1Vpp Vo = 0.1Vpp Vo = 2.5Vpp Vo = 2Vpp Phase Av = 1 0 -45 -90 -135 -180 -225 100M Phase 0 RL = 1kΩ RL = 100Ω RL = 25Ω -90 -180 -270 -360 -450 100M Av = 2 Av = -1 1M 10M 1M 10M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo (Av = +1) Vo = 1Vpp Frequency (Hz) Frequency Response vs. Vo (Av = -1) Frequency (Hz) Frequency Response vs. CL Vo = 0.5Vpp Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) Vo = 2.5Vpp Vo = 2Vpp Vo = 1Vpp Vo = 0.1Vpp CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 21Ω CL = 1000pF Rs = 6.7Ω + - Vo = 0.1Vpp Vo = 2.5Vpp Vo = 2Vpp Rs 1k CL 1k 1k 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Gain Flatness 4 Vo = 0.5Vpp Frequency (Hz) Equivalent Input Noise 12 11 3.5 Inverting Current 8.5pA/√Hz Frequency (Hz) 2nd & 3rd Harmonic Distortion -40 Vo = 2Vpp 3rd RL = 100Ω Noise Voltage (nV/√Hz) Noise Current (pA/√Hz) Magnitude (0.05dB/div) -50 10 9 8 7 6 0.1k 1k 10k 100k 1M 10M Distortion (dBc) -60 -70 -80 -90 1M 3rd RL = 1kΩ 3 Voltage 3.0nV/√Hz Non-Inverting Current 6.9pA/√Hz 2nd RL = 1kΩ 2nd RL = 100Ω 2.5 10 20 30 10M Frequency (MHz) 2nd Harmonic Distortion, RL = 25Ω -25 -30 -20 Frequency (Hz) 3rd Harmonic Distortion, RL = 25Ω -55 -60 Frequency (Hz) 2nd Harmonic Distortion, RL = 100Ω Distortion (dBc) Distortion (dBc) -35 -40 -45 -50 -55 0 0.5 1 1.5 2 1MHz 10MHz 5MHz 2MHz 5MHz 2MHz Distortion (dBc) -30 10MHz -65 -70 10MHz 5MHz -40 -75 -80 -85 2MHz 1MHz -50 -60 0 0.5 1 1.5 2 1MHz -90 0 0.5 1 1.5 2 2.5 2.5 2.5 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 100Ω -30 -35 -60 -65 Output Amplitude (Vpp) 2nd Harmonic Distortion, RL = 1kΩ -50 -55 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 1kΩ 5MHz 10MHz Distortion (dBc) Distortion (dBc) 10MHz Distortion (dBc) -40 -45 -50 -55 -60 -65 1MHz 5MHz -60 2MHz -70 -75 -80 1MHz 10MHz -65 -70 -75 -80 1MHz 5MHz 2MHz 2MHz -70 0 0.5 1 1.5 2 2.5 -85 0 0.5 1 1.5 2 2.5 -85 0 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) Output Amplitude (Vpp) Output Amplitude (Vpp) http://www.national.com 4 +5V Typical Performance (A Closed Loop Output Resistance 100 v = +2, RL = 100Ω, Vs = + 5V1, Vcm = VEE + (Vs/2), RL tied to Vcm, unless specified) Recommended Rs vs. CL 50 + Large & Small Signal Pulse Response Output Voltage (0.5V/div) Rs Output Resistance (Ω) 40 10 30 20 10 0 10k 100k 1M 10M 100M 10 100 - 1k 1k CL 1k Large Signal Small Signal 1 0.1 0.01 Rs (Ω) 1000 Time (10ns/div) Frequency (Hz) PSRR & CMRR 60 PSRR CL (pF) IBN, Vos vs. Temperature -0.6 6 5 4 3 2 1 -100 -50 0 50 100 150 5 4.5 IBN Vos Maximum Output Voltage vs. RL PSRR & CMRR (dB) Output Voltage (Vpp) 50 40 30 20 10 0 1k Offset Voltage Vos (mV) CMRR -0.7 -0.8 -0.9 -1 -1.1 4 3.5 3 2.5 2 1.5 1 10 100 1000 IBN (µA) 10k 100k 1M 10M 100M Frequency (Hz) Temperature (°C) RL (Ω) ±5V Typical Performance (A Frequency Response Normalized Magnitude (1dB/div) Vo = 1Vpp Gain Av = +1 Phase Av = -1 v = +2, RL = 100Ω, VCC = ± 5V, unless specified) Frequency Response vs. RL Vo = 1Vpp RL = 100Ω RL = 1kΩ Frequency Response vs. Vo (Av = 2) Phase (deg) Magnitude (1dB/div) Magnitude (1dB/div) Phase (deg) 0 -45 -90 -135 -180 -225 Gain Vo = 1Vpp Phase 0 -90 RL = 25Ω Av = 2 -180 -270 -360 -450 Vo = 2Vpp Vo = 0.1Vpp Vo = 5Vpp 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency Response vs. Vo (Av = +1) Vo = 1Vpp Frequency (Hz) Frequency Response vs. Vo (Av = -1) Vo = 2Vpp Frequency (Hz) Frequency Response vs. CL Vo = 1Vpp Magnitude (1dB/div) Magnitude (1dB/div) Magnitude (1dB/div) CL = 10pF Rs = 49.9Ω CL = 100pF Rs = 17.4Ω CL = 1000pF Rs = 6.7Ω + - Vo = 1Vpp Vo = 0.1Vpp Vo = 2Vpp Vo = 0.1Vpp Vo = 5Vpp Rs 1k CL 1k 1k 1M 10M 100M 1M 10M 100M 1M 10M 100M Frequency (Hz) Frequency (Hz) Frequency (Hz) 5 http://www.national.com ±5V Typical Performance (A Gain Flatness Vo = 1Vpp v = +2, RL = 100Ω, VCC = ± 5V, unless specified) Large & Small Signal Pulse Response -40 Vo = 2Vpp 2nd & 3rd Harmonic Distortion 3rd RL = 100Ω 3rd RL = 1kΩ Output Voltage (0.5V/div) Magnitude (0.05dB/div) Large Signal Small Signal -50 Distortion (dBc) -60 -70 -80 -90 2nd RL = 1kΩ 2nd RL = 100Ω 0 5 10 15 20 25 30 Time (10ns/div) 3rd Harmonic Distortion, RL = 25Ω -25 -58 10MHz 1M 10M Frequency (MHz) 2nd Harmonic Distortion, RL = 25Ω -30 10MHz Frequency (Hz) 2nd Harmonic Distortion, RL = 100Ω 10MHz -35 -30 -60 Distortion (dBc) Distortion (dBc) -40 -45 -50 -55 -60 0 1 2 3 4 5 2MHz 5MHz Distortion (dBc) 5MHz -35 -40 -45 -50 -55 -60 0 1 2 3 -62 -64 -66 2MHz 5MHz 2MHz -68 -70 -72 -74 1MHz 1MHz 1MHz 4 5 0 1 2 3 4 5 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 100Ω -30 -40 -60 -65 Output Amplitude (Vpp) 2nd Harmonic Distortion, RL = 1kΩ -50 -55 Output Amplitude (Vpp) 3rd Harmonic Distortion, RL = 1kΩ 10MHz Distortion (dBc) Distortion (dBc) -50 -60 -70 -80 0 1 2 3 10MHz -70 -75 2MHz Distortion (dBc) -60 -65 -70 2MHz 5MHz 5MHz 5MHz 2MHz 1MHz 10MHz -75 -80 1MHz -80 1MHz -85 4 5 0 1 2 3 4 5 -85 0 1 2 3 4 5 Output Amplitude (Vpp) Recommended Rs vs. CL 50 + Output Amplitude (Vpp) Maximum Output Voltage vs. RL 10 -0.1 Output Amplitude (Vpp) Differential Gain & Phase -0.3 f = 3.58MHz Rs 9 Output Voltage (Vpp) 40 30 20 10 0 10 100 - 1k 1k CL 1k -0.2 -0.3 8 Gain Positive Sync -0.4 -0.5 Phase (deg) Gain (%) Rs (Ω) 7 6 5 4 3 2 Gain Negative Sync -0.4 -0.5 Phase Positive Sync -0.6 -0.7 -0.8 Phase Negative Sync -0.6 -0.7 10 100 1000 1 2 3 4 -0.9 1000 CL (pF) IBN, Vos vs. Temperature 1.5 12 0.2 RL (Ω) Short Term Settling Time 0.2 Vo = 2Vstep Number of 150Ω Loads Long Term Settling Time Vo = 2Vstep Offset Voltage Vos (mV) 0.15 Vo (% Output Step) Vo (% Output Step) 1 8 0.1 0.1 0.05 0 -0.05 -0.1 -0.15 IBN (µA) 0.5 IBN Vos 4 0 0 0 -0.1 -0.5 -100 -50 0 50 100 150 -4 -0.2 1 10 100 1000 -0.2 1µ 10µ 100µ 1m 10m 100m 1 Temperature (°C) Time (ns) Time (s) http://www.national.com 6 CLC451 Operation The CLC451 is a current feedback buffer built in an advanced complementary bipolar process. The CLC451 operates from a single 5V supply or dual ±5V supplies. Operating from a single 5V supply, the CLC451 has the following features: s s s s Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1. Vo = Vin where: s s s Gains of +1, -1, and 2V/V are achievable without external resistors Provides 100mA of output current while consuming only 7.5mW of power Offers low -66/-75dBc 2nd and 3rd harmonic distortion Provides BW > 60MHz and 1MHz distortion < -55dBc at Vo = 2Vpp Av Rf 1+ Z(jω ) Equation 1 Av is the closed loop DC voltage gain Rf is the feedback resistor Z(jω) is the CLC451’s open loop transimpedance gain Z( jω ) is the loop gain Rf The CLC451 performance is further enhanced in ±5V supply applications as indicated in the ±5V Electrical Characteristics table and ±5V Typical Performance plots. If gains other than +1, -1, or +2V/V are required, then the CLC450 can be used. The CLC450 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors. Current Feedback Amplifiers Some of the key features of current feedback technology are: s s s s s s The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing Rf has the following affects: s s s s s Independence of AC bandwidth and voltage gain Inherently stable at unity gain Adjustable frequency response with feedback resistor High slew rate Fast settling Decreases loop gain Decreases bandwidth Reduces gain peaking Lowers pulse response overshoot Affects frequency response phase linearity CLC451 Design Information Closed Loop Gain Selection The CLC451 is a current feedback op amp with Rf = Rg = 1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and -1V/V by connecting pins 2 and 3 as described in the chart below. Gain Av -1V/V +1V/V +2V/V Input Connections Non-Inverting (pin3) Inverting (pin2) ground input signal input signal input signal NC (open) ground Single Supply Operation (VCC = +5V, VEE = GND) The specifications given in the +5V Electrical Characteristics table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcm is the voltage around which the inputs are applied and the output voltages are specified. Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC451 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections. DC Coupled Single Supply Operation Figures 1, 2, and 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC. The gain accuracy of the CLC451 is excellent and stable over temperature change. The internal gain setting resistors, Rf and Rg are diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of ˜ 2000ppm/°C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer. 7 http://www.national.com Note: Rb provides DC bias for the non-inverting input. Rb, RL and Rt are tied to Vcm for minimum power consumption and maximum output swing. VCC 6.8µF + 1 Vin Rt Rb Vcm Vcm 2 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ. The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC ÷ 2 = 2.5V (For VCC = +5V). VCC 6.8µF + CLC451 5 VCC Vin CC R 1 2 3 1kΩ 1kΩ 8 7 6 Vo 0.1µF Figure 1: DC Coupled, Av = -1V/V Configuration Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing. R 4 CLC451 5 1 , 2πRinCC R >> R source VCC 6.8µF + Vo = Vin + 2.5 Low frequency cutoff = where Rin = R 2 1 2 Vin Rt Vcm 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm VCC Vin CC RC R 6.8µF + Figure 5: AC Coupled, Av = +1V/V Configuration VCC 6.8µF + CLC451 5 1 2 3 4 1kΩ 1kΩ 8 7 6 Vo 0.1µF Figure 2: DC Coupled, Av = +1V/V Configuration Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing. VCC CLC451 5 1 , 2πRinCC R >> R source 1 Vcm Vin Rt Vcm 2 3 4 1kΩ 1kΩ 8 7 6 0.1µF Vo RL Vcm Vo = 2Vin + 2.5 Low frequency cutoff = where Rin = R 2 CLC451 5 Figure 6: AC Coupled, Av = +2V/V Configuration Dual Supply Operation The CLC451 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 7, 8 and 9. VCC 6.8µF + Figure 3: DC Coupled, Av = +2V/V Configuration AC Coupled Single Supply Operation Figures 4, 5, and 6 show possible non-inverting and inverting configurations for input signals that go below 0.8V DC. VCC Vin CC VCC R 3 R 4 6 1 2 1kΩ 1kΩ 1 6.8µF + 8 1kΩ 1kΩ Vin Rt Rb 2 3 4 + 7 6 0.1µF Vo 8 7 Vo 0.1µF CLC451 5 CLC451 6.8µF Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ. 5 1 , 2πR gCC Vo = − Vin + 2.5 Low frequency cutoff = where Rg = 1kΩ. 0.1µF VEE Figure 4: AC Coupled, Av = -1V/V Configuration 8 Figure 7: Dual Supply, Av = -1V/V Configuration http://www.national.com VCC 6.8µF + Figure 10 shows typical inverting and non-inverting circuit configurations for matching transmission lines. Non-inverting gain applications: 1 2 Vin Rt 3 4 + 1kΩ 1kΩ 8 7 6 0.1µF Vo s s s CLC451 5 6.8µF Connect pin 2 as indicated in the table in the Closed Loop Gain Selection section. Make R1, R2, R6, and R7 equal to Zo. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. Inverting gain applications: 0.1µF VEE s s s Figure 8: Dual Supply, Av = +1V/V Configuration VCC 6.8µF + Connect R3 directly to ground. Make the resistors R4, R6, and R7 equal to Zo. Make R5 II Rg = Zo. 1 2 Vin Rt 3 4 + 1kΩ 1kΩ 8 7 6 0.1µF Vo The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. C6 compensates for the increase of the amplifier’s output impedance with frequency. 1 R4 Z0 2 R5 R1 V2 + Z0 R3 R2 3 4 1kΩ 1kΩ 8 7 6 C6 Z0 Vo R7 CLC451 5 6.8µF V1 + - CLC451 R6 5 0.1µF VEE Figure 10: Transmission Line Matching Power Dissipation Follow these steps to determine the power consumption of the CLC451: 1. Calculate the quiescent (no-load) power: Pamp = ICC (VCC - VEE) 2. Calculate the RMS power at the output stage: Po = (VCC - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total RMS power: Pt = Pamp + Po The maximum power that the DIP, SOIC, and SOT packages can dissipate at a given temperature is illustrated in Figure 11. The power derating curve for any CLC451 package can be derived by utilizing the following equation: (175° − Tamb ) θ JA Figure 9: Dual Supply, Av = +2V/V Configuration Bandwidth vs. Output Amplitude The bandwidth of the CLC451 is at a maximum for output voltages near 1Vpp. The bandwidth decreases for smaller and larger output amplitudes. Refer to the Frequency Response vs. Vo plots. Load Termination The CLC451 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm. Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC451 will improve stability and settling performance. The Frequency Response vs. CL and Recommended Rs vs. CL plots, in the typical performance section, give the recommended series resistance value for optimum flatness at various capacitive loads. Transmission Line Matching One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. where Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) 9 http://www.national.com 1.0 AJP s AJE SOT 0.8 Power (W) s s 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 140 160 180 Rt - Optional resistor for inverting gain configurations (Select Rt to yield desired input impedance = Rg || Rt) C1, C2 - 0.1µF ceramic capacitors C3, C4 - 6.8µF tantalum capacitors C5, C6, C7, C8 R1 thru R8 Components not used: s s Ambient Temperature (°C) Figure 11: Power Derating Curve Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC451 (CLC730013-DIP, CLC730027-SOIC, CLC730068-SOT) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout: The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin. Special Evaluation Board Considerations for the CLC451 To optimize off-isolation of the CLC451, cut the Rf trace on both the CLC730013 and the CLC730027 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 12 shows where to cut both evaluation boards for improved off-isolation. OUT + C3 C4 R2 R8 RF C1 R7 C5 ROUT C6 C2 R6 R3 R1 s s s s s s Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. Place the 6.8µF capacitors within 0.75 inches of the power pins. Place the 0.1µF capacitors less than 0.1 inches from the power pins. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets. + C8 R5 C7 RIN A National Semiconductor Company Comlinear (303) 226-0500 730013 REV C -Vcc GND +Vcc IN Cut trace here Cut trace here Figure 12: Evaluation Board Changes SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Comlinear’s monolithic amplifiers that: s s Evaluation Board Information Data sheets are available for the CLC730013/ CLC730027 and CLC730068 evaluation boards. The evaluation board data sheets provide: s s s Evaluation board schematics Evaluation board layouts General information about the boards s Support Berkeley SPICE 2G and its many derivatives Reproduce typical DC, AC, Transient, and Noise performance Support room temperature simulations The CLC730013/CLC730027 data sheet also contains tables of recommended components to evaluate several of Comlinear’s high speed amplifiers. This table for the CLC451 is illustrated below. Refer to the evaluation board data sheet for schematics and further information. Components Needed to Evaluate the CLC451 on the Evaluation Board: s The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for Comlinear’s Op Amps, contains schematics and a reproduction of the readme file. Application Circuits Single Supply Cable Driver The typical application shown on the front page shows the CLC451 driving 10m of 75Ω coaxial cable. The CLC451 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. 10 Rin, Rout - Typically 50Ω (Refer to the Basic Operation section of the evaluation board data sheet for details) http://www.national.com RG R4 Twisted Pair Driver The high output current and low distortion, of the CLC451, make it well suited for driving transformers. Figure 13 illustrates a typical twisted pair driver utilizing the CLC451 and a transformer. The transformer provides the signal and its inversion for the twisted pair. 1 2 Vin Rt 3 4 + 1kΩ 1kΩ Req = RL n2 8 7 6 V = Av Vin V= Rm 1:n n A v Vin 4 Zo RL UTP Req Av = 2 V= -n A v Vin 4 IL Select the transformer so that it loads the line with a value close to Zo, over the desired frequency range. The output impedance, Ro, of the CLC451 varies with frequency and can also affect the return loss. The return loss, shown below, takes into account an ideal transformer and the value of Ro. Return Loss(dB) ≈ − 20log10 n2 ⋅ Ro Zo CLC451 5 6.8µF + Vo - 0.1µF VEE Vo = 1n A v Vin 2 Figure 13: Twisted Pair Driver To match the line’s characteristic impedance (Zo) set: s s The load current (IL) and voltage (Vo) are related to the CLC451’s maximum output voltage and current by: Vo ≤ n ⋅ Vmax IL ≤ I max n RL = Zo Rm = Req Where Req is the transformed value of the load impedance, (RL), and is approximated by: From the above current relationship, it is obvious that an amplifier with high output drive capability is required. 11 http://www.national.com CLC451, Single Supply, Low-Power, High Output, Programmable Buffer Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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