CLC416AJ

CLC416 Dual Low-Power, 120MHz Op Amp September 1998 N CLC416 Dual Low-Power, 120MHz Op Amp General Description The CLC416 is a dual, wideband (120MHz) op amp. The CLC416 consumes only 39mW per channel and can source or sink an output current of 60mA. These features make the CLC416 a versatile, high-speed solution for demanding applications that are sensitive to both power and cost. Utilizing National’s proven architectures, this dual current feedback amplifier surpasses the performance of alternative solutions and sets new standards for low power. This powerconserving dual op amp achieves low distortion with -80dBc and -80dBc second and third harmonics respectively. Many high source impedance applications will benefit from the CLC416’s 6MΩ input impedance. And finally, designers will have a bipolar part with an exceptionally low 100nA non-inverting bias current. With 0.1dB flatness to 30MHz and low differential gain and phase errors, the CLC416 is an ideal part for professional video processing and distribution. The 120MHz -3dB bandwidth (Av = +2) coupled with a 400V/µs slew rate also makes the CLC416 a perfect choice in cost-sensitive applications such as video monitors, fax machines, copiers, and CATV systems. Features s s s s s s s 0.01%, 0.03° DG, Dφ Very low input bias current: 100nA High input impedance: 6MΩ 120MHz -3dB bandwidth (Av = +2) Low power High output current: 60mA Low-cost Applications s s s s s s s Desktop video systems Video distribution Flash A/D driver High-speed driver High-source impedance applications Professional video processing High resolution monitors Frequency Response (Av = +2V/V) Typical Application Diagram Instrumentation Amplifier V1 + 1/2 CLC416 Pinout DIP & SOIC 348Ω 348Ω - 348Ω Vout = 3(V2 - V1) Vo1 Vinv1 Vnon-inv1 -VCC +VCC Vo2 Vinv2 Vnon-inv2 348Ω 348Ω 1/2 CLC416 348Ω CLC405 + R1 348Ω - V2 + © 1998 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com CLC416 Electrical Characteristics (AV = +2, Rf = 348Ω: Vcc = + 5V, RL = 100Ω unless specified) PARAMETERS Ambient Temperature CONDITIONS CLC416AJ TYP +25˚C 120 52 30 0.1 0 0.3 0.01 0.03 4.3 22 3 400 700 -80 -80 -65 -57 5 12 3 72 1 30 100 3 1 17 52 50 3.9 6 1 ±2.2 +3.5,-2.9 +4.0,-3.4 60 0.06 MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C 65 40 15 0.7 0.3 0.6 0.04 0.08 6.5 30 12 300 45 36 0.8 0.6 0.7 0.04 0.11 7.2 38 12 260 45 35 1.0 0.6 0.7 0.04 0.12 7.4 41 12 250 UNITS NOTES FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 1.0Vpp Vout < 5.0Vpp ±0.1dB bandwidth Vout < 1.0Vpp gain flatness Vout < 1.0Vpp peaking DC to 200MHz rolloff 1MHz non-inverting current >1MHz crosstalk, input referred 2Vpp, 10MHz STATIC DC PERFORMANCE input offset voltage average drift input bias current average drift input bias current average drift power supply rejection ratio common-mode rejection ratio supply current per channel -55 -50 6.3 15 3.8 66 5 900 5 47 45 4.5 3 2 ±1.8 +3.1/-2.8 +3.9/-3.3 44 0.2 -50 -45 6.6 16 4.0 66 7 50 1600 8 6 40 47 45 4.6 2.4 2 ±1.7 +2.9/-2.7 +3.8/-3.2 38 0.25 -47 -45 6.7 17 4.2 66 8 50 2800 11 8 45 45 43 4.9 1 2 ±1.5 +2.4/-1.7 +3.7/-2.8 20 0.4 A A A non-inverting inverting DC DC RL= ∞ A MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting common mode input range output voltage range RL = 100Ω output voltage range RL = ∞ output current output resistance, closed loop Recommended gain range +1 to +40V/V Transistor count = 110 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings supply voltage Iout is short circuit protected to ground common-mode input voltage maximum junction temperature storage temperature range lead temperature (soldering 10 sec) ESD rating (human body model) ±7V ±Vcc +175˚C -65˚C to +150˚C +300˚C 1000V Notes 1) At temps < 0˚C, spec is guaranteed for RL = 500Ω. A) J-level: spec is 100% tested at +25˚C. Ordering Information Model CLC416AJP CLC416AJE Temperature Range -40˚C to +85˚C -40˚C to +85˚C Description 8-pin PDIP 8-pin SOIC Package Thermal Resistance Package Plastic (AJP) Surface Mount (AJE) θJC 80°C/W 95°C/W θJA 95°C/W 115°C/W http://www.national.com 2 CLC416 Typical Performance Characteristics (Vcc = ±5V, Av = +2, Rf = 348Ω, RL = 100Ω; Frequency Response Normalized Magnitude (1dB/div) Vo = 0.5Vpp unless specified) Inverting Frequency Response Normalized Magnitude (1dB/div) Av = 1 Rf = 1.65kΩ Av = 2 Rf = 348Ω Vo = 0.5Vpp Frequency Response vs. RL Vo = 1Vpp Av = +2 Phase (deg) Av = -2 Rf = 348Ω Av = -1 Rf = 2kΩ Av = -4 Rf = 255Ω Magnitude (1dB/div) Phase (deg) 0 -90 -180 -270 -360 -450 Phase (deg) RL = 100Ω RL = 1kΩ RL = 50Ω 0 -90 -180 -270 Av = -10 Rf = 200Ω RL = 1kΩ 0 -90 -180 -270 -360 -450 Av = 10 Rf = 100Ω Av = 4 Rf = 200Ω -360 -450 -540 -630 RL = 100Ω RL = 50Ω 1 10 100 1 10 100 1 10 100 Frequency (MHz) Frequency Response vs. Vout Av = +2 Frequency (MHz) Frequency Response vs. CL 130 Vo = 1Vpp Rs = 107Ω CL = 10pF Rs = 39.25Ω CL = 47pF Rs = 27.4Ω CL = 100pF Rs 348Ω 348Ω CL 1k Frequency (MHz) Open Loop Transimpedance Gain, Z(s) 200 160 Gain Magnitude (1dB/div) 1Vpp 2Vpp 5Vpp 0.2Vpp Magnitude (1dB/div) 20 log [|Vo/|i|] (dBΩ) 110 90 Phase Phase (deg) 120 80 - Rs = 8Ω CL = 1000pF 70 50 30 Ii CLC416 + Vo 100Ω 40 0 1 10 100 1 10 100 1k 10k 100k 1M 10M 100M Frequency (MHz) Maximum Output Voltage vs. RL 4 120 Frequency (MHz) Recommended Rs vs. Capacitive Load -40 Frequency (Hz) 2nd & 3rd Harmonic Distoration Vo = 2Vpp 3rd, RL = 100Ω Maximum Output Voltage (V) Distortion Level (dBc) 100 2 80 0 -50 -60 Rs (Ω) 60 40 2nd, RL = 100Ω -70 2nd, RL = 1kΩ -2 20 -4 0 100 200 300 400 500 600 0 10 100 1000 -80 -90 1 3rd, RL = 1kΩ 10 Load (Ω) 2nd Harmonic Distortion vs. Pout -55 50Ω Po 50Ω CL (pF) 3rd Harmonic Distortion vs. Pout -40 10MHz 50Ω Po 50Ω Frequency (MHz) Differential Gain & Phase 0.1 0.09 10MHz 0.30 0.27 0.24 0.21 0.18 Phase Negative Sync Gain Negative Sync -60 Distortion (dBc) -65 -70 -75 -80 -85 -90 -10 Distortion (dBc) 348Ω 348Ω -50 5MHz 348Ω 348Ω 0.08 0.07 Gain (%) -60 -70 -80 1MHz 5MHz Phase (deg) 0.06 0.05 0.04 0.03 0.02 0.01 0 Phase Positive Sync Gain Positive Sync 0.15 0.12 0.09 0.06 0.03 0 4 1MHz 500kHz -90 -100 500kHz -5 0 5 10 -10 -5 0 5 10 1 2 3 Output Power (dBm) Small Signal Pulse Response 0.08 0.06 Av = +1 Output Power (dBm) Large Signal Pulse Response 2 Av = +2 Number of 150Ω Loads PSRR and CMRR 60 PSRR Output Voltage (V) PSRR/CMRR (dB) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 Av = -1 Output Voltage (V) 1 50 40 30 20 10 CMRR 0 -1 Av = -2 -2 Time (5ns/div) Time (5ns/div) 10k 100k 1M 10M 100M Frequency (Hz) 3 http://www.national.com CLC416 Typical Performance Characteristics (Vcc = ±5V, Av = +2, Rf = 348Ω, RL = 100Ω; unless specified) Typical DC Errors vs. Temperature 6 1 100 Equivalent Input Noise 100 1.0 0.8 Power Derating Curves Noise Voltage (nV/√Hz) Noise Current (pA/√Hz) Offset Voltage (mV) 5 4 IBN Bias Current (µA) 0 -1 3 2 VIO IBI Power (W) Inverting Current = 12pA/√Hz 0.6 0.4 AJP 10 Voltage = 5nV/√Hz Non-Inverting Current = 3pA/√Hz 10 -2 -3 AJE 0.2 0 1 1 100 1k 10k 100k 1M 10M 0 20 40 60 80 100 120 140 160 180 1 -50 0 50 100 Temperature (°C) Frequency (Hz) Ambient Temperature (°C) CLC416 OPERATION Description The CLC416 is a dual current feedback amplifier with the following features: Differential gain and phase errors of 0.01% and 0.03° into a 150Ω load s Low, 3.9mA, supply current per amplifier s The professional video quality differential gain and phase errors and low power capabilities of the CLC416 make this product a good choice for video applications. Gain The non-inverting and inverting gain equations for the CLC416 are as follows: Non-inverting Gain: 1+ Inverting Gain: − Rf Rg Rf Rg Feedback Resistor Selection The feedback resistor, Rf, determines the loop gain and frequency response of a current feedback amplifier. Optimum performance of the CLC416, at a gain of +2V/V, is achieved with Rf equal to 348Ω. The frequency response plots in the typical performance section illustrate the recommended Rf for several gains. Within limits, Rf can be adjusted to optimize the frequency response. Decrease Rf to peak frequency response and extend bandwidth s Increase Rf to roll off frequency response and reduce bandwidth s As a rule of thumb, if the recommended Rf is doubled, the bandwidth will be cut in half. Channel Matching Channel matching and crosstalk efficiency are largely dependent on board layout. The layout of National’s dual amplifier evaluation boards are designed to produce optimum channel matching and isolation. Typical channel matching for the CLC416 is shown in Figure 2. g Channel A Where Rf is the feedback resistor and Rg is the gain setting resistor. Figure 1 shows the general non-inverting gain configuration including the recommended bypass capacitors. +Vcc 6.8µF Magnitude (0.5dB/div) Channel B Phase (deg) Vin Rin + - 0.1µF Vo Rf 0.1µF RL Channel A 0 Channel B Av = +2 RL = 100Ω Vo = 2Vpp -90 -180 -270 -360 -450 CLC416 Rg 1 10 100 Frequency (MHz) 6.8µF -Vcc Figure 2: Channel Matching The CLC416’s channel-to-channel isolation is better than 70dB for input frequencies of 4MHz. Input referred crosstalk vs. frequency is illustrated in Figure 3. Figure 1: Recommended Non-Inverting Gain Circuit http://www.national.com 4 -20 -40 Crosstalk (dB) evaluation boards for the CLC416 (CLC730038 - DIP, CLC730036 - SOIC) and suggests their use as a guide for high frequency layout and as an aid for device testing and characterization. Supply bypassing is required for best performance. The bypass capacitors provide a low impedance return current path at the supply pins. They also provide high frequency filtering on the power supply traces. Other layout factors play a major role in high frequency performance. The following are recommended as a basis for high frequency layout: 1. Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies. 2. Place the 6.8µF capacitors within 0.75 inches of the power pins. 3. Place the 0.1µF capacitors within 0.1 inches of the power pins. 4. Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance. 5. Minimize all trace lengths to reduce series inductances. Additional information is included in the evaluation board literature. SPICE Models SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for National’s monolithic amplifiers that: Support Berkeley SPICE 2G and its many derivatives s Reproduce typical DC, AC, Transient, and Noise performance s Support room temperature simulations s -60 -80 -100 -120 1 10 100 Frequency (MHz) Figure 3: Input Referred Crosstalk vs. Frequency Driving Cables and Capacitive Loads When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC416 will improve stability. The Rs vs. Capacitive Load plot, in the Typical Performance section, gives the recommended series resistance value for optimum flatness at various capacitive loads. Power Dissipation The power dissipation of an amplifier can be described in two conditions: Quiescent Power Dissipation PQ (No Load Condition) s Total Power Dissipation PT (with Load Condition) s The following steps can be taken to determine the power consumption for each CLC416 amplifier: 1. Determine the quiescent power PQ = Icc (VCC - VEE) 2. Determine the RMS power at the output stage PO = (Vcc - Vload) (Iload), where Vload and Iload are the RMS voltage and current across the external load. 3. Determine the total RMS power PT = PQ + PO Add the total RMS powers for both channels to determine the power dissipated by the dual. The maximum power that the package can dissipate at a given temperature is illustrated in the Power Derating curves in the Typical Performance section. The power derating curve for any package can be derived by utilizing the following equation: (175° − Tamb) P= θ JA where: Tamb = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) Layout Considerations A proper printed circuit layout is essential for achieving high frequency performance. National provides 5 The readme file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for National’s Op Amps, contains schematics and a reproduction of the readme file. Applications Circuits Instrumentation Amplifier An instrumentation circuit is shown on the front page and reproduced in Figure 4. The DC CMRR can be fine tuned by adjusting R1. V1 + 1/2 CLC416 348Ω 348Ω - 348Ω Vout = 3(V2 - V1) 348Ω 348Ω 1/2 CLC416 348Ω CLC405 + R1 348Ω - V2 + Figure 4: Instrumentation Amplifier http://www.national.com CLC416 Dual Low-Power, 120MHz Op Amp Differential Line Receiver Figure 5 illustrates a Differential Line Receiver. The circuit will convert differential signals to single-ended signals. R R 1/2 CLC416 C 1/2 CLC416 + - R R - R R R - R +Vin R + Av = -1V/V R -Vin R 1/2 CLC416 - Ro Vo = 2Vin Vin R1 C + 1/2 CLC416 + CLC405 + Av = -1V/V Vo - R= 1 2πfr C R1 = QR Rf Figure 5: Differential Line Receiver Bandpass Filter Figure 6 illustrates a low-sensitivity bandpass filter and design equations. This topology utilizes the CLC416’s closely matched amplifiers to obtain low op-amp sensitivity at high frequencies. The CLC405 is used as a buffer to obtain low output impedance. The overall circuit gain is unity. For additional gain, the CLC405 can be configured as a non-inverting amplifier. To design the filter, choose C and then determine values for R and R1 based on the desired resonant frequency (fr) and Q factor. Figure 7 illustrates a bandpass filter with Q = 10 and fr = 1MHz. The component values used are listed below: R1 = 4.9kΩ R = 499Ω C = 330pF Rf = 2kΩ Figure 6: Bandpass Filter Topology 0 1.8dB 935kHz Magnitude (dB) -10 -20 -30 -40 1 10 Frequency (MHz) Figure 7: Bandpass Response Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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